Data Patterns — Interview Prep Guide

Data Patterns (India) Ltd.

Hardware / Electronics Engineer (Fresher)
Interview Preparation Guide

Built from confirmed candidate/interview reports + core ECE syllabus

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 Data Patterns — Interview Prep Guide

0. What's Actually Confirmed About This Interview

This section is honest about sourcing. There isn't a large public archive of leaked Data Patterns questions the way there is for
TCS/Infosys. Below is what's directly supported by candidate reports (Glassdoor, campus interview write-ups) and the
company's own job postings — not invented.

Confirmed process
• Round 1 — Written Test: Aptitude + Technical (Electronics). Candidate reports describe it as 'basics-heavy' — digital
circuits, circuit analysis, op-amps.
• Round 2 — Technical Interview (face-to-face, usually Chennai/Siruseri): core electronics fundamentals, your resume
and projects, and increasingly for hardware roles, embedded/interface knowledge (I2C, SPI, UART, USB, PCIe, power
supplies).
• Round 3 — HR Interview: mostly personal/family background, willingness to relocate, and general fit questions —
described as low-pressure relative to the technical rounds.

Confirmed interviewer behavior

• Multiple independent reports say the technical round is fundamentals-first, not trick questions — 'anyone strong in
basics can clear it with ease.'
• Interviewers probe depth on whatever you list on your resume — projects are a guaranteed topic, not optional prep.
• No reports of case-study style whiteboard design challenges for freshers (that's more common at Google/large MNC
hardware roles) — Data Patterns fresher rounds skew toward verbal fundamentals + project defense.

What this means for your prep

• Depth on fundamentals beats breadth on exotic topics. A clean, confident answer on op-amps/BJT/digital logic matters
more than knowing niche VLSI trivia.
• Your STM32/FPGA/embedded/PCB projects are your biggest asset — expect 15-20 minutes of the technical round to
be about them specifically.
• Communication protocols (UART/SPI/I2C) are explicitly named in the company's own hiring postings — treat these as
near-guaranteed.

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1. Priority Roadmap
Weighted by: (a) explicit mention in Data Patterns' own syllabus/job postings, (b) frequency in candidate reports, (c) how
core it is to any ECE hardware fundamentals check.

★★★★★ Must Know

Near-certain to appear. Master these cold.

Topic Why

Op-Amps Explicitly in written syllabus; most-cited topic in candidate reports

for technical round

Diodes & Transistors (BJT) Core written syllabus item; foundational for every follow-up question

Digital Logic (gates, FF, K-map, Explicit syllabus item; 'basics of digital circuits' cited directly by
mux/demux) candidates

Microcontroller fundamentals Named directly in company job posting

ADC / DAC Named directly in company job posting

UART / SPI / I2C Named directly in company job posting under embedded hardware
interfaces

Your own projects Guaranteed 15-20 min of technical round per every report
(STM32/FPGA/embedded/PCB)

★★★★ Important
Comes up frequently, usually as follow-up or written-test filler.

Topic Why

Circuit theory (Ohm's, KVL/KCL, Standard written-test filler across all ECE campus drives
Thevenin/Norton, dividers)

RC/RL/RLC transient & frequency response Tests real circuit intuition, common follow-up after op-amp
questions

MOSFET basics (regions, as a switch) Increasingly asked alongside BJT for comparison questions

Number systems, Boolean algebra Standard written test filler

★★★ Moderate
Topic Why

Filters (low-pass/high-pass, active/passive) Occasional follow-up to op-amp questions

Instrumentation/differential/summing Named in syllabus but less frequently probed than basic op-
amplifiers amp configs

Power supplies (linear vs switching, LDO) Named in job posting; relevant if you mention power
projects

Verilog/FPGA specifics Relevant mainly if it's on your resume — then it becomes

must-know for YOU specifically

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★★ Low Priority
• Deep VLSI (fabrication, layout) — unless you've listed it as a specific project skill
• Advanced sensor theory beyond basic transducer principles
• Memory architecture deep-dives (cache hierarchies etc.) — more relevant to software roles

★ Skip Unless Time Permits

• RF/microwave engineering, advanced power electronics topologies (buck/boost converter design math) — not indicated
anywhere in the fresher ECE syllabus for this role

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2. Study Plans
Pick whichever matches your actual runway. Each plan assumes ~5-6 focused hours/day. Do not try to do more than one plan
— pick one and commit.

7-Day Plan
Day Focus

Day 1 Diodes, BJT, MOSFET — theory + numericals. Redraw every characteristic curve from
memory.

Day 2 Op-Amps — all configs (inverting, non-inverting, follower, summing, differentiator,

integrator). Practice gain derivations.

Day 3 Digital logic — gates, K-maps, flip-flops, counters, mux/demux. Do truth tables by hand,
timed.

Day 4 Microcontrollers + ADC/DAC + UART/SPI/I2C — know differences (SPI vs I2C

wiring/speed/master-slave) cold.

Day 5 Circuit theory — Thevenin/Norton, dividers, RC/RL/RLC. Do 15-20 numericals.

Day 6 Deep-dive your OWN projects. Prepare a 2-min pitch per project + anticipate 5 follow-ups
each.

Day 7 Full mock interview + HR prep + light revision only. No new topics.

5-Day Plan
Day Focus

Day 1 Diodes, BJT, MOSFET, Op-Amps (combine — these are most-tested)

Day 2 Digital logic (gates, K-map, flip-flops, mux/demux) + number systems

Day 3 Microcontrollers, ADC/DAC, UART/SPI/I2C — must-know cold by end of today

Day 4 Circuit theory numericals + your own projects deep-dive

Day 5 Mock interview + HR prep + cheat sheet review only

3-Day Plan
Drop ★★★ and ★★ topics entirely. Focus only on ★★★★★ and ★★★★.

Day Focus

Day 1 Op-Amps + Diodes + BJT/MOSFET — theory, common configs, quick

numericals

Day 2 Digital logic essentials + Microcontroller + ADC/DAC + UART/SPI/I2C

Day 3 (morning) Your own projects — prepare pitch + follow-ups

Day 3 (afternoon/eve) Mock interview + cheat sheet + HR prep

1-Day Plan — Maximum Yield Only

Do NOT attempt full topic coverage. Use the Cheat Sheet (Section 9) as your spine for today. Priority order if time is short:

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• 1. Your own projects — this is guaranteed and fully in your control. Prepare it first.
• 2. Op-Amp configs + Diode/BJT basics (highest-frequency written + interview topic)
• 3. UART vs SPI vs I2C differences (commonly asked as a direct comparison question)
• 4. Digital logic basics — gates, flip-flops, one K-map example
• 5. Skim the Cheat Sheet once more before sleeping. Do not start new topics after 9pm.

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3. Topic Deep-Dives (★★★★★ and ★★★★ topics)

Full explanations for moderate/low topics would dilute your prep time — covered briefly in Section 3.9. These deep-dives
focus on what's actually likely to be asked.

3.1 Operational Amplifier

Definition: A high-gain DC-coupled differential amplifier IC with two inputs (inverting -, non-inverting +) and one output.
Working principle: Ideal op-amp: infinite open-loop gain, infinite input impedance, zero output impedance. In closed-loop
negative feedback, the 'virtual short' concept applies: V+ ≈ V- .

Circuit: Inverting Amplifier

Rf
___
| |
Vin--Rin--+--|>o--+--- Vout
| | |
+--+----+
(- input) (feedback via Rf)
Formula: Vout = -(Rf/Rin) x Vin | Non-inverting: Vout = (1 + Rf/Rin) x Vin | Voltage follower: Vout = Vin (Rf=0,
Rin=∞)
Applications: Signal amplification, filters, integrators/differentiators, ADC front-ends, instrumentation circuits
Advantages: High input impedance, low output impedance, precise gain control via resistors, versatile
Disadvantages: Bandwidth limited by gain-bandwidth product, real op-amps have offset voltage/bias current errors, slew
rate limits

Common Interview Questions

• Q: Why is the inverting input called 'virtual ground' but not actually grounded? A: It sits at 0V due to feedback forcing
V- = V+ = 0V, but draws no current to ground — it's a virtual, not physical, connection.
• Q: What happens if you remove the feedback resistor? A: Op-amp goes into open-loop — output saturates to +Vsat or -
Vsat (behaves like a comparator).
• Q: Derive gain of a non-inverting amplifier. A: Walk through virtual short, current through Rin and Rf being equal,
solve for Vout/Vin.
• Q: Difference between open loop and closed loop op-amp? A: Open loop = no feedback, gain is huge/unstable (used as
comparator); closed loop = feedback added, gain is controlled/stable.
Numerical example: Inverting amp, Rin=1k, Rf=10k, Vin=0.5V → Vout = -(10k/1k)*0.5 = -5V
Common mistakes: Forgetting the negative sign in inverting config; confusing which input is virtual ground; assuming ideal
op-amp always applies (interviewers may probe real limitations)
Memory trick: 'Non-inverting always ≥ 1x gain (1 + Rf/Rin), inverting can be < 1x (just -Rf/Rin)'
Follow-ups to expect: What is slew rate? What is CMRR? Why do we use a differential amplifier for sensor signals?

3.2 Diodes & Transistors (BJT)

Definition: Diode: a two-terminal PN junction device allowing current in one direction. BJT: a 3-terminal current-controlled
device (NPN/PNP) used for amplification/switching.
Working principle: Diode conducts when forward biased (P-side +) beyond ~0.7V (Si) barrier potential. BJT: small base
current controls larger collector current (Ic = β x Ib) when in active region.

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BJT Regions
Region Condition Use

Cutoff Both junctions reverse biased Switch OFF

Active BE forward, BC reverse Amplification

Saturation Both junctions forward biased Switch ON

Formula: Diode: Id = Is(e^(Vd/nVt) - 1). BJT: Ic = βIb, Ie = Ic + Ib, α = β/(β+1)
Applications: Diodes: rectification, voltage regulation (Zener), protection (TVS/flyback). BJT: amplifiers, switches,
oscillators
Advantages/Disadvantages: BJT: high gain but temperature-sensitive and current-controlled (draws base current, unlike
MOSFET's voltage control)

Common Interview Questions

• Q: Why does a Zener diode operate in reverse breakdown deliberately? A: Its breakdown voltage is sharp and stable,
used for voltage regulation/reference.
• Q: Difference between CE, CB, CC configurations? A: CE = high voltage & current gain (most common, 180° phase
shift); CB = high voltage gain, low input impedance, no phase shift; CC (emitter follower) = high current gain, ~unity
voltage gain, no phase shift, high input/low output impedance.
• Q: Why use a transistor as a switch, and what region does it operate in? A: Cutoff (OFF) and Saturation (ON) — avoids
the active/linear region entirely for clean digital switching.
Numerical example: If β=100 and Ib=20µA, Ic = 100 x 20µA = 2mA, Ie = 2.02mA
Common mistakes: Mixing up which junction is forward/reverse biased per region; forgetting Ie = Ic + Ib; confusing BJT
(current-controlled) with MOSFET (voltage-controlled)
Memory trick: 'CE = Common Everything (gain in both V & I), CC = Common Current only (follower), CB = Common
Voltage only'

3.3 Digital Logic Fundamentals

Definition: Circuits operating on binary signals using logic gates (AND, OR, NOT, NAND, NOR, XOR, XNOR),
combinational (mux/demux/encoder/decoder) and sequential (flip-flops/counters) building blocks.
Working principle: Combinational logic: output depends only on current inputs. Sequential logic: output depends on current
inputs AND stored state (memory via flip-flops).

Common Interview Questions

• Q: Why is NAND called a 'universal gate'? A: Any logic function (AND, OR, NOT) can be built using only NAND
gates — used for fabrication simplicity/cost.
• Q: Difference between latch and flip-flop? A: Latch is level-triggered (transparent while enable is high); flip-flop is
edge-triggered (changes only at clock edge) — flip-flops are used for reliable synchronous designs.
• Q: SR flip-flop's invalid state? A: When S=1, R=1 simultaneously — output becomes undefined/race condition, hence
avoided in practice (JK flip-flop fixes this).
• Q: Difference between multiplexer and demultiplexer? A: MUX selects one of many inputs to a single output (many-to-
one); DEMUX routes one input to one of many outputs (one-to-many), both using select lines.
Common mistakes: Confusing MUX/DEMUX direction; forgetting SR flip-flop's invalid state; miscounting select lines
needed (2^n inputs need n select lines)
Memory trick: 'MUX = Many-to-one (like a multi-lane road merging), DEMUX = one-to-Many (like a road splitting)'
Follow-ups: Design a 4:1 MUX using 2:1 MUX. Draw a JK flip-flop truth table. What is race-around condition in JK flip-
flop and how is it solved (master-slave JK)?

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3.4 Microcontrollers, ADC/DAC, and Communication Protocols

Definition: Microcontroller: single-chip computer (CPU + memory + peripherals) for embedded control. ADC converts
analog signal to digital code; DAC does the reverse.

Protocol comparison — expect this exact question

Feature UART SPI I2C

Wires 2 (TX, RX) 4 (MOSI, MISO, SCK, CS) 2 (SDA, SCL)

Speed Slower (~1 Mbps typical) Fastest (10s of Mbps) Moderate (100k-3.4M
bps)

Topology Point-to-point Single master, multiple slaves Multi-master, multi-

(needs a CS per slave) slave (addressed)

Sync Asynchronous (needs baud Synchronous (clock line) Synchronous (clock

rate match) line)
Applications: ADC: sensor reading (temperature, audio input). DAC: audio output, control signals. UART: debug
console/GPS modules. SPI: fast peripherals (flash, displays). I2C: sensors, EEPROMs on a shared bus

Common Interview Questions

• Q: Why does I2C need pull-up resistors but SPI doesn't? A: I2C lines are open-drain (devices only pull low, never drive
high) — pull-ups provide the high state; SPI uses push-pull drivers.
• Q: What is resolution in ADC, and how does it affect accuracy? A: Number of bits determines discrete levels (2^n) —
an 8-bit ADC has 256 levels; higher resolution = finer voltage steps = better accuracy.
• Q: Explain successive approximation ADC. A: Uses a DAC + comparator in a binary search algorithm to converge on
the input voltage in n clock cycles for n-bit resolution.
• Q: What's the difference between a microprocessor and microcontroller? A: Microprocessor is just the CPU (needs
external RAM/ROM/peripherals); microcontroller integrates CPU + memory + peripherals on one chip — used for
embedded/dedicated tasks.
Common mistakes: Saying I2C is faster than SPI (it's not); forgetting SPI needs a separate CS line per slave; confusing
sampling rate with resolution
Memory trick: 'UART = Uses Any wiRing Talk (async, 2 wire) — SPI = Speedy Pin-Intensive (fast, more wires) — I2C =
Its 2 wires Connect many (multi-device, address-based)'
Follow-ups: How would you interface a sensor to your STM32 using I2C? What's the difference between blocking and
interrupt-driven UART reads? What's DMA and why use it with ADC?

3.5 Circuit Theory (Ohm's/Kirchhoff's, Thevenin/Norton, RC/RL)

Definition: The fundamental laws governing voltage/current relationships in circuits, and simplification techniques
(Thevenin/Norton) for analysis.
Formula: Ohm's Law: V=IR. KVL: sum of voltage drops in a loop = 0. KCL: sum of currents into a node = sum out.
Thevenin: any linear circuit reduces to Vth in series with Rth. RC time constant: τ=RC. RL: τ=L/R

Common Interview Questions

• Q: State and derive maximum power transfer theorem. A: Max power is delivered to load when RLoad = RThevenin
(source impedance matched).
• Q: What happens to capacitor voltage over time in an RC charging circuit? A: Exponential rise: Vc(t) = V(1 -
e^(-t/RC)), reaches ~63% at one time constant, ~99% after 5τ.
• Q: Difference between Thevenin and Norton equivalents? A: Thevenin = voltage source + series resistance; Norton =
current source + parallel resistance; they're interconvertible (Vth = IN x Rth).
Numerical example: R1=2Ω, R2=4Ω in series with 12V source: I = 12/(2+4) = 2A. Voltage divider: V_R2 = 12 x (4/6) =
8V

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Common mistakes: Sign errors in KVL loop direction; forgetting to deactivate sources correctly when finding Thevenin
resistance (short voltage sources, open current sources)

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3.9 Brief Notes — Moderate Priority Topics

MOSFET: Voltage-controlled (gate, no gate current in steady state), 3 regions: cutoff, triode/linear, saturation. Used as
switch in digital logic (CMOS) due to near-zero static power.
Filters: Low-pass = passes below cutoff freq (RC: fc = 1/2πRC); High-pass = passes above cutoff. Active filters use op-amps
for gain + no loading effect.
Instrumentation Amplifier: 3 op-amp design for high CMRR, used for amplifying small differential signals (sensor
bridges) while rejecting common-mode noise.
Power Supplies: Linear regulators (LDO): simple, low noise, but low efficiency (dissipates as heat). Switching regulators
(buck/boost): high efficiency, more complex, some switching noise.

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4. Project-Based Interview Prep

This is your highest-leverage prep area — it's guaranteed to come up and it's the one section where you have full control over
the outcome.

Why interviewers focus here

• It reveals whether you actually understood your project or just followed a tutorial/copied a teammate's work
• It tests whether you can explain technical decisions, not just describe what the project 'does'
• It's a natural way to probe depth on protocols/components you claim to know

Prepare for each project you list

Question type Example

What & why What does the project do, and why did you choose this approach over
alternatives?

Component choice Why did you choose STM32 over Arduino/ESP32 for this? Why this specific
sensor/protocol?

Debugging What was the hardest bug you hit, and how did you find/fix it? (Have a
REAL specific story ready)

Depth probe Walk me through exactly how data moves from the sensor to your
output/display

Failure/limitation What would you improve if you did this again?

Specific prep by your listed skills

STM32 projects: Be ready to explain: clock configuration, which peripherals you used (GPIO/timers/ADC/UART),
interrupt vs polling choice, and any HAL vs register-level work
FPGA/Verilog: Be ready to explain: your design's module hierarchy, testbench approach, synchronous vs combinational
logic choices, and any timing/synthesis issues you hit
Embedded Systems: RTOS vs bare-metal choice if applicable, memory constraints, real-time requirements
PCB Design (KiCad): Layer count, why you placed components as you did, any signal integrity or grounding
considerations, how you handled decoupling capacitors
Raspberry Pi: Difference in role vs your STM32 work — likely to be asked why you used Pi vs MCU for a given task (OS
overhead vs bare-metal control)

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5. Technical Question Bank

A realistic, high-yield bank organized by topic — built to match the priority weighting above rather than padded to hit an
arbitrary count. Quality and relevance over quantity.

5.1 Electronics Basics & Circuit Theory

Q1. State Kirchhoff's Current and Voltage Laws.
Expected answer: KCL: sum of currents entering a node = sum leaving (charge conservation). KVL: sum of voltage drops
around any closed loop = 0 (energy conservation).
Possible follow-up: Apply KVL to a two-loop circuit and solve for currents.
Difficulty: Easy
Q2. Explain Thevenin's theorem and when you'd use it.
Expected answer: Any linear two-terminal network can be replaced by a single voltage source Vth in series with resistance
Rth — useful for simplifying analysis when you only care about one branch/load.
Possible follow-up: How do you find Rth when there are dependent sources?
Difficulty: Medium
Q3. What is the significance of the time constant in RC circuits?
Expected answer: τ=RC is the time to reach ~63.2% of final value during charging (or decay to 36.8% during discharge);
after 5τ the circuit is considered settled.
Possible follow-up: How does τ change if you double R and halve C?
Difficulty: Easy
Q4. Differentiate impedance and reactance.
Expected answer: Impedance (Z) is total opposition to AC current (resistance + reactance, complex number). Reactance (X)
is the opposition from capacitors/inductors only (frequency-dependent, no energy dissipation).
Difficulty: Medium

5.2 Analog Electronics

Q1. Derive the gain of an inverting amplifier.
Expected answer: Using virtual ground (V- = 0) and equal currents through Rin and Rf: Vout = -(Rf/Rin) x Vin.
Possible follow-up: What if Rf is replaced with a capacitor?
Difficulty: Medium
Q2. What is CMRR and why does it matter?
Expected answer: Common Mode Rejection Ratio measures an amplifier's ability to reject signals common to both inputs
(noise) while amplifying the differential signal — critical in instrumentation amps for noisy sensor environments.
Difficulty: Medium
Q3. Explain the working of a Zener diode voltage regulator.
Expected answer: Zener operates in reverse breakdown at a stable voltage; placed with a series resistor across the load, it
maintains constant output voltage despite input/load variation as long as it stays in breakdown.
Possible follow-up: What happens if load current exceeds the Zener's rated current?
Difficulty: Medium
Q4. Why is a transistor used in saturation/cutoff for switching, not active region?
Expected answer: Active region has high power dissipation (V x I both significant); saturation (Vce≈0) and cutoff (Ic≈0)
minimize power loss, giving clean digital-like ON/OFF behavior.
Difficulty: Medium
Q5. What's the difference between a differentiator and integrator op-amp circuit?

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Expected answer: Differentiator: capacitor at input, resistor in feedback — output proportional to rate of change of input.
Integrator: resistor at input, capacitor in feedback — output proportional to integral of input over time.
Possible follow-up: Why is a pure differentiator noisy in practice?
Difficulty: Hard

5.3 Digital Electronics

Q1. Simplify a given Boolean expression using K-map (interviewer will provide one).
Expected answer: Approach: group adjacent 1s in powers of 2, identify prime implicants, write minimal SOP expression.
Difficulty: Medium
Q2. Design a 1-bit full adder using logic gates.
Expected answer: Sum = A XOR B XOR Cin; Cout = AB + Cin(A XOR B). Two half-adders + OR gate.
Possible follow-up: How would you build a 4-bit adder from this?
Difficulty: Medium
Q3. Explain the difference between synchronous and asynchronous counters.
Expected answer: Synchronous: all flip-flops clocked simultaneously (faster, no ripple delay). Asynchronous (ripple): each
flip-flop clocked by the previous stage's output (simpler but cumulative delay).
Difficulty: Medium
Q4. What is the race-around condition in a JK flip-flop and how is it fixed?
Expected answer: When J=K=1, output toggles continuously within one clock pulse if the pulse width exceeds propagation
delay. Fixed using a master-slave JK flip-flop configuration.
Difficulty: Hard

5.4 Microcontroller & Communication Protocols

Q1. Explain the difference between polling and interrupt-driven I/O.
Expected answer: Polling: CPU repeatedly checks a status flag, wasting cycles. Interrupt: peripheral signals CPU only when
ready, freeing CPU for other tasks — more efficient for infrequent/unpredictable events.
Possible follow-up: When would polling actually be preferable?
Difficulty: Medium
Q2. How does SPI achieve full-duplex communication?
Expected answer: Separate MOSI (master out) and MISO (master in) lines allow simultaneous bidirectional data transfer,
synchronized by the shared clock (SCK).
Difficulty: Medium
Q3. Why does I2C support multiple devices on the same two wires?
Expected answer: Each device has a unique address; the master initiates communication with a specific address, and open-
drain lines allow multiple devices to share the bus without conflict (with pull-up resistors).
Possible follow-up: What happens if two devices have the same address?
Difficulty: Medium
Q4. Explain successive approximation ADC operation.
Expected answer: Uses a comparator and internal DAC in a binary-search algorithm — starts with MSB, compares, keeps or
clears the bit, moves to next bit, converges in n cycles for n-bit resolution.
Difficulty: Hard

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6. Aptitude Prep
Aptitude is the lower-leverage half of the written test — don't over-invest here at the cost of electronics. Below are core
shortcut patterns and worked examples per topic rather than a padded 100-question list; practicing the pattern generalizes
better than memorizing fixed questions.

Percentages
Shortcut: x% of y = (x/100)*y. To find % change: (new-old)/old * 100.
Worked example: Q: 40% of a number is 80. Find the number. A: 0.4x=80 → x=200.

Profit & Loss

Shortcut: Profit% = (SP-CP)/CP * 100. If loss, use CP-SP.
Worked example: Q: CP=500, SP=600. Find profit%. A: (100/500)*100 = 20%.

Time & Work

Shortcut: If A does work in 'a' days, A's 1-day work = 1/a. Combined rate = sum of individual rates.
Worked example: Q: A finishes in 10 days, B in 15 days. Together? A: 1/10+1/15 = 5/30=1/6 → 6 days.

Probability
Shortcut: P(event) = favorable outcomes / total outcomes. For independent events, multiply probabilities.
Worked example: Q: Probability of getting heads twice in 2 coin tosses. A: 1/2 * 1/2 = 1/4.

Clocks
Shortcut: Minute hand moves 6°/min, hour hand 0.5°/min. Angle = |30H - 5.5M|.
Worked example: Q: Angle at 3:15. A: |30*3 - 5.5*15| = |90-82.5| = 7.5°.

Blood Relations & Coding-Decoding

Shortcut: Draw a family tree/diagram for blood relations. For coding, identify the letter-shift or position pattern first with a
known example.
Worked example: Q: If in a code, CAT=DBU (each letter +1), decode DOG. A: EPH.

Direction Sense
Shortcut: Draw the path step by step on paper — don't try to solve in your head.
Worked example: Q: Facing north, turn right, then right again — now facing? A: South.

Data Interpretation
Shortcut: Read the chart/table fully once before answering any sub-question; note units carefully.
Worked example: Practice with 2-3 sample bar/pie chart sets from any aptitude book — the skill is reading speed, not math.

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7. Mock Interview (Live, Not In This Document)

The mock interview needs to be interactive — say the word in our chat and I'll run it properly:
• I'll ask one question at a time, playing a Data Patterns technical interviewer
• After your answer, I'll evaluate it, point out gaps, ask a realistic follow-up, and give a score
• Difficulty increases as you do well — this mirrors how real interviewers probe deeper on strong answers
• We can also run a project-defense mock specifically on your STM32/FPGA/embedded work
Just tell me: 'Start the mock interview' whenever you're ready.

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8. HR Interview Prep
Per candidate reports, Data Patterns' HR round leans toward personal/family background and general fit rather than
aggressive stress-testing.

Core questions to prepare

Question Good approach Common rejection cause

Tell me about yourself. 2-min structured pitch: background → Reciting your resume line by line
key project → why this role fits with no narrative

Why do you want to join Specific: defence/aerospace electronics, Generic 'good company, good
Data Patterns? hands-on hardware work, India's package' answer
strategic electronics sector

Tell me about your family Brief, honest, comfortable — this is Over-sharing or seeming
background. rapport-building, not a test defensive/uncomfortable

Are you willing to relocate to Clear yes/no with reasoning if Vague or evasive answer
Chennai? conditional

What are your strengths and One real weakness + how you're 'I'm a perfectionist' (cliché, sounds
weaknesses? addressing it evasive)

Where do you see yourself in Growing technically within Overly ambitious/unrelated

5 years? hardware/defence electronics domain answer (e.g., switching to
management/MBA immediately)

Body language & communication tips

• Maintain steady eye contact; don't look at the floor when explaining technical concepts
• Sit upright, avoid crossed arms — signals openness
• Pause briefly before answering technical questions — shows you're thinking, not guessing
• If you don't know something, say so directly and reason through what you DO know, rather than bluffing

Common rejection reasons (fresher hardware roles generally)

• Cannot explain their own listed projects beyond a surface level
• Weak fundamentals despite claiming advanced project experience (mismatch is a red flag)
• Unclear about relocation/location constraints
• Overconfidence without substance — bluffing on a topic gets exposed fast in follow-ups

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9. Final 2-Hour Cheat Sheet

Read this section last, right before the interview. Highest-yield only.

Op-Amp formulas
• Inverting: Vout = -(Rf/Rin)Vin
• Non-inverting: Vout = (1+Rf/Rin)Vin
• Voltage follower: Vout=Vin (buffer, high Zin, low Zout)

BJT quick facts

• Ic = βIb, Ie = Ic+Ib
• CE: high gain, 180° phase shift, most common. CC: unity voltage gain, current buffer. CB: no phase shift, low input
impedance
• Switch = cutoff (OFF) + saturation (ON), avoid active region

Protocol comparison (memorize this table)

UART SPI I2C

Wires 2 4 2

Speed Slow Fastest Medium

Type Async Sync Sync

Digital logic quick facts

• NAND & NOR are universal gates
• Latch = level-triggered, Flip-flop = edge-triggered
• 2^n inputs need n select lines (MUX/DEMUX)

Circuit theory quick facts

• τ(RC)=RC, τ(RL)=L/R. 5τ = fully settled
• Max power transfer: RLoad = RThevenin
• Thevenin = V source + series R. Norton = I source + parallel R

Your projects — 30-second reminder

• Have your 2-min pitch memorized for EACH project on your resume
• Know exactly why you made each major design/component choice
• Have one specific debugging story ready with real detail

Final reminders
• Basics > breadth. Confident fundamentals beat shaky advanced knowledge.
• If unsure, reason out loud from first principles rather than guessing silently.
• HR round: be genuine, clear on relocation, and avoid clichéd answers.

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