Computer Performance

Sachin Gajjar
[Link]@[Link]

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Reading Material

• Chapter 4 COMPUTER PERFORMANCE

• Book - Computer Architecture from Microprocessor
to Super Computer by Behrooz Parahami, Oxford
Publications

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Elements of Modern Computer System

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Elements of Modern Computer
System
• Computing Problems
• Numerical, alphanumerical, logical reasoning
• Science, business, machine learning, embedded
applications
• Algorithms and Data Structures
• Operating System
• Allocation/deallocation of resources (CPU, I/O devices,
Memory)
• System Software
• Compiler, Assembler

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Defining Computer Performance
• As users, we expect a higher-performing computer to run our
application programs faster.
• The computer must react immediately, is a universally accepted
indicator of performance
• As longer execution time implies lower performance, we might
write:
• Performance = 1/Execution time
• For end user this execution time is total response time or
turnaround time which includes latency due to scheduling
decisions, work interruptions, I/O queuing delays, and so on.
• This is wall clock time (measured by looking at a wall clock at
the start and termination of a task)

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 Defining Computer Performance
• To filter out effects of such highly variable and hard-to-
quantify factors, CPU execution time is used to define
user-perceived performance:
• Performance = 1/CPU execution time

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 Processor Performance

1
Processor Performance =
CPU Execution Time

Instructions Cycles Seconds

CPU Execution Time = X X
Program Instruction Cycle

(code size, instruction count) (M/C cycles (Time

consumed for required
execution of each for each
instruction, Cycles machine
per instruction cycle)
(CPI))

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 Instruction Cycle/Machine Cycle/T-State

• Instruction Cycle - time to complete 1 instruction

• Machine Cycle – time to complete 1 operation
• T-state – subdivision of operation done in 1 clock period
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Elaborated CPU Execution Time Formula
CPU time = Instructions  (Cycles Per Instruction)  (Seconds Per Cycle)
= Instructions  Average CPI / (Clock Rate)

(i.e Clock Rate = Cycles Per Second = frequency)

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 (i) Instructions:
• Number of instructions executed, not number of
instructions in program (dynamic instruction count)
• Actual Instructions executed, not static code size
• Dynamic instruction count > Static code size (loops,
repeated calls, procedures)
• Determined by
• algorithm (eg. sorting and searching),
• programmer,
• compiler (they do code optimisations),
• Instruction Set Architecture (which instructions
are available) (eg. ARM ADD R1,R2, R3, LSL #2,
DJNZ reg, addr = DEC, CMP, JMP, INC/ADD) 25
Compiler Optimization
GCC, GNU (GNU's Not Unix) Compiler Collection
([Link]

• The GNU Compiler Collection (GCC) includes compilers for C, C++,

Objective-C, Objective-C++, Fortran, Ada, D, and Go, as well as
libraries for these languages (libstdc++,...).
• GCC is free, was originally developed for GNU OS
• Works well on a variety of native and cross targets (including GNU
OS/Linux/Windows)
• Sources are freely available via Git and on gcc website
• GCC 13.1 released [April 2023] – Latest Release

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Compiler Optimization
GCC target Processor Support (more than 60)

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GCC optimization options

gcc -o [executable_name] [source_file].c

gcc –o0 helloworld helloworld.c
Ref: [Link]
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[Link]
(ii) Average CPI
• Cycles Per Instruction
• Is calculated based on the dynamic instruction mix and
knowledge of how many clock cycles are needed to
execute various instructions (or instruction classes-data
transfer, ALU …..)
• Inverse is Instructions Per Cycle - with hardware
support (pipelining) number of instructions per cycle
can be increased
• IPC increases, CPI will decrease and hence the
Execution time will decrease, which in turn increases
Performance

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(iii) Clock rate:
Clock rate: Clock = 1 GHz = 109 cycles / s (cycle time 10–9 s = 1 ns)
200 MHz = 200  106 cycles / s (cycle time = 5 ns)
Clock period

Clock frequency given to the processor

Determined by technology, circuit design

P α f Vdd2
• A high f decreases execution time, increases performance
• f increases, P increases, setting an upper limit to the value of f
that can be had
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 Clock Frequency
• Intel Processor Reference Guide
• [Link]
• Max. Clock Frequency - 3.8 GHz
• 12th Gen Intel® Core™ Mobile Processors – 3.8 GHz
• [Link]
ocessors/core/[Link]

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 Computer Performance
• Number of Instructions depend on ISA, programmer, algorithm,
compiler
• Cannot increase clock frequency beyond a point
• We are left with CPI to increase computer performance
• To decrease CPI, increase IPC, IPC can be increased by pipelining (has
some problems)
• People thought of increasing number of processors and do parallel
processing
• Will it help?

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Amdahl's Law (Parallel Processor )

• Points out some limitations of parallel processing.

• Programs contain certain computations that are
inherently sequential and thus cannot be speeded up
through parallel processing.

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Amdahl's Law (Parallel Processor )
• f = represents fraction of program that can be parallelized to run
in vector computation mode (eg. adding arrays in parallel)
• 1-f represents part of program that runs sequentially.
• T = time required to run program then overall speedup S can be
represented by

(where 1 is original running time of the program and (1-f) +(f/N)

is program's improved execution time with N processors)
• N becomes very large then second term (f/N) approaches to zero
then total execution time is dedicated to sequential part (1-f)
• This is referred as sequential bottleneck
• Can be used to find maximum expected improvement to an
overall system when only a part of the system is parallelized
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 Sequential Bottleneck
• Sequential bottleneck - time spent in sequential execution or
scalar computation becomes a limit to how much overall
performance improvement can be achieved via exploitation of
parallelism.
• As N increases or as machine parallelism increases, performance
will become more and more sensitive to and dictated by the
sequential part of program.
• Overall speedup due to parallel processing is strongly dictated by
sequential part of program as machine parallelism increases

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 Example 1
A processor spends 30% of its time on floating (flp) point addition,
25% on flp mult, and 10% on flp division. Evaluate the following
enhancements, each costing the same to implement:

a. Redesign of the flp adder to make it twice as fast.

b. Redesign of the flp multiplier to make it three times as fast.
c. Redesign the flp divider to make it 10 times as fast.

Solution
Speedup S can be represented by
a. Adder redesign speedup = 1 / [0.7 + 0.3 / 2] = 1.18 [f=0.3, N=2]
b. Multiplier redesign speedup = 1 / [0.75 + 0.25 / 3] = 1.20 [f=0.25, N=3]
c. Divider redesign speedup = 1 / [0.9 + 0.1 / 10] = 1.10 [f=0.1, N=10]

Significant speedup of the divider is not worth the effort

What if both the adder and the multiplier are redesigned? 36

Example 1 (Contd.)

• What if both the adder and the multiplier are

redesigned?
• N=2+3 (adder+multiplier)
• f=0.3+0.25 (adder+multiplier)
• Speedup S can be represented by

• Adder+Multiplier redesign speedup = 1 / [(1-0.55) +

0.55/5] = 1/0.45+0.11=1.78

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 Example -2
Members of a university research group frequently visit the library. Each
library trip takes 20 minutes. The group decides to subscribe to a
handful of publications that account for 90% of the library trips; access
time to these publications is reduced to 2 minutes.

a. What is the average speedup in access to publications?

b. If the group has 20 members, each making 2 weekly trips to the
library, what is the justifiable expense for the subscriptions?
Assume 50 working weeks/yr and $25/h for a researcher’s time.

Solution

a. Speedup in publication access time = 1 / [0.1 (1-0.9) + 0.9 / 10] =

5.26 [f=0.9 (subscription=parallelization), N=improved execution
time=20(original trip time)/2 (new trip time)=10]
b. Time saved = 20  2  50  0.9 (20 – 2) = 32,400 min = 540 h
Cost recovery = 540  $25 = $13,500 = Max justifiable expense
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 Benchmarking
• Benchmarks are real or synthetic programs that are selected or designed
for comparative evaluation of machine performance.
• A benchmark suite is a collection of such programs intended to represent
an entire class of applications (data compression, image processing, etc.)
• Benchmarks facilitate comparison across different platforms and
computer classes.
• They make it possible for computer vendors and independent firms to
evaluate many machines upon their entry into the market and to publish
the benchmarking results for the benefit of users.
• In this way, the user may not need to perform any benchmarking at all.
• Eg. Standard Performance Evaluation Corporation (SPEC) - a vendor
consortium that selects and standardizes benchmark programs submitted
by members or others

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SPEC CPU2000 benchmark suite characteristics

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 Performance Estimation
• Peak Performance
• the absolute highest level of performance that can be got from the system
• expressed in units of instructions per second or IPS, with MIPS (Million
Instructions per Second) and GIPS (Giga Instructions per second) preferred
to keep the numbers small.
• applications that involve floating- point calculations, floating-point
operations per second (FLOPS) is used as the unit, again with megaflops
(MFLOPS) and gigaflops (GFLOPS) preferred.
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Peak Performance =
CPU Execution Time
CPU Execution time = Instructions  Average CPI / (Clock rate)
Peak performance = Clock Rate/Average CPI (If all instructions are of same class)

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Classes of Instructions

• Floating point
• Integer arithmetic
• Non arithmetic
• I/O operations
• Data Transfer
• Logical
• Load/Store
• Jump

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Comparing two machines

• When comparing two machines M1 and M2, notion of relative

performance comes into play.
(Performance of M1)/(Performance of M2)
=Speedup of M1 over M2
= (Execution time of M2)/(Execution time M1)

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 Example 3
Consider two implementations M1 (600 MHz) and M2 (500 MHz) of
an instruction set containing three classes of instructions:
Class CPI for M1 CPI for M2 Comments
F 5.0 4.0 Floating-point
I 2.0 3.8 Integer arithmetic
N 2.4 2.0 Non-arithmetic
a. What are the peak performances of M1 and M2 in MIPS?
b. If 50% of instructions executed are class-N, with the rest divided
equally among F and I, which machine is faster? By what factor?
Solution
Peak performance = Clock Rate/Average CPI
Peak performance will come when CPI is minimum (2 for M1 and M2)
a. Peak MIPS for M1 = 600 / 2.0 = 300; for M2 = 500 / 2.0 = 250

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 Example 3 (Contd.)
b. If 50% of instructions executed are class-N, with the rest divided equally
among F and I, which machine is faster? By what factor?

Peak performance = Clock Rate/Average CPI

Average CPI = Class i fraction (share of class i instructions) x Class i CPI

• Average CPI for M1 = 5.0 / 4 + 2.0 / 4 + 2.4 / 2 = 2.95;

• Average CPI for M2 = 4.0 / 4 + 3.8 / 4 + 2.0 / 2 = 2.95
[50%=1/2, 25%=1/4]
• CPI is same 2.95 so M1 with higher clock rate is faster
→M1 is faster; factor 1.2 (ratio of clock rates 600/500)

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 Contd…
C. Designer of M1 plan to redesign the machine for better performance
with assumptions of part b, which of the following have great
performance impact and why?

1. Using faster floating point unit with double the speed (Class F, CPI = 2.5)
2. Adding Second inter ALU to reduce the integer CPI to 1.20
3. Using faster logic that allows a clock rate of 750 MHz with same CPI

Solution
1. Average CPI = 2.5/4+2.0/4+2.4/2 = 2.325; MIPS = 600/2.325 = 258
2. Average CPI = 5.0/4+1.2/4+2.4/2 = 2.75; MIPS = 600/2.75 = 218
3. MIPS = 750/2.95 = 254

Option 1 (MIPS=258) has greater impact.

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 Contd…

d. Given CPI has included the effect of instruction cache misses at an

average rate of 5%. Each cache miss imposes a 10-cycle penalty (i.e.
adds 10 to the effective CPI of the instruction causing the miss or 0.5
cycle per instruction on the average). A fourth redesign option is to
use a larger instruction cache that would reduce the miss rate from
5% to 3%. How does this compare to the three options in part c?

Solution: With a larger cache, all CPIs are reduced by 0.2 (0.02 (i.e. 2%
reduction in cache miss) X 10 cycle penalty) owing to lower cache miss
rate. Each CPI reduced by 0.2 by increasing cache size.
Average CPI: 4.8/4 + 1.8/4 + 2.2/2 = 2.75
This option is comparable to option 2 of part c.

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 Cont….

e. Characterize application programs that would run faster on M1

than M2. (you can say about the instruction mix in that application)

Hint: Let x, y and 1 – x – y be the fraction of instructions belonging to

classes F, I and N, respectively.
Solution:
Average CPI for M1 = 5.0x + 2.0y + 2.4 (1-x-y) = 2.6x – 0.4y + 2.4
Average CPI for M2 = 4.0x + 3.8y + 2.0 (1-x-y) = 2x + 1.8y + 2
So we are looking for condition under which,
600/(2.6x – 0.4y + 2.4)> 500/(2x + 1.8y + 2)
x/y < 12.8

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Example
Consider two implementations M1 (600 MHz) and M2 (500 MHz)
of an instruction set containing three classes of instructions:
Class CPI for M1 CPI for M2 Comments
F 5.8 5.4 Floating-point
I 2.8 3.8 Integer arithmetic
N 2.4 2.8 Non-arithmetic
a. What are the peak performances of M1 and M2 in MIPS?
b. If 50% of instructions executed are class-N, with the rest divided
equally among F and I, which machine is faster? By what factor?

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 Effect of Instruction Mix on Performance
Consider two applications DC (Data Compression) and RS (Reactor
Simulation) and two machines M1 and M2:
Class Data Comp. Reactor Sim. M1’s CPI M2’s CPI
A: Ld/Str 25% 32% 4.0 3.8
B: Integer 32% 17% 1.5 2.5
C: Sh/Logic 16% 2% 1.2 1.2
D: Float 0% 34% 6.0 2.6
E: Branch 19% 9% 2.5 2.2
F: Other 8% 6% 2.0 2.3
a. Find the effective CPI for the two applications on both machines.
Solution Average CPI = Class i fraction (share of class i instructions) x Class i CPI

a. CPI of DC on M1: 0.25  4.0 + 0.32  1.5 + 0.16  1.2 + 0  6.0 +

0.19  2.5 + 0.08  2.0 = 2.31
DC on M2: 2.54 RS on M1: 3.94 RS on M2: 2.89

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Some more parameters for performance

• Cost
• life-cycle cost, which includes upgrading, maintenance, usage, and other
recurring costs
• the highest-performance machine that is technologically feasible might never
materialize because it is cost-ineffective (has an unacceptably high
cost/performance ratio)
• Compactness (Embedded Systems)
• Power consumption

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Thank You

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