Processor Performance
Prof. Dhaval Shah
Acknowledgement
• Behrooz Parahami, Computer Architecture from
Microprocessor to Super Computer, Oxford (Book
and PPT referred)
Processor Performance
1
Processor Performance =
Execution Time
Instructions Cycles Seconds
Execution Time = X X
Program Instruction Cycle
(code size) (CPI) (cycle time)
Elaboration on the CPU Time Formula
CPU time = Instructions (Cycles per instruction) (Secs per cycle)
= Instructions Average CPI / (Clock rate)
Instructions: Number of instructions executed, not number of
instructions in our program (dynamic count)
Average CPI: Is calculated based on the dynamic instruction mix
and knowledge of how many clock cycles are needed
to execute various instructions (or instruction classes)
Clock rate: 1 GHz = 109 cycles / s (cycle time 10–9 s = 1 ns)
200 MHz = 200 106 cycles / s (cycle time = 5 ns)
Clock period
Amdahl's Law (Parallel Processor )
S = 1/T = 1/ (1-f) + (f/N)
• f = represents fraction of program that can be parallelized to run in
vector computation mode.
• 1-f represents program runs sequentially.
• T = time required to run program then overall speedup S can be
represented by
• N becomes very large then second term approaches to zero then
total execution time is dedicated to sequential part. This is referred
as sequential bottleneck
Example 1
A processor spends 30% of its time on flp addition, 25% on flp mult,
and 10% on flp division. Evaluate the following enhancements, each
costing the same to implement:
a. Redesign of the flp adder to make it twice as fast.
b. Redesign of the flp multiplier to make it three times as fast.
c. Redesign the flp divider to make it 10 times as fast.
Solution
a. Adder redesign speedup = 1 / [0.7 + 0.3 / 2] = 1.18
b. Multiplier redesign speedup = 1 / [0.75 + 0.25 / 3] = 1.20
c. Divider redesign speedup = 1 / [0.9 + 0.1 / 10] = 1.10
What if both the adder and the multiplier are redesigned?
Example -2
Members of a university research group frequently visit the library.
Each library trip takes 20 minutes. The group decides to subscribe
to a handful of publications that account for 90% of the library trips;
access time to these publications is reduced to 2 minutes.
a. What is the average speedup in access to publications?
b. If the group has 20 members, each making two weekly trips to
the library, what is the justifiable expense for the subscriptions?
Assume 50 working weeks/yr and $25/h for a researcher’s time.
Solution
a. Speedup in publication access time = 1 / [0.1 + 0.9 / 10] = 5.26
b. Time saved = 20 2 50 0.9 (20 – 2) = 32,400 min = 540 h
Cost recovery = 540 $25 = $13,500 = Max justifiable expense
Effect of Instruction Mix on Performance
Consider two applications DC and RS and two machines M1 and M2:
Class Data Comp. Reactor Sim. M1’s CPI M2’s CPI
A: Ld/Str 25% 32% 4.0 3.8
B: Integer 32% 17% 1.5 2.5
C: Sh/Logic 16% 2% 1.2 1.2
D: Float 0% 34% 6.0 2.6
E: Branch 19% 9% 2.5 2.2
F: Other 8% 6% 2.0 2.3
a. Find the effective (Average) CPI for the two applications on both
machines.
Solution
a. CPI of DC on M1: 0.25 4.0 + 0.32 1.5 + 0.16 1.2 + 0 6.0 +
0.19 2.5 + 0.08 2.0 = 2.31
DC on M2: 2.54 RS on M1: 3.94 RS on M2: 2.89
Example 3
Consider two implementations M1 (600 MHz) and M2 (500 MHz) of
an instruction set containing three classes of instructions:
Class CPI for M1 CPI for M2 Comments
F 5.0 4.0 Other instructions
I 2.0 3.8 Integer arithmetic
N 2.4 2.0 Non-arithmetic
a. What are the peak performances of M1 and M2 in MIPS?
b. If 50% of instructions executed are class-N, with the rest divided
equally among F and I, which machine is faster? By what factor?
Solution
a. Peak MIPS for M1 = 600 / 2.0 = 300; for M2 = 500 / 2.0 = 250
b. Average CPI for M1 = 5.0 / 4 + 2.0 / 4 + 2.4 / 2 = 2.95;
for M2 = 4.0 / 4 + 3.8 / 4 + 2.0 / 2 = 2.95 → M1 is faster; factor 1.2
Contd…
C. Designer of M1 plan to redesign the machine for better
performance with assumptions of part b, which of the following have
great performance impact and why?
1. Using faster floating point unit with double the speed (Class F, CPI = 2.5)
2. Adding Second inter ALU to reduce the integer CPI to 1.20
3. Using faster logic that allows a clock rate of 750 Mhz with same CPI
Solution
1. Average CPI = 2.5/4+2.0/4+2.4/2 = 2.325; MIPS = 600/2.325 = 258
2. Average CPI = 5.0/4+1.2/4+2.4/2 = 2.75; MIPS = 600/2.75 = 218
3. MIPS = 750/2.95 = 254
Option 1 has greater impact.
Contd…
d. Given CPI has included the effect of instruction cache misses at an
average rate of 5%. Each cache miss imposes a 10-cycle penalty (i.e.
adds 10 to the effective CPI of the instruction causing the miss or 0.5
cycle per instruction on the average). A fourth redesign option is to
use a larger instruction cache that would reduce the miss rate from
5% to 3%. How does this compare to the three options in part c?
Solution: With a larger cache, all CPIs are reduced by 0.2 owing to
lower cache miss rate.
Average CPI: 4.8/4 + 1.8/4 + 2.2/2 = 2.75
This option is comparable to option 2 of part c.
Cont….
e. Characterize application programs that would run faster on M1 than
M2. ( you can say about the instruction mix in that application)
Hint: Let x, y and 1 – x – y be the fraction of instructions belonging to
classes F, I and N, respectively.
Solution:
Average CPI for M1 = 5.0x + 2.0y + 2.4 (1-x-y) = 2.6x – 0.4y + 2.4
Average CPI for M2 = 4.0x + 3.8y + 2.0 (1-x-y) = 2x + 1.8y + 2
So,
600/(2.6x – 0.4y + 2.4) > 500/(2x + 1.8y + 2)
x/y < ?
Example - HW
Consider two implementations M1 (600 MHz) and M2 (500 MHz) of
an instruction set containing three classes of instructions:
Class CPI for M1 CPI for M2 Comments
F 5.8 5.4 Floating-point
I 2.8 3.8 Integer arithmetic
N 2.4 2.8 Non-arithmetic
a. What are the peak performances of M1 and M2 in MIPS?
b. If 50% of instructions executed are class-N, with the rest divided
equally among F and I, which machine is faster? By what factor?
Benchmarking
SPEC2000 Benchmarks
Example - 4
A benchmark suite B1 consists of equal proportion of class-X
and class-Y instructions. Machine M1 and M2, with identical
clocks (1 GHz), have equal performance of 500 MIPS on B1. If
we replace half of class-X instructions in B1 with class-Y
instructions to derive another bench mark suite of B2, M1’s
running time becomes 70% that of M2. If we replace half of
class-Y instructions with class-X instructions to transform B1
into B3, M2 becomes 1.5 times as fast as M1.
i. Assuming x1, y1 and x2, y2 be the average CPI of class-X
and class-Y instructions for M1 and M2 respectively,
compute the CPI for M1 (i.e., x1 and y1) and that of M2 (x2
and y2).
ii. What is the MIPS performance of M1 and M2 on the new
benchmark suites B2 and B3?
iii. What is the maximum speedup of M1 over M2 and for what
instruction mix is it achieved?
iv. Repeat part iii for the performance of M2 relative to M1.
Solution
(I) Assume identical clock rate = 1 GHz ➔ CPI = 1000MHz/500 MIPs = 2
• For 500 MIPS at 1 GHz for benchmark B1 leads to
• 0.5x1 + 0.5y1 = 2 ………………………………………………………. Eq.1
• 0.5x2 + 0.5y2 = 2 ………………………………………………………..Eq.2
• Given half of class-X instructions in B1 is replaced with class-Y
instructions to derive another bench mark suite of B2. such that M1’s
running time = 0.7 of M2’s running time. Thus, For Benchmark B2,
• We have, 0.25x1 + 0.75y1 = 0.7(0.25x2 + 0.75y2)…………………….Eq.3
Similarly for B3
• We have, 0.75x1 + 0.25y1 = 1.5(0.75x2 + 0.25y2)…………………….Eq.4
• Solve Eq. 1 to Eq.4 for x1, y1 (for M1) and x2, y2 (for M2)
• Class X x1 = 2.5 x2 = 1
• Class Y y1 =1.5 y2 = 3
• (ii) MIPS for M1
• MIPS on Benchmark B2 = 1000 MHz/(0.25x1 + 0.75y1) = 1000/(0.25x2.5 +
0.75x1.5) = 571.42 or 571
• MIPS on Benchmark B3 = 1000 MHz/(0.75x1 + 0.25y1) = 1000/0.75x2.5 +
0.25x1.15 = 444.44 or 444
• Similarly, MIPS for M2
• On Bench mark B2
= 1000 MHz/(0.25x2 + 0.75y2) = 1000/(0.25x1 + 0.75x3) = 400
• On Benchmark B3
= 1000/ (0.75x2 + 0.25y2) = 1000/(0.75x1 + .25x3) = 666.67 = 667
(iii) Speedup of M1 over M2 – it is possible when all the instructions are of Y-
type and can be computed as
MIPS M1/ MIPS M2 →1000/1x1.5// 1000/1x3
MIPS M1/ MIPS M2 = 2
• Speedup of M2 over M1 - it is possible when all the instructions are of X-
type and can be computed as
MIPS M2/ MIPS M1 →1000/1x1//1000/1x2.5
MIPS M2/ MIPS M1 = 2.5