JKEDUSPHERE STUDY MATERIAL
Microprocessors &
Microcontrollers
Practice Question Bank
193 Questions | Comprehensive Coverage
8085 • 8086 • 8051 • Memory • Development Tools
Based on JKEdusphere Complete Notes
For Study & Classroom Use
Compiled and Edited by Kaashmir
JKEdusphere © 2026 | All Rights Reserved
Table of Contents
Unit I — Intel 8085 Microprocessor
1.1 Introduction, Pin Diagram & Signals
1.2 Buses, Interrupts & DMA
1.3 Internal Architecture & Registers
1.4 Flag Register
1.5 Machine Cycles & T-States
1.6 Addressing Modes
1.7 Data Transfer Group
1.8 Arithmetic Group
1.9 Logical Group
1.10 Branching, Stack & Subroutines
Unit II — Intel 8086 Microprocessor
2.1 Introduction & Features
2.2 Architecture — EU & BIU
2.3 Register Organization
2.4 Flag Register
2.5 System Buses
2.6 Pin Diagram & Signals
2.7 8085 vs 8086 Comparison
2.8 Instruction Set Overview
Unit III — Semiconductor Memory
3.1 Memory Classification
3.2 Memory Types Compared
3.3 SRAM vs DRAM
3.4 Memory Capacity Calculations
Unit IV — 8051 Microcontroller
4.1 Microprocessor vs Microcontroller
4.2 Block Diagram & Pin Functions
4.3 Memory Organization
4.4 Registers, SFRs & PSW
4.5 Stack of the 8051
4.6 Addressing Modes
4.7 MUL, DIV & DA Instructions
4.8 Interrupts
Unit V — Program Development Tools
5.1 Editor, Compiler, Assembler, Linker & Loader
Numerical & Analytical Questions
Match the Following
True or False
Fill in the Blanks
Microprocessors & Microcontrollers — Practice Question Bank
UNIT I — INTEL 8085 MICROPROCESSOR
8-bit microprocessor | 40-pin DIP | 64KB addressing | 3MHz clock
Section 1.1 Introduction, Pin Diagram & Signals
1 The Intel 8085A is a ___-bit microprocessor in a ___-pin DIP package.
A 8, 40
B 16, 40
C 8, 20
D 16, 20
Answer: A
2 The 8085 multiplexed address/data bus consists of pins:
A A8–A15
B AD0–AD7
C D0–D7
D A0–A7
Answer: B
3 Which signal is used to demultiplex the lower address byte from the data bus?
A RD
B WR
C ALE
D IO/M
Answer: C
4 The 8085 can address a maximum memory of:
A 32 KB
B 64 KB
C 1 MB
D 128 KB
Answer: B
5 Which pin provides the system clock output in the 8085?
A X1
B X2
C CLK OUT
D RESET OUT
Answer: C
6 SID and SOD in the 8085 stand for:
A Serial Input Data and Serial Output Data
B System Input Data and System Output Data
C Signal Input Data and Signal Output Data
D Synchronous Input Data and Synchronous Output Data
Answer: A
Section 1.2 Buses, Interrupts & DMA
7 Which of the following is a non-maskable interrupt in the 8085?
A RST 7.5
B RST 6.5
C TRAP
D INTR
Answer: C
8 The vector address of RST 7.5 is:
A 0024H
B 003CH
C 0034H
D 002CH
Answer: B
9 Which interrupt is both edge and level triggered?
A RST 5.5
B RST 6.5
C RST 7.5
D TRAP
Answer: D
10In DMA operation, which signal does the peripheral use to request the buses?
A HLDA
B HOLD
C INTA
D READY
Answer: B
11What is the priority order (highest to lowest) of 8085 interrupts?
A TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
B INTR > TRAP > RST 7.5 > RST 6.5 > RST 5.5
C TRAP > INTR > RST 7.5 > RST 6.5 > RST 5.5
D RST 7.5 > TRAP > RST 6.5 > RST 5.5 > INTR
Answer: A
12During DMA, the CPU responds to HOLD with:
A INTA
B HLDA
C READY
D RESET
Answer: B
Section 1.3 Internal Architecture & Registers
13The 8085 has how many general-purpose 8-bit registers?
A4
B6
C8
D 10
Answer: B (B, C, D, E, H, L)
14Which register pair in the 8085 is commonly used as a memory pointer?
A BC
B DE
C HL
D SP
Answer: C
15The Program Counter (PC) in the 8085 is:
A 8-bit
B 16-bit
C 32-bit
D 4-bit
Answer: B
16Which register holds one operand and the result of ALU operations?
AB
BC
C Accumulator (A)
DH
Answer: C
17The Temporary Register in the 8085 is:
A User-accessible
B Not user-accessible
C 16-bit
D Used for I/O operations
Answer: B
18The Stack Pointer (SP) in the 8085 points to:
A The bottom of the stack
B The top of the stack
C The middle of the stack
D The program memory
Answer: B
Section 1.4 Flag Register
19How many active flags are present in the 8085 flag register?
A3
B5
C6
D8
Answer: B
20The flag register of the 8085 has how many undefined bits?
A1
B2
C3
D4
Answer: C
21The Parity flag is set when the result has:
A Odd number of 1-bits
B Even number of 1-bits
C Zero 1-bits
D All 1-bits
Answer: B
22After executing 38H + A9H = E1H, what is the value of the Sign flag?
A0
B1
C Undefined
D Depends on previous operation
Answer: B (D7 = 1)
23The Auxiliary Carry flag is used primarily for:
A Binary addition
B BCD arithmetic
C Logical operations
D Shift operations
Answer: B
24If the result of an operation is zero, which flag is set?
A Sign flag
B Zero flag
C Carry flag
D Parity flag
Answer: B
Section 1.5 Machine Cycles & T-States
25A T-state is defined as:
A One complete instruction execution
B One subdivision of an operation in one clock period
C One memory read operation
D One I/O write operation
Answer: B
26The first machine cycle of every instruction is always:
A Memory Read
B Memory Write
C Opcode Fetch
D I/O Read
Answer: C
27How many T-states does an opcode fetch typically take?
A 2 or 3
B 3 or 4
C 4 or 6
D 6 or 8
Answer: C
28A machine cycle typically takes:
A 1–2 T-states
B 3–6 T-states
C 7–10 T-states
D 10–15 T-states
Answer: B
Section 1.6 Addressing Modes
29In which addressing mode is the data byte inside the instruction itself?
A Register
B Immediate
C Direct
D Register Indirect
Answer: B
30The instruction "MOV A, B" uses which addressing mode?
A Immediate
B Register
C Direct
D Implied
Answer: B
31The instruction "LDA 2050H" uses which addressing mode?
A Immediate
B Register
C Direct
D Register Indirect
Answer: C
32The instruction "MOV A, M" uses which addressing mode?
A Immediate
B Register
C Direct
D Register Indirect
Answer: D
33The instruction "CMA" uses which addressing mode?
A Immediate
B Register
C Direct
D Implied / Inherent
Answer: D
Section 1.7 Data Transfer Group
34Which instruction copies data from one register to another?
A MVI
B MOV
C LDA
D STA
Answer: B
35The instruction "LXI H, 2050H" loads:
A 2050H into Accumulator
B 2050H into register pair HL
C 2050H into register H only
D 2050H into Stack Pointer
Answer: B
36Which instruction exchanges the contents of HL and DE?
A XTHL
B XCHG
C SPHL
D LHLD
Answer: B
37The instruction "PUSH B" affects:
A Only the B register
B Both B and C registers
C The stack pointer and memory
D The program counter
Answer: C
38Which instruction copies HL into the Stack Pointer?
A SPHL
B XTHL
C LHLD
D SHLD
Answer: A
Section 1.8 Arithmetic Group
39Which instruction adds the contents of register B to the Accumulator?
A ADI B
B ADD B
C ADC B
D ACI B
Answer: B
40The instruction "ADC C" adds:
A Only register C to A
B Register C and Carry flag to A
C Only Carry flag to A
D Register C and A to memory
Answer: B
41Which 16-bit instruction adds a register pair to HL and affects only the Carry flag?
A INX
B DCX
C DAD
D DAA
Answer: C
42The instruction "DAA" is used after:
A Binary addition
B BCD addition
C Logical AND operation
D Subtraction
Answer: B
43Which instructions do NOT affect any flags?
A INR and DCR
B INX and DCX
C ADD and SUB
D ADC and SBB
Answer: B
44To subtract 45H from 92H using 2's complement, the result is:
A 4DH with CY = 1
B 4DH with CY = 0
C 4EH with CY = 1
D 4EH with CY = 0
Answer: B
Section 1.9 Logical Group
45The instruction "ANA B" performs:
A OR operation
B AND operation
C XOR operation
D NOT operation
Answer: B
46After a logical operation, the Carry flag is:
A Always set
B Always cleared
C Unchanged
D Complemented
Answer: B
47The instruction "CMP B" compares A and B by:
A Adding B to A
B Subtracting B from A and storing result in A
C Subtracting B from A without changing A
D ANDing A with B
Answer: C
48The instruction "RLC" rotates the Accumulator:
A Left, D7 goes to D0 and CY
B Right, D0 goes to D7 and CY
C Left through carry
D Right through carry
Answer: A
49The instruction "CMA" produces:
A 2's complement of A
B 1's complement of A
C A unchanged
D A cleared to 00H
Answer: B
50Which instruction sets the Carry flag?
A CMC
B STC
C CMP
D CMA
Answer: B
Section 1.10 Branching, Stack & Subroutines
51The instruction "JMP 4000H" is:
A Conditional jump
B Unconditional jump
C Subroutine call
D Return instruction
Answer: B
52Which instruction pushes the return address onto the stack and jumps to a subroutine?
A JMP
B CALL
C RET
D PCHL
Answer: B
53The instruction "PCHL" copies:
A PC into HL
B HL into PC
C SP into HL
D HL into SP
Answer: B
54Which conditional jump is taken when the Zero flag is 1?
A JNZ
B JZ
C JNC
D JC
Answer: B
55The stack in the 8085 is:
A FIFO
B LIFO
C Random access
D Sequential access
Answer: B
56On a PUSH operation, the Stack Pointer is:
A Incremented first
B Decremented first
C Unchanged
D Cleared
Answer: B
Microprocessors & Microcontrollers — Practice Question Bank
UNIT II — INTEL 8086 MICROPROCESSOR
16-bit microprocessor | 20-bit address | 1MB memory | Pipelined EU + BIU
Section 2.1 Introduction & Features
57The Intel 8086 is a ___-bit microprocessor with a ___-bit address bus.
A 8, 16
B 16, 20
C 16, 16
D 32, 20
Answer: B
58The 8086 can address a maximum memory of:
A 64 KB
B 1 MB
C 16 MB
D 4 GB
Answer: B
59The 8086 instruction queue is:
A 4 bytes
B 6 bytes
C 8 bytes
D 10 bytes
Answer: B
60Pipelining in the 8086 allows:
A Sequential fetch and execute
B Overlapping fetch and execute
C Only fetch operations
D Only execute operations
Answer: B
61The 8086 operates in minimum mode when MN/MX pin is:
A0
B1
C Floating
D Connected to ground
Answer: B
Section 2.2 Architecture — EU & BIU
62The Execution Unit (EU) contains:
A Segment registers only
B ALU, flag register, and general registers
C Instruction queue only
D Address generation adder only
Answer: B
63The Bus Interface Unit (BIU) contains:
A ALU only
B Segment registers, IP, and instruction queue
C Flag register only
D General registers only
Answer: B
64The physical address in the 8086 is calculated as:
A Segment + Offset
B Segment x 10H + Offset
C Segment x 16H + Offset
D Segment + Offset x 10H
Answer: B
65If CS = 2000H and IP = 1234H, the physical address is:
A 21234H
B 31234H
C 2000H
D 1234H
Answer: A
Section 2.3 Register Organization
66The AX register is primarily used for:
A Base addressing
B Arithmetic, I/O, and string instructions
C Loop counting
D Port addressing
Answer: B
67Which register is used as a loop counter?
A AX
B BX
C CX
D DX
Answer: C
68The DX register is used for:
A Base addressing
B 32-bit multiply/divide with AX and port addressing
C Loop counting
D Stack operations
Answer: B
69The SI register is used as:
A Stack pointer
B Source index in string operations
C Base pointer
D Destination index
Answer: B
70Which segment register is paired with SP for stack operations?
A CS
B DS
C SS
D ES
Answer: C
71The Instruction Pointer (IP) is equivalent to:
A Stack Pointer
B Program Counter
C Base Pointer
D Data Pointer
Answer: B
Section 2.4 Flag Register
72The 8086 flag register is:
A 8-bit
B 16-bit
C 32-bit
D 4-bit
Answer: B
73How many status flags are in the 8086 flag register?
A3
B5
C6
D9
Answer: C
74Which of the following is a control flag?
A CF
B PF
C IF
D ZF
Answer: C
75The Trap flag (TF) when set enables:
A Maskable interrupts
B Single-step mode for debugging
C Direction of string operations
D Non-maskable interrupts
Answer: B
76The Direction flag (DF) when set causes string instructions to:
A Auto-increment SI/DI
B Auto-decrement SI/DI
C Stop string operations
D Reverse the string
Answer: B
77The Overflow flag (OF) is set when:
A Unsigned result exceeds range
B Signed result exceeds its range
C Result is zero
D Result is negative
Answer: B
Section 2.5 System Buses
78The 8086 data bus is:
A 8-bit unidirectional
B 16-bit bidirectional
C 20-bit unidirectional
D 32-bit bidirectional
Answer: B
79The BHE signal in the 8086 is used for:
A Enabling the bus
B Transferring a byte on D8-D15
C Resetting the CPU
D Interrupt acknowledgment
Answer: B
80Even-address bytes in the 8086 use:
A D8-D15
B D0-D7
C A16-A19
D AD8-AD15
Answer: B
Section 2.6 Pin Diagram & Signals
81In minimum mode, the pin S0 (DEN) is used for:
A Data enable for transceivers
B Address latch enable
C Read strobe
D Write strobe
Answer: A
82In maximum mode, the signals S2, S1, S0 are decoded by:
A 8284
B 8286
C 8288
D 8255
Answer: C
83The READY pin in the 8086 is used for:
A Resetting the CPU
B Inserting wait states for slow memory/peripherals
C Enabling interrupts
D DMA operations
Answer: B
84On reset, the CS register is initialized to:
A 0000H
B FFFFH
C 1234H
D 0001H
Answer: B
Section 2.7 8085 vs 8086 Comparison
85Which feature is present in the 8086 but NOT in the 8085?
A 8-bit data bus
B Pipelining
C 16-bit address bus
D Single execution unit
Answer: B
86The 8086 supports which operating modes?
A Only minimum mode
B Only maximum mode
C Minimum and maximum modes
D Neither mode
Answer: C
87Which coprocessor can be interfaced with the 8086?
A 8085
B 8087
C 8051
D 8255
Answer: B
88Memory segmentation in the 8086 creates:
A Flat 64 KB memory
B 16 x 64 KB logical segments
C 1 MB continuous memory
D 32 KB segments
Answer: B
Section 2.8 Instruction Set Overview
89Which group does the instruction "MOVS" belong to?
A Data transfer
B Arithmetic
C String
D Program transfer
Answer: C
90The instruction "LEA" stands for:
A Load Effective Address
B Load Extended Accumulator
C Logical AND Address
D Loop End Address
Answer: A
91Which instruction is used for sign-extended division?
A MUL
B IMUL
C DIV
D IDIV
Answer: D
92The "REP" prefix is used with:
A Arithmetic instructions
B String instructions
C Logical instructions
D Branch instructions
Answer: B
Microprocessors & Microcontrollers — Practice Question Bank
UNIT III — SEMICONDUCTOR MEMORY
RAM & ROM families | Comparison | Capacity calculations | Interfacing basics
Section 3.1 Memory Classification
93RAM is classified as:
A Non-volatile read-only memory
B Volatile read/write memory
C Non-volatile read/write memory
D Volatile read-only memory
Answer: B
94ROM is used primarily for:
A Temporary data storage
B Monitor programs and fixed firmware
C Cache memory
D Main working memory
Answer: B
Section 3.2 Memory Types Compared
95Which memory type is programmed by blowing fuses and cannot be erased?
A ROM
B PROM
C EPROM
D EEPROM
Answer: B
96EPROM is erased using:
A Electrical signals
B Ultra-violet light through a quartz window
C Magnetic fields
D Heat
Answer: B
97Which memory type allows byte-by-byte electrical erasure?
A EPROM
B EEPROM
C Flash
D PROM
Answer: B
98Flash memory erases data:
A Byte-by-byte
B Block-wise
C Bit-by-bit
D Word-by-word
Answer: B
Section 3.3 SRAM vs DRAM
99SRAM uses which storage element?
A Capacitor charge
B Flip-flops (4-6 transistors/bit)
C Magnetic domains
D Optical pits
Answer: B
100DRAM requires periodic refreshing because:
A It uses flip-flops
B It uses capacitor charge which leaks
C It is non-volatile
D It uses magnetic storage
Answer: B
101Which is faster?
A SRAM
B DRAM
C Both are equal
D Depends on the manufacturer
Answer: A
102Which has higher density and is cheaper per bit?
A SRAM
B DRAM
C Both are equal
D ROM
Answer: B
103Cache memory typically uses:
A DRAM
B SRAM
C EPROM
D Flash
Answer: B
104Main memory of computers typically uses:
A SRAM
B DRAM
C ROM
D EEPROM
Answer: B
Section 3.4 Memory Capacity Calculations
105A 1K x 8 memory chip has how many address lines?
A8
B 10
C 12
D 16
Answer: B
106A 64K x 8 memory chip has how many address lines?
A 14
B 15
C 16
D 20
Answer: C
107In memory interfacing, the chip-select (CS) is generated by decoding:
A All address lines
B Unused high-order address lines
C Data lines
D Control lines
Answer: B
108Absolute decoding uses:
A Only some address lines
B All address lines
C Only data lines
D Only control lines
Answer: B
109Partial decoding can cause:
A Faster access
B Fold-back (mirror) memory
C Non-volatile behavior
D Increased capacity
Answer: B
Microprocessors & Microcontrollers — Practice Question Bank
UNIT IV — 8051 MICROCONTROLLER
8-bit CPU | 4KB ROM | 128B RAM | 4 ports | 2 timers | 5 interrupts
Section 4.1 Microprocessor vs Microcontroller
110A microcontroller integrates on a single chip:
A CPU only
B CPU + memory + I/O + timers
C Memory only
D I/O ports only
Answer: B
111The 8051 generally follows which architecture?
A von Neumann
B Harvard
C Princeton
D RISC
Answer: B
112Which application is typical for a microcontroller?
A Supercomputer
B Washing machine
C Mainframe server
D High-end gaming PC
Answer: B
113Microcontrollers are generally:
A High power, general purpose
B Low power, task-oriented
C High cost, bulky
D External memory dependent
Answer: B
Section 4.2 Block Diagram & Pin Functions
114The 8051 has how much on-chip ROM?
A 1 KB
B 4 KB
C 8 KB
D 16 KB
Answer: B
115The 8051 has how much on-chip RAM?
A 64 bytes
B 128 bytes
C 256 bytes
D 512 bytes
Answer: B
116How many I/O ports does the 8051 have?
A2
B3
C4
D5
Answer: C
117The 8051 has how many 16-bit timers/counters?
A1
B2
C3
D4
Answer: B
118The ALE pin in the 8051 pulses at what frequency relative to the oscillator?
A 1/2
B 1/4
C 1/6
D 1/12
Answer: C
119When EA = 1, the 8051 fetches program from:
A Only external ROM
B Internal ROM first, then external
C Only internal ROM
D RAM
Answer: B
120The PSEN pin is used for:
A Reading external data memory
B Reading external program memory
C Writing to external memory
D Resetting the chip
Answer: B
Section 4.3 Memory Organization
121The 8051 follows which architecture for memory?
A von Neumann (shared program/data)
B Harvard (separate program/data)
C Princeton
D RISC
Answer: B
122Internal RAM in the 8051 spans addresses:
A 0000H-0FFFH
B 00H-7FH
C 80H-FFH
D 0000H-FFFFH
Answer: B
123How many register banks are available in the 8051 internal RAM?
A2
B3
C4
D5
Answer: C
124The bit-addressable area in the 8051 is located at:
A 00H-1FH
B 20H-2FH
C 30H-7FH
D 80H-FFH
Answer: B
125When EA = 0, all program fetches come from:
A Internal ROM
B External ROM
C Internal RAM
D External RAM
Answer: B
126External data memory in the 8051 is accessed using:
A MOVC
B MOVX
C MOV
D MUL
Answer: B
127Look-up tables in program ROM are read using:
A MOVX
B MOVC
C MOV
D MUL
Answer: B
Section 4.4 Registers, SFRs & PSW
128The PSW in the 8051 is located at address:
A 80H
B D0H
C E0H
D F0H
Answer: B
129The Accumulator (A) in the 8051 is located at SFR address:
A 80H
B D0H
C E0H
D F0H
Answer: C
130The B register in the 8051 is located at SFR address:
A 80H
B D0H
C E0H
D F0H
Answer: D
131To select Bank 2 in the 8051, RS1 and RS0 should be:
A 00
B 01
C 10
D 11
Answer: C
132The Overflow flag (OV) in the 8051 PSW is set when:
A Unsigned result exceeds 255
B Signed result exceeds -128 to +127
C Result is zero
D Carry occurs from bit 3 to bit 4
Answer: B
133The Parity flag (P) in the 8051 is set when:
A A contains even number of 1-bits
B A contains odd number of 1-bits
C A is zero
D A is negative
Answer: B
134How many Special Function Registers (SFRs) does the 8051 have?
A 16
B 21
C 32
D 64
Answer: B
135The DPTR in the 8051 is:
A 8-bit
B 16-bit
C 32-bit
D 4-bit
Answer: B
Section 4.5 Stack of the 8051
136On reset, the Stack Pointer (SP) in the 8051 is initialized to:
A 00H
B 07H
C 08H
D 80H
Answer: B
137The stack in the 8051 begins at address:
A 07H
B 08H
C 00H
D 80H
Answer: B
138During a PUSH operation in the 8051, SP is:
A Decremented first, then data written
B Incremented first, then data written
C Unchanged
D Cleared
Answer: B
139The 8051 stack is located in:
A External RAM
B Internal RAM
C ROM
D SFR space
Answer: B
Section 4.6 Addressing Modes
140The instruction "MOV A, #15H" uses which addressing mode?
A Register
B Immediate
C Direct
D Indirect
Answer: B
141The instruction "MOV A, R2" uses which addressing mode?
A Immediate
B Register
C Direct
D Indirect
Answer: B
142The instruction "MOV A, 35H" uses which addressing mode?
A Immediate
B Register
C Direct
D Indirect
Answer: C
143The instruction "MOV A, @R1" uses which addressing mode?
A Immediate
B Register
C Direct
D Indirect
Answer: D
144The instruction "MOVC A, @A+DPTR" uses which addressing mode?
A Immediate
B Register
C Direct
D Indexed
Answer: D
145External RAM is accessed using which indirect addressing?
A @R0/@R1 with MOV
B @DPTR/@Ri with MOVX
C @A+DPTR with MOVC
D Direct addressing
Answer: B
Section 4.7 MUL, DIV & DA Instructions
146After executing MUL AB, the low byte of the product is in:
AB
BA
C DPTR
D PSW
Answer: B
147After executing MUL AB, if the product exceeds FFH:
A CY = 1
B OV = 1
C AC = 1
DP = 1
Answer: B
148After executing DIV AB, the quotient is in:
AB
BA
C DPTR
D PSW
Answer: B
149If division by zero occurs in DIV AB:
A CY = 1
B OV = 1
C AC = 1
DP = 1
Answer: B
150The DA A instruction is used after:
A Binary addition
B Addition of packed BCD numbers
C Logical AND
D Subtraction
Answer: B
Section 4.8 Interrupts
151How many interrupt sources does the 8051 have?
A3
B4
C5
D6
Answer: C
152The vector address for External Interrupt 0 (INT0) is:
A 0000H
B 0003H
C 000BH
D 0013H
Answer: B
153The vector address for Timer 0 overflow is:
A 0003H
B 000BH
C 0013H
D 001BH
Answer: B
154Which interrupt has the highest default priority?
A Timer 0
B External Interrupt 0
C External Interrupt 1
D Serial port
Answer: B
155The global interrupt enable bit in the 8051 is:
A ES
B EA
C ET0
D EX0
Answer: B
156The IE register in the 8051 is located at address:
A 80H
B A8H
C B8H
D D0H
Answer: B
157The IP register in the 8051 is located at address:
A 80H
B A8H
C B8H
D D0H
Answer: C
158Which instruction returns from an interrupt service routine?
A RET
B RETI
C CALL
D JMP
Answer: B
Microprocessors & Microcontrollers — Practice Question Bank
UNIT V — PROGRAM DEVELOPMENT TOOLS
Editor | Compiler | Assembler | Linker | Loader
Section 5.1 Editor, Compiler, Assembler, Linker & Loader
159Which tool translates assembly language mnemonics into machine code?
A Compiler
B Assembler
C Linker
D Loader
Answer: B
160A compiler translates:
A Assembly language to machine code
B High-level language to machine code
C Machine code to assembly language
D Object code to executable
Answer: B
161The linker combines:
A Source files into object files
B Object files and libraries into a single executable
C Machine code into source code
D Data into memory
Answer: B
162The loader places the executable:
A Into the editor
B Into memory at required addresses
C Into the compiler
D Into the assembler
Answer: B
163In the typical 8051 development flow, which step comes last?
A Writing the program
B Assembling/Compiling
C Linking
D Loading the HEX file into ROM
Answer: D
Microprocessors & Microcontrollers — Practice Question Bank
NUMERICAL & ANALYTICAL QUESTIONS
Problem-solving and calculation-based questions
164Calculate the physical address if CS = 3000H and IP = 2000H in the 8086.
A 32000H
B 5000H
C 30000H
D 20000H
Answer: A (3000H x 10H + 2000H = 32000H)
165How many memory chips of size 2K x 8 are needed to design a 16K x 8 memory system?
A4
B6
C8
D 16
Answer: C (16K / 2K = 8)
166A memory chip has 12 address lines. What is its capacity in terms of locations?
A 1K
B 2K
C 4K
D 8K
Answer: C (2^12 = 4096 = 4K)
167
If the 8085 executes an instruction with 2 machine cycles (opcode fetch + memory read), and each takes 4 T-states,
what is the total execution time at 3MHz?
A 1.33 us
B 2.67 us
C 4 us
D 8 us
Answer: B (8 T-states x 1/3us = 2.67us)
168In the 8051, if SP = 07H and PUSH A is executed, what will be the new value of SP?
A 06H
B 07H
C 08H
D 09H
Answer: C (SP increments first: 07H + 1 = 08H)
169After executing MUL AB with A = 20H and B = 03H, what is the value in A?
A 20H
B 03H
C 60H
D 00H
Answer: C (20H x 03H = 60H, low byte in A)
170If the 8051 PSW has RS1=1 and RS0=0, which register bank is selected?
A Bank 0
B Bank 1
C Bank 2
D Bank 3
Answer: C
Microprocessors & Microcontrollers — Practice Question Bank
MATCH THE FOLLOWING
Connect concepts with their correct counterparts
171Match the 8085 interrupts with their vector addresses:
Column A Column B
(a) TRAP (i) 002CH
(b) RST 7.5 (ii) 003CH
(c) RST 6.5 (iii) 0024H
(d) RST 5.5 (iv) 0034H
A a-iii, b-ii, c-iv, d-i
B a-i, b-ii, c-iii, d-iv
C a-ii, b-iii, c-i, d-iv
D a-iv, b-i, c-ii, d-iii
Answer: A
172Match the 8086 registers with their special roles:
Column A Column B
(a) CX (i) Base register for addressing
(b) BX (ii) Loop counter
(c) DX (iii) Accumulator
(d) AX (iv) Port address / 32-bit operations
A a-ii, b-i, c-iv, d-iii
B a-i, b-ii, c-iii, d-iv
C a-iii, b-iv, c-i, d-ii
D a-iv, b-iii, c-ii, d-i
Answer: A
173Match the 8051 SFRs with their addresses:
Column A Column B
(a) P0 (i) 90H
(b) P1 (ii) 80H
(c) P2 (iii) B8H
(d) IP (iv) A0H
A a-ii, b-i, c-iv, d-iii
B a-i, b-ii, c-iii, d-iv
C a-ii, b-i, c-iii, d-iv
D a-iv, b-iii, c-ii, d-i
Answer: A
Microprocessors & Microcontrollers — Practice Question Bank
TRUE OR FALSE
Determine the validity of each statement
Q174. The 8085 has a 16-bit data bus. FALSE
Q175. The 8086 uses memory segmentation to access 1MB of memory. TRUE
Q176. SRAM requires periodic refreshing. FALSE
Q177. The 8051 can expand to 64KB external program memory and 64KB external data memory. TRUE
Q178. In the 8085, the stack grows upward in memory. FALSE (it grows downward)
Q179. The 8086 in maximum mode uses the 8288 bus controller. TRUE
Q180. Flash memory can be erased byte-by-byte. FALSE (block-wise)
Q181. The 8051 has 32 I/O lines across 4 ports. TRUE
Q182. The 8085 TRAP interrupt is maskable. FALSE (it is non-maskable)
Q183. In the 8051, the instruction "MOVX A, @DPTR" accesses external data memory. TRUE
Fill in the Blanks
Complete each statement with the correct term or value
Q184. The 8085 microprocessor has a 8 -bit ALU.
Q185. The 8086 can address 1 MB of memory.
Q186. The 8051 has 128 bytes of on-chip RAM.
Q187. A memory chip with 10 address lines can store 1024 or 1K locations.
Q188. The 8085 flag register has 5 active flags.
Q189. The 8086 instruction queue is 6 bytes long.
Q190. In the 8051, the bit-addressable RAM area is from 20H to 2FH .
Q191. The 8085 SID pin stands for Serial Input Data .
Q192. The 8086 EU stands for Execution Unit .
Q193. DRAM stores data using capacitor charge.
Question Bank Summary
193 5 5
TOTAL QUESTIONS UNITS COVERED QUESTION TYPES
Coverage: 8085 (56) | 8086 (36) | Memory (17) | 8051 (70) | Tools (5) | Mixed (9)
Types: MCQ | Numerical | Match | True/False | Fill in the Blanks
End of Question Bank
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