Tutorial 1
Problems from Textbook
1.1: List the steps needed to execute the machine instruction Add LOCA, R0 in terms of
transfers between the components shown in Figure 1.2 and some simple control
commands. Assume that the instruction itself is stored in the memory at location INSTR
and that this address is initially in register PC. Include the steps needed to update the
contents of PC from INSTR to INSTR+1 so that the next instruction can be fetched.
1.2: Repeat Problem 1.1 for the machine instruction Add R1, R2, R3.
1.3(a): Give a short sequence of machine instructions for the task: "Add the contents of
memory location A to those of location B, and place the answer in location C." The
instructions Load LOC,Ri and Store Ri,LOC are the only instructions available to transfer
data between the memory and general-purpose register Ri. Add instructions were
described in Sections 1.3 and 1.6.3. Do not destroy the contents of either location A or B.
1.3(b): Suppose that Move and Add instructions are available with the format Move/Add
Location1, Location2. These instructions move or add a copy of the operand at the first
location to the second location, overwriting the original operand at the second location.
Location can be either in the memory or the processor register set. Is it possible to use
fewer instructions to accomplish the task in Part (a)? If yes, give the sequence.
1.5(a): Program execution time, T, as defined in Section 1.6.2, is to be examined for a
certain high-level language program. The program can be run on a RISC or a CISC
computer. Both computers use pipelined instruction execution, but pipelining in the RISC
machine is more effective than in the CISC machine. Specifically, the effective value of S
in the T expression for the RISC machine is 1.2, but it is only 1.5 for the CISC machine.
Both machines have the same clock rate, R. What is the largest allowable value for N, the
number of instructions executed on the CISC machine, expressed as a percentage of the
N value for the RISC machine, if time for execution on the CISC machine is to be no
longer than that on the RISC machine?
1.5(b): Repeat Part (a) if the clock rate, R, for the RISC machine is 15 percent higher
than that for the CISC machine.
1.6(a): A processor cache, as shown in Figure 1.5, is discussed in Section 1.6. Suppose
that execution time for a program is directly proportional to instruction access time and
that access to an instruction in the cache is 20 times faster than access to an instruction in
the main memory. Assume that a requested instruction is found in the cache with
probability 0.96, and also assume that if an instruction is not found in the cache, it must
first be fetched from the main memory to the cache and then fetched from the cache to be
executed. Compute the ratio of program execution time without the cache to program
execution time with the cache. This ratio is usually defined as the speedup factor
resulting from the presence of the cache.
1.6(b): If the size of the cache is doubled, assume that the probability of not finding a
requested instruction there is cut in half. Repeat Part (a) for a doubled cache size.
Other Problems
I. A program is executed on a processor with the following parameters:
• Total number of instructions executed = 50,000,000
• Average CPI = 2.7
• CPU clock rate = 2.0 GHz
Calculate the CPU execution time of the program.
II. Suppose that machine A executes a program with an average CPI of 2.3. Consider
machine B (with the same instruction set and a better compiler) that executes the same
program with 20% less instructions and with a CPI of 1.7 at 1.2 GHz. What should be
the clock rate of A so that the two machines have the same performance?
III. A program initially executes on a processor with the following characteristics:
• Instruction Count (IC) = 50,000,000
• Average CPI = 2.7
• Clock Rate = 2.0 GHz
A new compiler and processor implementation are introduced with the following
changes:
• New Instruction Count = 40,000,000
• New Average CPI = 3.0
• New Clock Rate = 2.4 GHz
Calculate:
1. The CPU execution time before optimization.
2. The CPU execution time after optimization.
3. The speedup achieved by the new system.
IV. Consider an implementation of an Instruction Set Architecture (ISA) in which the
instructions are classified into four types with CPI values of 1, 2, 3, and 4,
respectively.
Two code sequences have the following instruction counts:
Code Sequence ICType1 ICType2 ICType3 ICType4
CS-1 20 15 5 2
CS-2 10 12 10 4
Calculate:
1. The total number of CPU cycles required to execute CS-1 and CS-2.
2. The average CPI for each code sequence.
3. Which code sequence has better performance? Justify your answer.
V. Suppose an implementation of a RISC Instruction Set Architecture (ISA) has four
instruction types with the following frequency of occurrence and CPI values:
Instruction Type Frequency CPI
Load 20% 4
Store 8% 3
ALU 60% 1
Branch 12% 2
Calculate the average CPI of the processor.
VI. Suppose that a program is running on a machine with the following instruction types,
CPI values, and frequencies of occurrence:
Instruction Type CPI Frequency
A 1.3 60%
B 2.2 10%
C 2.0 30%
The CPU designer proposes two optimization options:
• Option (a): Reduce the CPI of instruction type A from 1.3 to 1.1.
• Option (b): Reduce the CPI of instruction type B from 2.2 to 1.6.
Calculate the average CPI for each option and determine which optimization provides
better performance.
VII. A benchmark program takes 600 seconds on the reference machine and 150 seconds
on the test machine. Calculate the SPEC ratio.
VIII. A benchmark suite contains four programs.
Program Reference Time (s) Test Time (s)
P1 100 20
P2 150 30
P3 120 40
P4 180 45
Calculate:
1. SPEC ratio of each program.
2. Overall SPEC rating.
IX. Six benchmark programs have SPEC ratios 3.5, 4.2, 2.8, 5.4, 3.9, 4.5. Find the overall
SPEC rating.
X. Two computer systems have the following SPEC ratios:
Benchmark System A System B
P1 4 5
P2 5 4
P3 6 5
P4 5 6
P5 4 5
Calculate the overall SPEC rating of both systems and identify the better system.