Microprocessors and
Interfacing (EEDC0317 )
Dr. Deblina Biswas
Assistant Professor
Dept. of Instrumentation and Control Engineering
About microprocessor
• It is multipurpose,
programmable, logic device that
reads binary instructions,
process data accordingly and
provide results as output
• Programmable machine has
three components:
Microprocessor, memory and
I/O device.
• These components work
together and act as system
called hardware
Microprocessor as CPU
Computer with microprocessor
Traditional computer
Microprocessor with bus architecture
• It is designed with
VLSI technology.
• It consists of ALU,
register array,
control unit, input,
out put, memory,
system bus
ALU
• The ALU performs the actual numerical and logic operation such as
add, subtract, AND, OR, etc. Uses data from memory and from
Accumulator to perform arithmetic. Always stores result of operation
in Accumulator.
• It is not accessible by user.
• The word length of ALU depends upon of an internal data bus.
• IT is 8 bit. It is always controlled by timing and control circuits.
• It provides status or result on flag register
Register array
• There are various types of registers.
• These registers stores data temporarily during execution of the
program.
• Some registers are accessible through instructions
• Types:
• Temporary Register (W and Z registers)
• General Purpose Register (B,C,D,E,H &L)
• Special Purpose Registers (Accumulator, stack pointer etc)
Control unit
• This unit generates timing signals to synchronize operations and manage data
flow. It also produces control signals like Read (RD) and Write (WR).
• Timing and Control Unit
• The timing and control unit comes under the CPU section, and it controls the
flow of data from the CPU to other devices. It is also used to control the
operations performed by the microprocessor and the devices connected to it.
There are certain timing and control signals like Control signals, DMA Signals,
RESET signals and Status signals.
• Interrupt Control
• Whenever a microprocessor is executing the main program and if suddenly an
interrupt occurs, the microprocessor shifts the control from the main program to
process the incoming request. After the request is completed, the control goes
back to the main program. There are 5 interrupt signals in 8085
microprocessors: INTR, TRAP, RST 7.5, RST 6.5, and RST 5.5.
Input and output devices
• Inputs: keyboard, ADC
• Output: CRO, LED, Display
Memory
• To execute a program:–
• the user enters its instructions in binary format into the memory.–
• The microprocessor then reads these instructions and whatever data
is needed from memory, executes the instructions and places the
results either in memory or produces it on an output device.
System Bus
• Data bus
• Address bus
• Control bus
• The address bus has 8 signal lines A8 – A15 which are unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8 data
bits.– So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0
– D7 at the same time
• The control bus carries control signals that direct the operations of the
system — such as reading from memory, writing to an I/O device, or
identifying the type of operation being performed.
How microprocessor works?
Microprocessor architecture
• 8-bit general-purpose µp
• Capable of addressing 64k of memory
• 40 pins
• Requires +5 v power supply
• Can operate with 3 MHz clock
Cont.
Register array
• General Purpose Registers
• • B, C, D, E, H & L (8 bit registers)
• Can be used singly
• Or can be used as 16-bit register pairs– BC,
DE, HL
• H & L can be used as a data pointer (holds
memory address)
• Special Purpose Registers:
A
• Accumulator (8 bit register) 02 LDAX D
• – Store 8 bit data D E
• – Store the result of an operation 3001 02 30 01
• – Store 8 bit data during I/O transfer
Cont.
• Flag Register– 8 bit register
• – shows the status of the microprocessor before/after an operation
• – S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) &
CY (carry flag)
Cont.
• Sign Flag:
• Used for indicating the sign of the data in the accumulator
• The sign flag is set if negative (1 – negative)
• The sign flag is reset if positive (0 –positive)
• Zero Flag
• Is set if result obtained after an operation is 0
• 1s set following an increment or decrement operation of that register
Cont.
• Carry Flag
• Is set if there is a carry or borrow from arithmetic operation
Cont.
• Auxillary Carry Flag
• – Is set if there is a carry out of bit 3
• Example: Consider the following BCD addition: 29H + 4CH = 75H;
• 00101001 + 01001100 = 01110101.
• In the lower nibble (rightmost 4 bits), 1001 + 1100 = 10101. There is a
carry from bit 3 to bit 4, so the AC flag is set.
• In BCD arithmetic, each decimal digit is represented by 4 bits (a
nibble). When adding two BCD numbers, a carry from the lower
nibble to the upper nibble (or vice versa) can result in an invalid BCD
representation. The AC flag helps the processor identify when such
adjustments are needed.
Cont.
• Parity Flag
• – Is set if parity is even
• – Is cleared if parity is odd
• Consider an 8-bit result of an operation: 10101010. There are four 1-
bits, which is an even number. Therefore, the parity flag would be set
(1).
• Another example: 11000001. There are three 1-bits, which is an odd
number. The parity flag would be reset (0)
Cont.
• The Program Counter (PC)–
• This is a register that is used to
control the sequencing of the
execution of instructions.
• This register always holds the address
of the next instruction
• The PC stores the memory address
of the next instruction to be
executed.
• It dictates the flow of program
LDA 2000H
execution by pointing to the CMA
instruction that the CPU will fetch INR A
and process next.
• The PC is typically incremented after
STA 3000H
each instruction fetch, unless a jump, HLT
branch, or call instruction alters its
value.
Cont.
• Stack pointer
• The SP stores the memory address of the top of
the stack. Stack
• The stack is a region of memory used for pointer
temporary storage, following a Last-In, First-Out
(LIFO) principle.
• It is used to manage function calls, local
variable allocation, and saving/restoring
register values during context switches or
interrupts.
• When data is "pushed" onto the stack (e.g.,
function arguments, return addresses), the SP
is typically decremented (or incremented,
depending on the stack's growth direction) to
point to the new top of the stack. When data is
"popped" from the stack, the SP is adjusted
accordingly.
Non programmable registers
• Instruction Register & Decoder–
• Instruction is stored in IR after being fetched by the processor
• Decoder decodes the instruction in IR
• Internal Clock generator
• – 3.125 MHz internally
• – 6.25 MHz externally
The Address and Data Buses
• The address bus has 8 signal lines A8 – A15 which are unidirectional.
• The other 8 address bits are multiplexed (time shared) with the 8 data
bits
• So, the bits AD0 – AD7 are bi-directional and serve as A0 – A7 and D0
– D7 at the same time.
• During the execution of the instruction, these lines carry the address
bits during the early part, then during the late parts of the execution,
they carry the 8 data bits.
• In order to separate the address from the data, we can use a latch to
save the value before the function of the bits changes.
Demultiplexing AD7-AD0
• From the above description, it becomes
obvious that the AD7– AD0 lines are
serving a dual purpose and that they need
to be demultiplexed to get all the
information.
• The high order bits of the address remain
on the bus for three clock periods.
• However, the low order bits remain for
only one clock period and they would be
lost if they are not saved externally.
• Also, notice that the low order bits of the
address disappear when they are needed
most .
• To make sure we have the entire address
for the full three clock cycles, we will use
an external latch to save the value of AD7–
AD0 when it is carrying the address bits.
• We use the ALE signal to enable this latch.
Pin description
Power supply and clock frequency
• Vcc= + 5V
• Vss: Ground reference
• X1, X2: A crystal is connected at these two pins. The frequency is
initially divided by two; therefore to operate system at 3 MHz, the
crystal should have 6 MHz
• CLK (OUT): The signal can be used as the system clock for other
devices.
8085 Pin Description
Status signals
Status signal
Control signal
Control and status signal
Generating control signals
Interrupt
Reset signal
Serial I/O
External-initiated signal
Important concepts:
• Multiplexed Bus AD7-AD0.
• This can be demultiplexed by latch and ALE signal
• By ANDing status signal (IO/M’) and Control signals (RD’ and WR’)
four control signals are generated.
• MEMR’- transfer data from memory location to microprocessor
(reading from memory)
• MEMW’- transfer data from microprocessor to memory location
(writing into memory)
• IOR’- Accept data from input devices
• IOW’- send data to o/p devices.
Instruction decoding and execution
• Place the memory address of the instruction to the
address bus
• Indicates the operation status on the status lines.
• Send the MEMR’ control signal to enable the memory,
fetch the instruction byte and place it in the instruction
decoder.
• Execute the instruction
Data flow from memory to MPU ALE – high
IO/M’- low
• Step of data flow when
instruction code 0100
1111 (4FH – MOV C, A)
stored in XX0AH memory
location is being fetched.
RD’
Example
Assume that the accumulator contains data byte 82H
and the instruction MOV C,A is fetched. List the steps
of decoding and executing the instruction.
Example of a microcomputer system
RAM and ROM models
• Calculate the address line, data lines and memory size of 128*8 RAM.
Calculate the number of pins.
• Calculate the address line, data lines and memory size 4096*16 RAM.
Calculate the number of pins.
Memory Map and Addresses
• The memory map is a
picture representation
of the address range
and shows where the
different memory chips
are located within the
address range.
• To communicate with
memory, the MPU
should be able to
1. Select the chip
2. Identify the register
3. Read from or write
into the register
Example
• Illustrate the memory address range of the chip with 256 bytes of
memory shown in figure. Explain how the range can be modified by
changing hardware of CS’.
A15-A8
Range 0000H- 00FF H
256
byte
Cont.
• Explain how the range can be modified by changing hardware of CS’.
8085 Machine cycles and Bus Timing
• Designed to execute 74 different instruction types.
• Each instruction has two parts:
• Operation code (opcode)- The opcode is a unique code that identifies the
specific action the processor should execute. It's essentially the command
word for the CPU.
• Operand -Operands are the data or addresses that the opcode operates
on. They specify where to find the data to be processed or where to store
the results of the operation.
• "ADD R1, R2", "ADD" is the opcode specifying an addition operation, and
"R1" and "R2" are the operands representing registers containing the data
to be added.
Timing diagram
• A time diagram is a graphical representation
where the 8085 instruction timing diagram
represents the execution time of each
instruction in graphical format.
• Instruction Cycle: The time taken by the
processor to complete the execution of an
instruction. An instruction cycle consists of one
to six machine cycles.
• Machine Cycle: The time required to complete
one operation; accessing either the memory or
I/O device. A machine cycle consists of three to
six T-states.
• T-State: Time corresponding to one clock
period. It is the basic unit to calculate execution
of instructions or programs in a processor
Cont.
• To execute a program, the 8085 performs various
operations as:
• Opcode fetch
• Memory read/write
• I/O read/write
• External communication functions are:
• Memory read/write
• I/O read/write
• Interrupt request acknowledge
Cont.
• The function of the microprocessor is divided into a fetch and execute
cycle for any instruction of a program.
• The program is nothing but a number of instructions stored in the memory
in sequence.
• In the normal process of operation, the microprocessor fetches (receives
or reads) and executes one instruction at a time in the sequence until it
executes the halt (HLT) instruction.
• Thus, an instruction cycle is defined as the time required to fetch and
execute an instruction.
• The time taken by the µP in performing the fetch and execute operations is
called the fetch and execute cycle.
Cont.
Op-code fetch machine cycle
Cont.
Memory read machine cycle
Memory write
I/O read and I/O write machine cycle
I/O read I/O write
Step of data flow when instruction code
0100 1111 (4FH – MOV C, A) stored in
XX0AH memory location is being fetched.
Execution of instructions 1. At T1 microprocessor identifies it is an
Memory location Machine code Instruction opcode fetch cycle by placing 011 on
2000H 0011 1110 3EH MVI A, 32H status signal
2001H 0011 0010 32H 2. At T2, the 8085 asserts RD’ control signal
which enables the memory and memory
places the byte 3EH from location 2000H
on the data bus.
3. Then 8085 places opcode in the
instruction register and disable RD’
signal. Fetch cycle is complete in T3
4. During T4 the microprocessor decodes
the opcode and find out that a second
byte needs to be read
Timing Diagram of STA 8000H
Address Data
• STA stands for Store Accumulator - the Address Data
1000H 32H
contents of the accumulator are stored at
1001H 00H 8000H 55H
(1000H).
• Content of the accumulator- 55H 1002H 80H