Assignment – 2 Solutions

1. Consider the following logic circuit. Delays of logic gates are tnor = 1.5ns, tinv = 1ns, tor = 2ns,
tand = 1.5ns and tmux = 2.5ns.

The critical path delay in the logic circuit given above is ______

Answer: (11ns)

̅ + 𝐶). 𝐶 = 𝐶𝐷
X = (𝐷 ̅ + 𝐶 = 𝐶(𝐷
̅ + 1) = C.

The value at point x in the circuit does not depend on D, So the inverter doesn’t need to be
considered in the critical path delay.

Tcritical = tor + tand + tinv + tmux + tnor + tmux = 2 + 1.5 + 1.5 + 2.5 + 1.5 + 2.5 = 11.5ns

2. Find the delay of the false path in the logic circuit given in question 1.
a. 11 ns
b. 10 ns
c. 11.5 ns
d. 12.5 ns

Answer: (d)

There are 2 false paths in the circuit. The value of the false path that has the largest delay is

Tfalse = tinv + tor + tand + tnor + tmux + tnor + tmux = 1 + 2 + 1.5 + 1.5 + 2.5 + 1.5 + 2.5 = 12.5 ns
 3. Consider the following logic circuit.

What is the Unateness of output pin Y with respect to the input pin B?

a. Negative unate
b. Positive unate
c. Non unate
d. Can’t be determined

Answer: (b)

B A C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Case – 1: keep A = 0, C = 0 and B is changing from 0 → 1. You see no change in the output y from
truth table.

Case – 2: keep A = 0, C = 0 and B is changing from 1 → 0. You see no change in the output y from
truth table.

Case – 3: keep A = 0, C = 1 and B is changing from 0 → 1. You see 0 → 1 in the output y from truth
table.

Case – 4: keep A = 0, C = 1 and B is changing from 1 → 0. You see 1 → 0 in the output y from truth
table.

Similarly, you can check for four other cases and find that output pin Y is of positive unate with
respect to pin B.

4. The number of timing arcs in a three input AND gate are

a. 3
 b. 4
c. 6
d. 7

Answer: (c)

Let a,b and c are the inputs of the AND gate.

If a = 1, b = 1 and c = 0 → 1, then output = 0 → 1

If a = 1, b = 1 and c = 1 → 0, then output = 1 → 0

If a = 0 → 1, b = 1 and c = 1, then output = 0 → 1

If a = 1 → 0, b = 1 and c = 1, then output = 1 → 0

If a = 1, b = 0 → 1 and c = 1, then output = 0 → 1

If a = 1, b = 1 → 0 and c = 1, then output = 1 → 0

These are the six timing arcs in the 3 input AND gate.

5. Consider the given logic circuit. Find the rise and fall delays of the timing path from input to
output.

The rise and fall delays of the gates are as follows

Gate NOT(ns) NOR(ns) NAND(ns)

Rise delay 2 2 5
Fall delay 2 3 4

a. trise = 10ns, tfall = 8ns

b. trise = 8ns, tfall = 9ns
c. trise = 7ns, tfall = 10ns
d. trise = 9ns, tfall = 8ns

Answer: (a)

trise = trise(inv) + tfall(nor) + trise(nand) = 2 + 3 + 5 = 10ns

tfall = tfall(inv) + trise(nor) + tfall(nand) = 2 + 2 + 4 = 8ns

6. Consider the master-slave flipflop circuit given below.

Delays of gates are tinv = 0.5ns, ttx = 1ns.

Given master-slave flipflop is _________ triggered.

a. Positive edge
b. Negative edge
c. Level
d. None of the above

Answer: (b)

Master is a positive latch and Slave is a negative latch.

Data is captured by master during positive clock cycle and slave becomes transparent during
negative cycle. So it is a negative edge triggered flipflop.

7. The setup time of the master-slave flipflop given in question 6 is ______ns(NAT) (4ns)

Answer: 4ns

tsetup = 6*tinv + ttx

tsetup = 3ns + 1ns = 4ns

8. The hold time of the master-slave flipflop given in question 6 is

a. Negative
b. Positive
c. Zero
d. Cannot be determined

Answer: (c)

Since, tinv = ttx = 0.5ns, Hold time, thold = 0

9. Consider the following diagram

Delay values of Flipflop and Combinational circuit are: tsetup = 5ns and thold = 4ns

Delay tclk-q tcomb

Max 4 ns 7 ns
 Min 3 ns 2 ns

The maximum frequency at which the given circuit can operate without failure is ____(MHz)

Answer:(62.5)

Tclk ≤ tcombmax + tclk-qmax + tsetup

Tclk ≤ 7ns + 4ns + 5ns

Tclk ≤ 16ns

Therefore, fclk = 1/16ns = 62.5 MHz

10. Choose the correct hold constraint equation for the circuit given in question 9.
a. 4ns ≤ 3ns + 7ns
b. 4ns ≤ 3ns + 2ns
c. 4ns ≤ 4ns + 7ns
d. 4ns ≤ 4ns + 2ns

Answer: (b)

thold ≤ tclk-qmin +tcombmin

4ns ≤ 3ns + 2ns

 Assignment – 3
1. Consider the following circuit.

Delay values of Flipflop and Combinational circuit are: tsetup = 5ns and thold = 4ns. The delay of the
buffer is tbuf = 2ns.

Delay tclk-q tcomb

Max 4 ns 7 ns
Min 3 ns 2 ns

The maximum frequency at which the given circuit can operate without failure is _____(MHz)
(Rounded to 2 decimal points)

Answer: The max timing constraint equation for positive skew is:

tclk-qmax + tcombmax + tsetup – tbuf ≤ Tclk

4ns + 7ns + 5ns – 2ns ≤ Tclk

14ns ≤ Tclk

Therefore, fclkmax = 1/14n = 71.43 MHz

2. Choose the correct hold constraint equation for the circuit given in question 1.
a. 4ns ≤ 4ns + 7ns
b. 4ns – 2ns ≤ 3ns + 2ns
c. 4ns + 2ns ≤ 3ns + 2ns
d. 4ns ≤ 3ns + 2ns + 2ns

Answer: Min timing constraint equation for positive skew is:

thold + tbuf ≤ tclk-qmin + tcombmin

4ns + 2ns ≤ 3ns + 2ns

3. Consider the following circuit.

 Delay values of Flipflop and Combinational circuit are: tsetup = 5ns and thold = 4ns. The delay of the
buffer is tbuf = 2ns.

Delay tclk-q tcomb

Max 4 ns 7 ns
Min 3 ns 2 ns
The maximum frequency at which the given circuit can operate without failure is
_____(MHz)(Rounded to 2 decimal points)

Answer: The max timing constraint equation for positive skew is:

tclk-qmax + tcombmax + tsetup + tbuf ≤ Tclk

4ns + 7ns + 5ns + 2ns ≤ Tclk

18ns ≤ Tclk

Therefore, fclkmax = 1/18n = 55.56 MHz

4. Consider the following circuit.

Delay values of Flipflop and Combinational circuit are: tsetup = 5ns and thold = 4ns. The clock period
is Tclk = 20ns.

Delay tclk-q tcomb

Max 4 ns 7 ns
Min 3 ns 2 ns
What is the maximum allowable jitter(tjitter) in the clock signal so that the given circuit works at
the given frequency without failure?

a. 0.5 ns
b. 1 ns
c. 2 ns
d. 4 ns

Answer:
Max timing analysis considering clock jitter

Tclk ≥ tclk-qmax + tcombmax + tsetup + 2tjitter

20ns ≥ 4ns + 7ns + 5ns + 2tjitter

tjitter ≤ (20ns – 16ns)/2

tjitter ≤ 2ns

Min timing analysis considering clock jitter

thold ≤ tclk-qmin + tcombmin – 2tjitter

4ns ≤ 3ns + 2ns – 2tjitter

tjitter ≤ (5ns – 4ns)/2 = 0.5ns

Maximum allowable jitter (tjitter) in the clock signal so that the given circuit works at the given frequency
without failure = min(2ns, 0.5ns) = 0.5ns

5. Choose the correct option(s) about clock skew and clock jitter.
a. Clock jitter deteriorates the performance of the system
b. Clock jitter is a spatial variation
c. Clock period varies due to clock skew
d. Coupling between two adjacent lines is one of the sources of clock jitter

6. Consider the following circuit.

Delay tclk-q(FF1) tclk-q(FF2) tcomb

Max 3.8 ns 5 ns 6 ns
Min 2 ns 2.8 ns 2.5 ns
The delays of buffers tbuf1 = 1.2ns, tbuf2 = 0.9ns, and tbuf3 = 0.7ns. The setup and hold time of both
flipflops is tsetup = 2ns and thold = 1ns respectively.

The On-chip variation is modeled as

set_timing_derate -early 0.9

set_timing_derate -late 1.12

set_timing_derate -late 1.08 -cell_check

With On-chip variation, the maximum frequency at which the given circuit can operate without
failure is _____(MHz) (Round to the nearest integer)

Answer:

Capture clock path = 1.2 + 0.7 = 1.9ns

Launch clock path = 1.2 + 0.9 = 2.1ns

Max data path = 3.8 + 6 = 9.8ns

With OCV:

Tclk + capture clock path*(0.9) – tsetup*(1.08) ≥ (launch clock path + max data path)*(1.12)

Tclk + 1.9*0.9 – 2*1.08 ≥ (2.1+9.8)*1.12

Tclk + 1.71 – 2.16 ≥ 13.328

Tclk ≥ 13.778ns

Fclkmax = 1/13.778ns = 72.57 MHz = 73MHz

7. The value of common path pessimism(CPP) in the circuit given in question 6 is ____ps

Answer: CPP = latest AT @ common point – Earliest AT @ common point

CPP = 1.2*1.12 – 1.2*0.9 = 0.264ns = 264ps

8. Consider the following logic circuit.

Logic gate Rise delay(ns) Fall delay(ns)

NAND 4 3
NOR 3 5
AND 2 3
OR 5 4
Buffer 1 2

Arrival Time at all primary inputs a, b, c, d, e, and f is 0/0.

Required Time at node ‘m’ is 16/13

The fall output arrival time at node ‘l’ is __14__(ns)

9. The rise input required time at node ‘c’ in the circuit given in question 8 is __-3__ (ns)

10. The slack(rise/fall) at node ‘i’ in the circuit given in question 8 is ____
a. 0/6
b. 6/0
c. 1/4
d. 4/1

For question 10 option all given options are wrong. The correct answer is 7/-1

Answer: (For questions 8, 9 and 10)

Equations used in the solution:

For inverting gates: For inverting gates:

output rise AT = max(input fall AT) + trise output rise AT = max(input rise AT) + trise
output fall AT = max(input rise AT) + tfall output fall AT = max(input fall AT) + tfall
input rise RT = min(output fall RT) – tfall input rise RT = min(output rise RT) – trise
input fall RT = min(output rise RT) – trise input fall RT = min(output fall RT) – tfall

You can find the values using the above equations.