CPU

STUDY GUIDE

Introduction to
Microprocessor Architecture
A foundational tour of what's inside a CPU: registers, buses, the fetch–decode–execute cycle, and
the design choices that shape how processors are built.

ELECTRONICS & COMPUTER ENGINEERING STUDY GUIDE

INTRODUCTION TO MICROPROCESSOR ARCHITECTURE

1. What Is a Microprocessor?
A microprocessor is a single integrated-circuit chip that contains the core logic of a computer's central
processing unit (CPU). It fetches instructions from memory, decodes what they mean, and executes them —
performing arithmetic, moving data, and making decisions millions or billions of times per second. Every
device with a “brain,” from a laptop to a washing machine controller, relies on one.

At its core, a microprocessor is built to repeatedly do four things:

• Fetch the next instruction from memory.

• Decode that instruction to determine what operation is required.

• Execute the operation using its internal circuitry.

• Store or forward the result, then move on to the next instruction.

Why it matters
Understanding microprocessor architecture is the foundation for everything from writing efficient code to
designing embedded systems — it explains why computers behave the way they do, not just how to
program them.

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2. Core Architectural Components

Every microprocessor, regardless of brand or generation, is built from the same handful of core building
blocks working together:

• Arithmetic Logic Unit (ALU) — performs arithmetic (add, subtract) and logical (AND, OR, compare)
operations on data.

• Control Unit (CU) — directs the operation of the processor: it interprets instructions and generates the
signals that coordinate every other component.

• Registers — small, extremely fast storage locations inside the CPU that hold data and addresses
currently in use.

• Buses — the electrical pathways (data, address, control) that carry information between the CPU,
memory, and input/output devices.

CPU Address Bus Memory

RAM / ROM
Control Unit ALU
(CU) Arithmetic / Logic
Data Bus

Registers Control Bus I/O

PC · IR · ACC · MAR · MDR · SP Devices

Internal Data Path

Figure 1. Simplified block diagram of a microprocessor and its connection to memory and I/O via three buses.

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3. The Instruction Cycle: Fetch – Decode – Execute

Every single instruction a processor runs — whether it's adding two numbers or reading a byte from disk —
goes through the same three-stage cycle, over and over, for as long as the machine is powered on:

1. FETCH 2. DECODE 3. EXECUTE

Read instruction from Control unit interprets ALU / registers perform
memory address in PC the opcode & operands the operation

repeats for every instruction — the CPU's basic rhythm

Figure 2. The fetch–decode–execute cycle repeats for every instruction.

In the fetch stage, the Control Unit reads the instruction stored at the address held in the Program Counter
(PC), and the PC then advances to point at the next instruction. During decode, the instruction's opcode is
interpreted to determine which operation and which operands (registers or memory locations) are involved.
Finally, in execute, the ALU or another functional unit actually performs the operation, and the result is
written back to a register or memory.

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4. Registers in Detail
Registers are the processor's closest, fastest storage — far faster than RAM, but very limited in number and
size (typically 8, 16, 32, or 64 bits each). A handful of registers have well-defined, special-purpose roles in
almost every architecture:

Register Full Name Purpose

PC Program Counter Holds the memory address of the next instruction to fetch.

IR Instruction Register Holds the instruction currently being decoded/executed.

ACC Accumulator General register that holds intermediate arithmetic/logic

results.

MAR Memory Address Register Holds the address of the memory location being accessed.

MDR Memory Data Register Holds the data being transferred to or from memory.

SP Stack Pointer Points to the top of the call/data stack in memory.

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5. Buses — the CPU's Communication Highways

A bus is a shared set of electrical wires that carries signals between the CPU, memory, and peripherals.
Three buses do almost all of the work:

Bus Direction Carries

Address Bus CPU → Memory/I-O The memory address the CPU wants to read from or
(one-way) write to. Its width limits how much memory can be
addressed.

Data Bus Two-way The actual data being transferred — an instruction, a

number, a character.

Control Bus Two-way (signals) Timing and control signals such as read/write, clock,
and interrupt requests that keep every component
synchronized.

The width of the address bus determines the processor's maximum addressable memory (an n-bit address
bus can address 2n locations), while the width of the data bus — often called the processor's “word size”
(e.g. 32-bit, 64-bit) — affects how much data can move in a single transfer.

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6. Von Neumann vs. Harvard Architecture

Processors differ in how instructions and data share (or don't share) memory and buses:

Von Neumann Architecture Harvard Architecture

CPU CPU

one bus

Memory Instr. Mem. Data Mem.

instructions + data share one space

instructions & data compete for one bus separate buses — can fetch instruction & data at once

Figure 3. Von Neumann architecture shares one memory and bus for instructions and data; Harvard architecture keeps them
separate.

Feature Von Neumann Harvard

Memory Single shared memory for code and data Separate memory spaces for code and
data

Bus One shared bus — fetch and data access Separate buses — can fetch instruction
compete and access data simultaneously

Simplicity Simpler, cheaper to design More complex, but faster in practice

Common use General-purpose CPUs (most desktops) Microcontrollers, DSPs, embedded

systems

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7. CISC vs. RISC Design Philosophies

Beyond memory architecture, processors also differ in instruction set philosophy — how much work a single
instruction is expected to do:

CISC RISC

Stands for Complex Instruction Set Computer Reduced Instruction Set Computer

Instructions Many, complex — one instruction can do Few, simple — each instruction does one
several steps basic step

Instruction Variable Fixed

length

Examples x86 / x86-64 (Intel, AMD) ARM, RISC-V, older MIPS/SPARC

Trade-off Fewer instructions per program, more More instructions per program, but
complex hardware simpler & often faster hardware

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8. What Affects Microprocessor Performance?

• Clock speed (GHz) — how many cycles the processor completes per second; more cycles generally
means more instructions processed, though not all instructions take one cycle.

• Word size / data bus width — 32-bit vs 64-bit processors move more data per transfer and can
address more memory.

• Cache memory — small, very fast on-chip memory (L1/L2/L3) that stores frequently used data close to
the CPU, reducing slow trips to main memory.

• Pipelining — overlapping the fetch, decode, and execute stages of multiple instructions so the
processor isn't idle while waiting for one stage to finish.

• Number of cores — modern processors package multiple independent execution units on one chip,
allowing true parallel execution of separate instruction streams.

Worth remembering
Clock speed alone is a poor measure of performance — architecture, cache design, and instruction
efficiency often matter more than raw gigahertz.

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9. Key Terms Glossary

Term Meaning

Opcode The part of an instruction that specifies which operation to perform.

Operand The data or register/address an instruction operates on.

Clock cycle One tick of the processor's internal clock — the basic unit of timing.

Pipelining Overlapping instruction stages to increase throughput.

Cache Small, fast memory that stores frequently accessed data near the CPU.

Interrupt A signal that pauses normal execution to handle an urgent event.

Word size The natural unit of data (in bits) a processor's registers and bus handle at once.

This guide covered the essential vocabulary and mental model for reading about processors: the ALU,
control unit, and registers that do the work; the buses that connect them; the fetch–decode–execute cycle
that drives every instruction; and the architectural choices (Von Neumann vs. Harvard, CISC vs. RISC) that
shape real-world chips.

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