Input-Output Organization

BASIC CONCEPTS
• Figure 8.1 shows a simple arrangement for connecting the processor and the memory in a
given computer system to an input device for example, a keyboard and an output device
such as a graphic display.

• A single bus consisting of the required address, data, and control lines is used to connect
the system’s components.
 Shared I/O (I/O Mapped I/O)
• In this arrangement, I/O devices are assigned particular addresses, isolated from the
address space assigned to the memory.

• The execution of an input instruction will cause the character stored in the input register
of that device to be transferred to a specific register in the CPU.

• Similarly, the execution of an output instruction will cause the character stored in a
specific register in the CPU to be transferred to the output register of that output device.

• This arrangement is called shared I/O and shown in Figure 8.2.

• In this case, the address and data lines can be shared between the memory and I/O
devices.

• A separate control line will have to be used.

• In a typical computer system, there exists more than one input and more than one output
device.

• Therefore, there is a need to have address decoder circuitry for device identification.

• There is also a need for status registers for each input and output device.

• The status of an input device, whether it is ready to send data to the processor, should be
stored in the status register of that device.

• Similarly, the status of an output device, whether it is ready to receive data from the
processor, should be stored in the status register of that device.

• Input register, output register, status registers, and address decoder circuitry are the main
components of an I/O interface.
Advantage and Disadvantage of shared I/O
• The main advantage of the shared I/O arrangement is the separation between the
memory address space and that of the I/O devices.

• Its main disadvantage is the need to have special input and output instructions in
the processor instruction set.

• The shared I/O arrangement is mostly adopted by Intel.

 Memory-Mapped I/O
• The second I/O arrangement is to deal with input and output registers as if they are
regular memory locations.

• In this case, a read operation from the address corresponding to the input register of an
input device, for example, Read Device 6, is equivalent to performing an input operation
from the input register in Device #6.

• Similarly, a write operation to the address corresponding to the output register of an

output device, for example, Write Device 9, is equivalent to performing an output
operation into the output register in Device #9.

• This arrangement is called memory-mapped I/O. It is shown in Figure 8.3.

 Advantage and Disadvantage of Memory-Mapped I/O

• The main advantage of the memory-mapped I/O is the use of the read and write
instructions of the processor to perform the input and output operations,
respectively. It eliminates the need for introducing special I/O instructions and
separate I/O control lines.

• The main disadvantage of the memory-mapped I/O is the need to reserve a certain
part of the memory address space for addressing I/O devices, that is, a reduction in
the available memory address space.

• The memory-mapped I/O has been mostly adopted by Motorola.

 PROGRAMMED I/O
• The main hardware components required for communications between the processor and
I/O devices are presented here.

• The way according to which such communications take place is also indicated.

• This protocol has to be programmed in the form of routines that run under the control of
the CPU.

• Consider, for example, an input operation from Device 6 (could be the keyboard) in the
case of shared I/O arrangement.

• Let us also assume that there are eight different I/O devices connected to the processor in
this case (see Fig. 8.4).
• The following protocol steps have to be followed:
• Step 1: The processor executes an input instruction from device 6, for example, INPUT 6.

• The effect of executing this instruction is to send the device number to the address
decoder circuitry in order to identify the specific input device to be involved.

• In this case, the output of the decoder in Device #6 will be enabled, while the outputs of
all other decoders will be disabled.

• Step 2: The buffers holding the data in the specified input device (Device #6) will be
enabled by the output of the address decoder circuitry.

• Step 3: The data output of the enabled buffers will be available on the data bus.

• Step 4: The data available on the data bus will be transferred to a particular register in the
CPU, normally the accumulator.
• Output operations can be performed in a way similar to the input operation.

• The only difference will be the direction of data transfer, which will be from a specific
CPU register to the output register in the specified output device.

• I/O operations performed in this manner are called programmed I/O.

• They are performed under the CPU control.

• A complete instruction fetch, decode, and execute cycle will have to be executed for every
input and every output operation.

• Programmed I/O is useful in cases whereby one character at a time is to be transferred, for
example, keyboard and character mode printers.

• Although simple, programmed I/O is slow.

 Polling Scheme
• Software I/O Polling:
• The process of checking the status of I/O devices in order to determine their readiness for
receiving and/or sending characters, is called software I/O polling.

• Hardware Polling Scheme:

• As shown in the figure, each of the N I/O devices has access to the interrupt line INR.
• Upon recognizing the arrival of a request (called Interrupt Request) on INR, the processor
polls the devices to determine the requesting device.
• The priority of the requesting device will determine the order in which addresses
are put on the polling lines.

• The address of the highest priority device is put first, followed by the next priority,
and so on until the least priority device.
 INTERRUPT-DRIVEN I/O
• Interrupt: An interrupt refers to a signal or event that halts the normal execution
of a program or process.

• Need of Interrupt:
• To react to abnormal events, such as power failure.

• An interrupt can also be used to acknowledge the completion of a particular course

of action, such as a printer indicating to the computer that it has completed
printing the character(s) and ready to receive other character(s).
 Interrupt Service
• When the CPU is interrupted, it is required to discontinue its current activity,
provide service to the interrupt and then resume its activity from where it stopped.

• Discontinuity of the processor’s current activity requires finishing executing the

current instruction, saving the processor status (mostly in the form of pushing
register values onto a stack), and transferring control (jump) to what is called the
interrupt service routine (ISR).

• The service offered to an interrupt i.e. ISR will depend on the source of the
interrupt.

• For example, if the interrupt is due to power failure, then the action taken will be
to save the values of all processor registers and pointers such that resumption of
correct operation can be guaranteed upon power return.
• In the case of an I/O interrupt, serving an interrupt means to perform the required
data transfer.

• Upon finishing serving an interrupt, the processor should restore the original status
by popping the relevant values from the stack.

• Once the processor returns to the normal state, it can enable sources of interrupt
again.
 Interrupt Hardware
• Computers are provided with interrupt hardware capability in the form of specialized
interrupt lines to the processor.

• These lines are used to send interrupt signals to the processor.

• In the case of I/O, there exists more than one I/O device.

• The processor should be provided with a mechanism that enables it to handle

simultaneous interrupt requests and to recognize the interrupting device.

• Two basic schemes can be implemented to achieve this task:

• Daisy chain bus arbitration (DCBA) and
• Independent source bus arbitration (ISBA)
 Daisy Chain Bus Arbitration (DCBA)
• According to the DCBA, I/O devices send their interrupt requests to the interrupt request
line INR’.

• Upon recognizing the arrival of an interrupt request, the processor sends its
acknowledgement via grant line (GL) to the requesting device through a daisy chain
method.
• The GL goes through all devices starting from the first device nearer to the
processor and going to the next device and so on until it reaches the last device
(Device #N).

• If Device #1 has put a request, then it will hold the grant signal and start
communication with the processor.

• If Device #1 has no interrupt request, it will pass the grant signal to device #2,
which will repeat the same procedure, and so on.

• In the case of multiple requests, the DCBA arrangement gives highest priority to
the device physically nearer to the processor. The furthest device from the
processor has the lowest priority.
• Advantages:
• Simplicity and Scalability.
• The user can add more devices anywhere along the chain, up to a certain
maximum value.

• Disadvantages:
• The value of priority assigned to a device depends on the position of the master
bus.
• Propagation delay arises in this method.
• If one device fails then the entire system will stop working.
 Independent Source Bus Arbitration (ISBA)
• According to the ISBA, each I/O device has its own interrupt request line, through
which it can send its interrupt request, independent of the other devices.

• Similarly, each I/O device has its own grant line, through which it receives the
grant signal for its request such that it can start communicating with the processor.

• I/O device priority in the ISBA does not depend on the device location. A priority
arbitration circuitry is needed in order to deal with simultaneous interrupt requests.
 DIRECT MEMORY ACCESS (DMA)
• The main idea of DMA is to enable peripheral devices to cut out the “middle man”
role of the CPU in data transfer.

• It allows peripheral devices to transfer data directly from and to memory without
the intervention of the CPU.

• It allows the CPU to do other work, which would lead to improved performance,
especially in the cases of large transfers.
 DMA Controller
• The DMA controller is a piece of hardware that controls one or more peripheral devices.

• It allows devices to transfer data to or from the system’s memory without the help of the processor.

• Both the DMA and CPU use memory bus and only one or the other can use the memory at the
same time.

• The DMA controller then sends a request to the CPU asking its permission to use the bus.

• The CPU returns an acknowledgment to the DMA controller granting it bus access.

• The DMA can now take control of the bus to independently conduct memory transfer.

• When the transfer is complete the DMA releases its control of the bus to the CPU.