comp3370

CPU DESIGN/IMPLEMENTATION

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 Single Cycle Implementation (cont’d)
• To understand, in terms of the circuit, what
makes this a single cycle implementation we
need to know how the processor clock is used
• Recall: there are fundamentally two types of
circuits – combinational and sequential
– combinational (stateless) logic is where the output
of the circuit is determined solely by the inputs
– Sequential (stateful) logic is where the output of
the circuit is determined by the inputs and “state”
• State is “remembered information” derived from prior
inputs seen by the circuit
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 Single Cycle Implementation (cont’d)
• Sequential circuits must contain memory
elements (e.g. flip-flops, registers, buffers, etc.)
– to store the state information
• For example, in a computer design, the state
information from previous instruction
evaluations must be stored
– We use the register file, PC, etc. to do this
• Such elements are present in our design
– as they must be, since programs are stateful!
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 Single Cycle Implementation (cont’d)
• In most other respects though we have been
treating our single cycle design almost as if it
were a combinational circuit
– E.g. we extract register numbers from the current
instruction, feed them to register file inputs, the
register file provides register values which go to the
ALU which does something producing a result …
• Hmmm! – Not terribly realistic!
• Let’s think about updating the PC!
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 Single Cycle Implementation (cont’d)
• As part of every instruction evaluation, we
update the PC (Program Counter)
– Normally, this is just: PC=PC+4
• Question: When can we actually replace the
contents of the PC with PC+4 (or …)?
• If we do this too quickly, a new instruction will
be fetched, decoded, etc.
– How do we guarantee that the current instruction
is complete before this can happen?

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 Single Cycle Implementation (cont’d)
• The Program Counter (PC) is a register (i.e. a
storage element) and hence part of a
sequential circuit (our single cycle design)
– Recall that a register is built from a collection of
Flip-Flops (FFs) operating in parallel (1 bit per FF)
• Recall also that FFs are commonly clocked to
control when changes on the input are
reflected in the flip flop
• Thus, registers (like the PC) are also clocked!
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 Single Cycle Implementation (cont’d)
• Since the PC is clocked, we can control when the
new PC value is latched
– and thus when the next instruction evaluation starts
• And thus when the next cycle begins
• This leads to the question of “When should we
latch the new PC value?”
– We should do this only once the entire previous
instruction has finished
• How we determine the single cycle machine cycle time!
– Find the duration of the longest running instruction and set the
cycle time to be that!

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 Single Cycle Implementation (cont’d)
• Viewed at a high level as a sequential circuit
our single cycle design looks like the following:

Single cycle Single cycle

design state design
elements combinational
(PC, registers, logic
data memory) (ALU, Adders, MUXes,
control )

– All clocked so that the state elements latch new

values (for example) on the leading clock edge
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 Single Cycle Implementation (cont’d)
• Having an actual (albeit simple) implementation
we can now consider finer grained performance
– i.e. Consider the speed of CPU components when
assessing performance and comparing machines
• Components in our implementation might have
the following performance characteristics:
– Memory access takes 500 psec (on average)
– ALU and adders take 500 psec
– Register access (read or write) takes 250 psec
– Control (ID), muxes, sign extension are ~delay-free
• Not realistic, actually small, but OK for this simple example
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 Single Cycle Implementation (cont’d)
• Let’s look at two alternatives for the cycle
time for our implementation and compare
their performance. We will call these two
options:
a) Fixed clock length (duration of the longest
running instruction, as already described)
b) Variable clock length (shorter or longer,
depending on instruction type)
– This exercise will provide a nice segue to our
second MIPS machine implementation!

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 Single Cycle Implementation (cont’d)
• Lets start by figuring out the option a cycle time
given our component performance data
– To do this we need to find the time needed for each
possible instruction type (and use the longest)
– R-type:
Time = IF(Mem) + OF(Reg) + EX(ALU) + WB(Reg)
= 500 +250 + 500 + 250 = 1500psec=1.5nsec
– lw:
Time = IF(Mem) + OF(Reg) + EX(ALU) + EX(Mem) + WB(Reg)
= 500 +250 + 500 + 500 + 250 = 2000psec=2nsec
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 Single Cycle Implementation (cont’d)
– sw:
Time = IF(Mem) + OF(Reg) + EX(ALU) + EX(Mem)
= 500 +250 + 500 + 500 = 1750psec=1.75nsec
– beq:
Time = IF (Mem) + OF (Reg) + EX (ALU) + EX (adder)
= 500 +250 + 500 + 500 = 1750psec=1.75nsec
– j:
Time = IF (Mem)
= 500 = 500psec=0.5nsec
• Longest is 2nsec: our fixed clock cycle time!
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 Single Cycle Implementation (cont’d)
• Now let’s consider the cycle times for option b
– Each instruction type has its own cycle time
• Which we have conveniently just calculated 
– What we are really interested in (for comparing
performance) is the average cycle time
• We need some more information (the instruction mix) to
compute this average. Let’s suppose the mix is:
– Loads 24%
– Stores: 12%
– R-type: 44%
– Branch: 18%
– Jump 2%
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 Single Cycle Implementation (cont’d)
• Given this instruction mix, we can compute
the average cycle time for option b as:
– Average cycle time per instruction
= 2 *0.24(lw) + 1.75 * 0.12(sw) +1.5 * 0.44(R-
type) + 1.75 * 0.18(beq) + 0.5 * 0.02(j)
= 0.48 + 0.21 + 0.66 + 0.315 + 0.01
= 1.675 nsec: our average variable clock cycle
time!

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 Single Cycle Implementation (cont’d)
• We can now compare these:
– Option b is clearly faster as it has a shorter average
cycle time, but by how much?

– Thus, option b is about 19% faster than option a!

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 Why single cycle not used
• Modern designs do not use single cycle
implementation
• In single cycle implementation, the clock cycle must
have the same length for every instruction
• Clock cycle is determined by the longest path in the
processor. This is, a load instruction which uses 5 state
elements (functional units) in series [instruction
memory, register file, ALU, data memory and register
file]
• The overall performance of a single cycle
implementation is poor!
– Clock cycle is too long

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