IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO.

12, DECEMBER 2014 2857

A 14 Bit 1 GS/s RF Sampling Pipelined ADC

With Background Calibration
Ahmed M. A. Ali, Member, IEEE, Huseyin Dinc, Paritosh Bhoraskar, Member, IEEE, Chris Dillon, Scott Puckett,
Bryce Gray, Carroll Speir, Jonathan Lanford, Janet Brunsilius, Peter R. Derounian, Member, IEEE, Brad Jeffries,
Ushma Mehta, Matthew McShea, and Russell Stop

Abstract—We discuss a 14 bit 1 GS/s RF sampling pipelined On the other hand, pipeline ADC architectures have been an
ADC that utilizes correlation-based background calibration to attractive choice for the high-performance and high-speed space
correct the inter-stage gain, settling and memory errors. To im- [3], [4]. They are capable of achieving relatively high resolution
prove the sampling linearity and RF sampling performance, the
ADC employs input distortion cancellation and a digital back- and good linearity throughout the whole Nyquist bandwidth.
ground calibration technique to compensate for the non-linear However, achieving a 14 bit ADC at 1 GS/s sample rate using a
charge injection (kick-back) from the sampling capacitors on pipelined architecture presents some significant challenges. The
the input driver. In addition, an effective dithering technique is short amount of time available for the input sampling, flash op-
embedded in the calibration signal to break the dependence of the eration and MDAC settling, coupled with the small level of set-
calibration’s convergence on the input signal amplitude. The ADC
is fabricated on a 65 nm CMOS process and has an integrated
tling error allowed, represent a nexus of speed and accuracy that
input buffer. With a 140 MHz and 2 Vpp input signal, the SNR is are very difficult to accomplish. Using a fine geometry process
69 dB, the SFDR is 86 dB, and the power is 1.2 W. (such as the 65 nm CMOS process used in this work) helps be-
Index Terms—A/D converter, pipeline, ADC, kick-back, distor- cause of the fast MOS devices and their small parasitics. How-
tion cancellation, RF sampling, SHA-less, background calibration. ever, the devices in fine geometry processes have very poor in-
trinsic gain and output resistance. Therefore, the combination
of gain and bandwidth required to achieve the targeted perfor-
I. INTRODUCTION mance and sample rate cannot be realized with conventional

T HE need for high-resolution A/D converters (ADCs) with analog design techniques. Consequently, analog circuits have
high sample rates, good AC performance and IF/RF sam- to be assisted by digital signal processing in the form of back-
pling capability has been unabated. For wireless communication ground calibration techniques to improve the performance and
applications, they enable wider cellular coverage, more carriers, speed, and reduce the power consumption.
and simplify the system design. Generally, higher sample rates In this paper, we describe a 14 bit pipelined ADC with a
also enable larger bandwidths, simplify anti-aliasing filters and sample rate up to 1 GS/s. The ADC is implemented in a 65 nm
provide more flexibility. In addition, RF sampling can lower the CMOS process with an integrated input buffer. The ADC re-
system cost and improve the overall system performance and lies on digital background calibration of the inter-stage gain and
efficiency. settling errors, inter-stage memory errors and input kick-back
Time interleaved architectures have been commonly used errors. Section II describes the ADC architecture. Section III
to implement GS/s ADCs. However, those architectures suffer covers some of the new analog design techniques employed to
from offset, gain, timing and bandwidth mismatches, which improve the performance and lower the power consumption.
cause interleaving spurs that limit the performance and usability Section IV discusses the background calibration techniques uti-
of those converters. Although the offset and gain mismatch lized in this work. Section V presents the ADC measurement
errors can be effectively calibrated, the timing and bandwidth results and finally Section VI concludes the paper.
mismatch effects tend to limit the level of performance that
is efficiently achievable with those architectures, especially at
II. ADC ARCHITECTURE
high input frequencies [1], [2].
A block diagram of the ADC is shown in Fig. 1, which
shows a SHA-less pipelined architecture with an integrated
Manuscript received April 27, 2014; revised July 01, 2014, and August 24, input buffer, five 3 bit stages and a 4 bit backend flash. The sam-
2014; accepted September 10, 2014. Date of publication October 21, 2014; date
pling capacitor is 1.5 pF in the first stage. This is scaled down
of current version November 20, 2014. This paper was approved by Guest Editor
Lucien J. Breems. to 400 fF in the second stage and 100 fF in the following stages,
A. M. A. Ali, H. Dinc, P. Bhoraskar, C. Dillon, S. Puckett, B. Gray, C. Speir, to reduce power consumption and area. To accommodate the
J. Lanford, P. R. Derounian, B. Jeffries, M. McShea, and R. Stop are with
2 Vpp input span, the input buffer uses a 3.3 V power supply,
Analog Devices, Inc., Greensboro, NC 27409 USA (e-mail: [Link]@analog.
com). while the reference and MDAC amplifiers use a 2.5 V supply.
J. Brunsilius and U. Mehta are with Analog Devices, Inc., San Diego, CA Over-voltage protection circuitry and clamps are implemented
92131 USA.
on-chip to ensure that no 65 nm device is stressed beyond its
Color versions of one or more of the figures in this paper are available online
at [Link] reliability limit. The flashes, the clocks, and the digital circuitry
Digital Object Identifier 10.1109/JSSC.2014.2361339 use a 1.2 V supply.

0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See [Link] for more information.
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2858 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

Fig. 1. Block diagram of the pipelined ADC. Input sampling capacitance is 1.5 pF. The following stages are scaled down to reduce power consumption.

The input buffer is required to improve the distortion, reduce The capacitor mismatches of the first three stages need to
the kick-back from the ADC sampling network and make it be calibrated to achieve the desired linearity. Since capacitor
easier to drive. Although it increases the power and noise of the mismatches are independent of supply, temperature and sample
ADC, a highly linear input buffer is essential to provide the low rate, they can be factory calibrated. This is done by using digital
impedance required to achieve the targeted linearity, especially coefficients in the digital correction logic that scale the different
at the GHz sample rates. sub-ranges appropriately to correct for both the DAC and gain
The first stage of the pipeline is shown in Fig. 2. During the errors that are due to the capacitor mismatches.
tracking/sampling phase, the input is sampled on the MDAC As shown in Fig. 2, the same capacitors are used for input
sampling capacitances and the flash. The sampling switch sampling and the DAC operation. This helps improve the
and the bootstrapped switch are turned on. residue amplifier’s feedback factor and hence substantially re-
During the hold/gain phase, the flash comparators make their duces the noise and power consumption. However, this creates
decisions and propagate them to the DAC switches, which non-linear charge injection on the input due to the DAC charge
connect the same MDAC capacitances to either Vref or Vref stored on the capacitors in the previous gain phase. A narrow
depending on the flash bits. In addition, the flash reference reset pulse can be used to briefly discharge the sampling
voltages are sampled on the comparator’s input capacitances capacitors before the input sampling starts to eliminate this
for the next sample. In this design, the flash takes about 100 ps kick-back [3], [4]. However, generating this pulse results in
to make its decision. At 1 GS/s, this leaves about 350 ps considerable power consumption. Furthermore, it occupies a
for the residue amplifier (RA) output to settle to the needed portion of the acquisition time, and hence degrades the sam-
accuracy. After accounting for the reference settling and the pling linearity. Alternatively, we employed a new kick-back
amplifier slewing, the amplifier’s small-signal settling is left background calibration technique to correct for this kick-back
with about 250 ps, which translates into a required bandwidth in the digital domain without requiring resetting the capacitors.
of about 6 GHz to settle to the desired accuracy. In addition, This is also covered in Section IV.
the amplifier’s open loop gain needs to be about 90 dB [3],
[4]. This required high gain-bandwidth product is very diffi-
III. ANALOG CIRCUIT DESIGN
cult to achieve with reasonable power consumption. Digital
assistance in the form of background calibration is required A. The Input Buffer
to achieve the desired performance, while reducing the power The input buffer, shown in Fig. 3, is composed of NMOS
consumption. Therefore, the first three stages are background source followers with feed-forward linearization replica capac-
calibrated to correct for the inter-stage gain and settling errors. itors, first proposed in [3]. The feed-forward replica capacitor
A correlation-based calibration technique is used as will be (C1) is equal to the sampling capacitor (Cs) and serves as a way
explained in detail in Section IV. to provide it with its required AC current . This alternative
Another concern at GHz sample rates is the inter-stage path for the load AC current reduces the current variation in the
memory errors, which can result from capacitor dielectric source follower device (M1). Therefore, the follower exhibits
relaxation/absorption and the incomplete resetting of the ampli- significantly better linearity with smaller bias current, and con-
fier and MDAC capacitors. In this work, the inter-stage memory sequently lower power consumption [3]. The improvement is in
errors are calibrated in the background using an extension to the the order of 10 dB and the reduction in power consumption is
correlation-based inter-stage gain error calibration technique as up to 70% [3]. In this implementation, the standing bias current
will be shown in Section IV. is about 30 mA.
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ALI et al.: A 14 BIT 1 GS/S RF SAMPLING PIPELINED ADC WITH BACKGROUND CALIBRATION 2859

Fig. 2. A schematic of the stage MDAC and flash. The flash path provides a non-linear current that is similar and opposite to the non-linear current in the
MDAC path. The reset pulse (dotted line) is shown for illustration, but is not used when employing the kick-back calibration.

Although an exact replica of the load would include a series to reduce the kick-back on the ADC driver. The replica capac-
resistance to represent the input switch in the sampling path, itor performs this function in addition to the distortion reduction
such addition was not necessary to achieve the desired perfor- described above. In this work, the peak current drawn by the
mance, because of the very small value of the switch resis- replica and sampling capacitors is about 10 mA at 2 GHz input
tance and the presence of another resistance in series with C1 frequency.
in the form of 1/gm of the cascode device M3. In addition, a Unlike emitter followers [3], the NMOS devices used
replica switch should be avoided as it introduces a non-linear in source followers suffer from low and non-linear output
impedance at the input of the buffer that would partially de- resistances (rds) that degrade the DC and high-frequency
feat the purpose of the buffer in isolating the input from the non-linearity. This non-linearity of the follower device (M1)
non-linear load of the sampling network. can be improved if the variation in the drain-to-source voltage
It is important to note that the presence of this replica capac- (Vds) is reduced. In this design, this is done by bootstrapping
itor reduces the input impedance of the buffer. However, the the drain voltage of the follower using the level shifting capac-
main goal of this buffer is to reduce the non-linear current flow itance (C2) and the cascode device (M2). This new technique
in the driver circuit, in order to improve the overall linearity. forces the drain voltage to follow the input and source voltages,
Linear current, on the other hand, such as the one drawn by the and hence reduces the variation in the follower’s Vds and
replica capacitor is considered benign enough to be supplied by reduces the non-linearity caused by rds. The level shifting
the driver [3]. Moreover, if the replica capacitor were not used, capacitance (C2) is charged using a switched-capacitor circuit
we would still need to use a decoupling capacitor on the input as shown in Fig. 3.
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2860 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

impedance that causes distortion at the ADC input and the

MDAC path. In this work, the comparator pre-amplifier is
designed to achieve some distortion cancellation at the input
by providing a capacitive non-linearity that is opposite to the
parasitic capacitive non-linearity of the MDAC’s input switch.
This leads to partial cancellation of the non-linear currents,
which reduces the net non-linear current flowing in the input
driver’s impedance and hence improves the input sampling
distortion.
To illustrate this further, we represent the MDAC by the
non-linear impedance Zin in Fig. 4(a). The MDAC is driven
by a signal source Vs with a source impedance Zs. The driver
can represent the ADC input buffer or the external driver, in
the absence of a buffer. The non-linearity of the MDAC’s
impedance causes a non-linear current to be drawn from the
driver ( Iin), and consequently results in a non-linear voltage
drop (Zs Iin) across the driver impedance Zs. This leads to
a non-linear voltage Vin at the input of the MDAC.
To reduce this non-linear voltage drop on the driver
impedance, a compensation path (Zc) in parallel with the
Fig. 3. A simplified schematic of the input buffer. The capacitance C1 is a MDAC path (Zin) can be employed to provide an equal and
replica of the load capacitance Cs. The load current is provided by the replica
capacitance instead of the follower device M1. opposite non-linear current. This new approach linearizes the
current in the source impedance and substantially improves the
distortion at the input of the MDAC, as shown in Fig. 4(b).
In this work, the flash path is utilized to provide this oppo-
B. The Flash Sub-ADC
site non-linearity. Instead of drawing an additional non-linear
The short amount of time (100 ps) available for the sub-ADC current that has traditionally degraded the non-linearity at the
operation makes it a major design challenge. To improve the ADC’s input, we design the flash to generate an opposite non-
comparator’s speed compared to previously reported SHA-less linear current that reduces the overall non-linear current drawn
implementations [3], [4], a single set of capacitors is used to from the ADC driver. The non-linearity in the MDAC path
sample the reference value in the gain phase and connect to the tends to be dominated by the non-linear capacitance of the input
input in the sample phase, thus eliminating the charge redis- switch. Typically, the switch is sized to be large enough to make
tribution time. A high-bandwidth pre-amplifier is used to help its resistance very small, such that its non-linearity does not con-
reset the latch during the sample phase and reduce the kick-back tribute to the sampling distortion. This is desirable because that
from the latch on the input driver. The latch is implemented by non-linear resistance would have a more detrimental effect on
two inverters cross-coupled with level-shifting capacitors that the overall distortion than the switch’s non-linear capacitance.
decouple the Vgs of the PMOS and NMOS devices, allowing This is due to the large sampling capacitance, and hence large
them to be maximized independently beyond what is allowed by current flowing in the switch’s resistance. In addition, reducing
the low supply (1.2 V). This configuration improves the device the switch’s resistance increases the sampling bandwidth, which
strength of the inverters, which reduces the regeneration time enables better linearity.
constant and propagation delay. In addition, during the sample The voltage division due to the bootstrapping operation
phase, these capacitors provide positive feedback on the input causes the Vgs and Vgd voltages of the input switch to be
of the inverters, thereby greatly improving the sampling band- out of phase with the input signal. On the other hand, the
width of the flash. This considerably improves the bandwidth non-linearity of the flash path is designed to be dominated
matching between the comparator and the MDAC sampling net- by the input capacitance of the input devices of the com-
works. In this work, acceptable bandwidth matching is achieved parators’ pre-amplifiers. The Vgs and Vgd voltages of those
up to 3 GHz input frequency without exceeding the stage’s cor- devices tend to be in phase with the input signal. Therefore,
rection range, which enables RF input sampling. It is important the non-linear capacitances of the two paths vary with the
to note that the 100 ps represents the flash propagation delay in input signal in opposite directions. Designing the comparator
the absence of deep meta-stability, using a comparator input of pre-amplifiers with the proper structure and sizing of their
1 mV. On the other hand, the flash comparators’ regeneration devices properly ensures the non-linear current caused by the
time is 9.5 ps. sub-ADC is almost equal in magnitude and opposite in di-
Traditionally, driving the flash path of the converter has been rection to the non-linear current caused by the input switches
detrimental to the linearity of the MDAC path. The redundancy of the MDAC. The cancellation of the non-linear currents
employed in pipelined ADCs makes the distortion in the flash caused by these two paths improves the sampling linearity.
irrelevant. However, the non-linear elements of the flash path In this work, consistent linearity improvement of about 6 dB
lead to a non-linear current flow in the ADC driver. This, in is achieved independent of supply, temperature and process
turn, leads to a non-linear voltage drop across the input driver’s variations.
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ALI et al.: A 14 BIT 1 GS/S RF SAMPLING PIPELINED ADC WITH BACKGROUND CALIBRATION 2861

Fig. 4. (a) A simplified illustration of driving the MDAC with a non-linear input impedance Zin, causing a non-linear current to flow in the source impedance
Zs. (b) Adding a compensation impedance (Zc) in parallel, representing the flash path, reduces the non-linear current in the source impedance.

Fig. 5. A schematic of the MDAC amplifier. V. Positive feedback is used in the first stage to improve the open loop gain. The back-gates of the
second stage’s PMOS devices are AC floated by connecting them to the supply through very high resistances (Rbg).

C. The MDAC Amplifier IV. BACKGROUND CALIBRATION

The MDAC residue amplifier (RA), shown in Fig. 5, is a two
stage Miller compensated amplifier with active cascodes and A. Inter-Stage Gain and Memory Calibration
positive feedback in the first stage, and a differential pair second
stage. The back-gates of the second stage’s PMOS devices are The RA used in the first stage has an open loop gain of about
AC floated to reduce the effective parasitic capacitance on the 75 dB and closed loop bandwidth of about 4 GHz, which are in-
drains of the PMOS devices. This causes the drain capacitances sufficient to achieve the targeted performance. Therefore, back-
(Cdb) to be in series with the n-well capacitances of the devices ground calibration is implemented for the first three pipeline
and hence substantially reduce the capacitance on the drains. stages to correct for inter-stage gain and settling (dynamic) er-
Furthermore, an on-chip inductor is inserted in series with the rors. Since the calibration corrects only for first-order terms,
PMOS load of the second stage. This inductor is optimized to only the linear portion of the settling error is fixed. This is ac-
“tune out” the capacitive load by forming an RLC circuit that ceptable because the slewing time of the amplifier is relatively
has a pair of complex poles, which improves the phase margin short (about 100 ps), and hence doesn’t significantly contribute
and settling across process, supply and temperature, compared to the settling error at 1 GS/s. The technique used in this work is
to a traditional RC circuit. Using this inductance lowered the a correlation-based calibration [5]–[7], where a pseudo-random
power consumption of the amplifier by about 40% compared to calibration signal (dither), which is uncorrelated with the input
traditional designs. signal, is injected in the MDAC, as shown in Fig. 6. The LMS
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2862 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

Fig. 6. A schematic of the dither injection. Cd is the dither capacitance unit and Nc is the number of dither capacitances, which depends on the number of dither
levels. The dither is injected in the gain phase.

algorithm is used to estimate the correction coefficients using B. Input Kick-Back Calibration
the recursive formula:
Another issue at high sample rates is the non-linear kick-back
(1) from the sampling capacitors on the input driver. The MDAC
input sampling network, shown in Fig. 2, uses the same capac-
Where Vd is the dither value, is the residue of the stage itors for input sampling and the DAC operation. This creates
being calibrated and is the algorithm step size. is the non-linear charge injection on the input due to the DAC charge
estimate of the gain coefficient that corrects for inter-stage gain stored on the capacitors in the previous gain phase. The input
and settling errors. buffer provides a low impedance that is capable of driving the
In this work, this algorithm is further expanded to correct for sampling capacitance to the required 14 bit accuracy at 1 GS/s.
possible inter-stage memory errors [8] by incorporating the pre- However, NMOS buffers tend to have relatively poor isolation,
vious dither samples in the correlation calculations as follows: which is in the order of 10 dB in this work. This causes some
of the charge injection to reach the ADC driver network whose
bandwidth is limited by the driver impedance and the ADC input
(2)
capacitance to be about 2 GHz. For 1 GS/s, the acquisition time
Where is the th past dither value and is excluding the clock non-overlap, rise and fall times is about 350
the estimate of the gain coefficient from the th past sample on ps. This results in about 6 bit settling. Since the kick-back is at-
the present th sample. If then is the coefficient tenuated by the first stage’s DAC quantization (3 bits) and the
for the inter-stage gain and linear settling error. If , then buffer isolation (1.7 bits), the kick-back settling error is reduced
is the th memory coefficient. to about 11 bit level. This would limit the performance and re-
The correction and equalization are performed digitally using sult in about 8 LSBs of error in the ADC’s linearity.
FIR filters whose taps are : We employed a new kick-back background calibration to cor-
rect for the non-linearity caused by this kick-back in the digital
domain. Since this non-linear kick-back is proportional to the
(3)
previous DAC values, the previous codes of the first flash are
used to correct for the resulting distortion as follows:
In this work, the inter-stage gain and settling errors are the
dominant source of performance degradation resulting in more
than 5 dB of SNDR degradation. Inter-stage memory errors con- (4)
tribute about 0.6 dB to the performance degradation.
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ALI et al.: A 14 BIT 1 GS/S RF SAMPLING PIPELINED ADC WITH BACKGROUND CALIBRATION 2863

Fig. 7. Dither propagation. Using odd number of dither levels N with an amplitude of of the subrange of the following stage, the dither propagates
to the following stages with the same number of distinct uniformly distributed levels (9). This results in effective dithering of every subsequent stage. With even
number of levels, the dither propagates with reduced number of distinct levels. After one stage, the number of levels is reduced from 8 to 2.

Where is the digital code of the first stage flash and is Since dithering improves the linearity proportionally to the
the ADC output code. The kick-back coefficients number of dither levels, we use the calibration signal to simul-
are obtained using the LMS algorithm by employing dither in- taneously dither the back-end and improve its accuracy. In this
jection that “kicks” the input during the sample phase. This is work, the calibration signals are composed of uniformly dis-
shown in Fig. 6. During the gain/hold phase, the dither is stored tributed multi-level dithers that are injected in the front-end
on the MDAC dither capacitances in a manner similar to the stages and properly propagated to the back-end pipeline. How-
dither injection of the inter-stage gain and memory error cali- ever, unlike previous work [5]–[7], the number of dither levels
bration. On the sample phase, the kick-back dither capacitors are used here is an odd number (N) that is greater than FS/DA,
connected to the input in parallel with the MDAC sampling ca- where FS is the input full-scale amplitude and DA is the dither
pacitors. This causes the dither capacitances to “kick” the input amplitude. Also, the peak-to-peak amplitude of the dither in-
with the stored dither charge, which then gets sampled at the jected in a certain stage is set to be equal to of the
end of the sample phase and digitized with the input signal. The sub-range size of the following stage. As shown in Fig. 7, this
LMS algorithm is used to remove that kick-back dither and to approach ensures dither propagation with the same number of
estimate the kick-back coefficients using the recursive formula: uniformly distributed levels down the pipeline stages without
losing any levels due to folding.
We use nine dither levels in stage 1, three levels in stage 2, and
(5) three levels in stage 3. Therefore, stages 4, 5, and 6 are dithered
by 81 uniformly distributed dither levels, which translate into
Where is the th past dither value and is the about 6.3 bits of additional accuracy. This practically eliminates
estimate of the kick-back coefficient from the th past sample the dependence of the convergence on the input amplitude that
on the present th sample. exists in traditional approaches like [5]. It also increases the cal-
It is important to note that the kick-back coefficients depend ibration’s digital power by about 33% (10 mW) and its area by
on the process, supply, temperature, sample rate and the ADC about 19% (0.1 mm . This increase, however, is very small
driving network. This kick-back calibration algorithm operates compared to the total power and area of the whole ADC. On
in the background in order to adaptively correct for the changing the other hand, compared to [7], this technique does not require
conditions. “residue decorrelators” and does not require different signal in-
C. Background Calibration Accuracy jections based on which stage is being calibrated. It also has the
added benefit of effectively dithering the non-linearity of the
A major problem with background calibration techniques backend pipeline stages.
has been the dependence of the estimated gain value on the
input amplitude [5]–[7]. This is due to the non-idealities of the
V. MEASUREMENT RESULTS
back-end stages that create “jumps” in the transfer function,
and hence cause the gain estimates to change with the input The ADC is implemented with the entire digital processing
amplitude. Although, these jumps may be acceptable for a needed for the calibration on chip. The ADC is driven by a
full-scale signal, they can be very detrimental to the calibration wideband Balun Transformer terminated by a 100 Ohm differ-
signal because of its small amplitude. ential resistance. Careful attention is paid in the board layout to
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2864 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

Fig. 9. INL with and without kick-back calibration.

Fig. 8. Performance comparison at 30 MHz input frequency, versus (a) tem-

perature and (b) supply voltage.

achieve good matching in the input network and to use a Balun

with small amplitude and phase mismatch. In some cases, a cas-
cade of two baluns can be used to improve the matching further.
In this work, the amplitude imbalance is limited to less than 1%,
and the phase imbalance is less than 5 degrees.
Fig. 8 shows the SNR and SFDR performance versus tem-
perature and supply with, and without, background calibration.
The ability of the background calibration to preserve the perfor-
mance across varying conditions is apparent.
Fig. 9 shows the INL, with and without, the kick-back
calibration. In the absence of the kick-back calibration, the
linearity degrades substantially due to the non-linear kick-back Fig. 10. Maximum INL versus sample rate with, and without, the background
memory effect of the DAC charge stored on the input sampling kick-back calibration.
capacitances. The kick-back calibration effectively removes
that degradation across varying conditions. Fig. 10 shows the
maximum INL error versus sample rate, where the effective- The SNR and SFDR performance of the ADC versus the input
ness of the kick-back calibration in correcting for the kick-back frequency is shown in Fig. 12. The die photo is shown in Fig. 13
error is demonstrated. Fig. 11 shows the performance versus and the ADC measured results are summarized in Table I. A
input amplitude with the new calibration running and frozen. comparison with the state-of-the-art is shown in Table II, which
In this test, the results of the new technique are almost identical indicates the figure of merit to be similar or better than the
which indicates that the calibration’s convergence is relatively state-of-the-art. It is interesting to note that most of the prior
independent of the input amplitude. The performance of a art is based on interleaved architectures. The only exception is
traditional calibration approach similar to [5] is also shown on [9], which is also a pipeline architecture. This work has
the same figure. higher sample rate and consumes about half the power of [9].
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ALI et al.: A 14 BIT 1 GS/S RF SAMPLING PIPELINED ADC WITH BACKGROUND CALIBRATION 2865

TABLE I
SUMMARY OF MEASURED RESULTS

TABLE II
COMPARISON OF THIS WORK TO THE STATE-OF-THE-ART. THIS WORK IS FASTER THAN THE PRIOR ART
OF SIMILAR SNDR/SFDR PERFORMANCE [9] AND CONSUMES 50% LESS POWER

Fig. 12. Measured performance versus input frequency. Performance is rela-

Fig. 11. Measured performance at 30 MHz input frequency versus input tively independent of sample rate up to 1 GS/s.
amplitude.

the desired performance. We presented a new dithering tech-

VI. CONCLUSION nique that improves the calibration effectiveness and desensi-
In this paper, we presented a 14 bit 1 GS/s pipelined ADC, tizes the performance to the input amplitude. We also presented
with an integrated input buffer, implemented on a 65 nm CMOS a new non-linear kick-back calibration that is utilized to correct
process. It employs some new analog circuit design techniques for the non-linear kick-back from the sampling capacitors on the
to improve the performance and lower the power consumption. ADC driver. We demonstrated the viability of the background
Furthermore, it relies heavily on background calibration of the calibration algorithms, and presented the silicon performance of
inter-stage gain, linear settling, and memory errors to achieve the whole ADC.
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2866 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 12, DECEMBER 2014

firsts in the high-speed ADC field. Before joining Analog Devices, he was with
Texas Instruments’ Mixed-Signal R&D Labs and Wireless Infrastructure Busi-
ness Unit. His past industrial experience also includes Anacad/Mentor Graphics
and Siemens AG. He was an Adjunct Assistant Professor at the University of
Pennsylvania from 2001 to 2007. He is the principal author of 25 papers and
holds 40 patents. His research interests include analog IC design, high-linearity
sampling, digitally assisted ADCs and signal processing.
Dr. Ali received the S.J. Stein award from the University of Pennsylvania
for an “outstanding Ph.D. in the field of electronics”. He is currently serving
as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS
I: REGULAR PAPERS. He is the recipient of the George Stephenson Foundation
award, the Catalyst Foundation fellowship award, the University of Pennsyl-
vania fellowship, and several academic excellence awards from the Ministry of
Education in Egypt.

Fig. 13. Die micrograph. Half the die is shown because the die is comprised of
a dual ADC (two cores).
Huseyin Dinc received the B.S. degree in electrical
engineering from the Middle East Technical Uni-
versity, Ankara, Turkey in 2000. He received the
ACKNOWLEDGMENT M.S. degree from Texas A&M University, College
The authors would like to acknowledge the contributions of Station, TX, USA, in 2002, and the Ph.D. degree
from the Georgia Institute of Technology, Atlanta,
Liam Noonan, Cindy Block, Todd Freeman, Robert Britton, GA, USA, in 2011. He was granted a scholarship
Allen Trandem, Chad Shelton, Adam Bray, Richard Hanvey, by the Scientific and Technical Research Council of
Darren Combs, and the rest of the High Speed Converters Turkey (TUBITAK) to pursue graduate studies.
Since 2008, he has been with the High-Speed
product line (ADC). The authors would also like to thank the Converters Group, Analog Devices Inc., Greens-
anonymous reviewers for their valuable feedback. boro, NC, USA. His technical interests include high-speed data converters,
digitally-assisted analog circuit design, and low-distortion and low-noise
REFERENCES circuits.
[1] B. Setterberg et al., “A 14b 2.5 GS/s 8-way-interleaved pipelined ADC
with background calibration and digital dynamic linearity correction,”
in IEEE ISSCC Dig. Tech. Papers, 2013, pp. 466–468.
[2] C.-Y. Chen et al., “A 12-bit 3 GS/s pipeline ADC with 0.4 mm and Paritosh Bhoraskar (M’07) received the [Link].
500 mW in 40 nm digital CMOS,” J. Solid-State Circuits, vol. 47, no. degree in electrical engineering from the Indian In-
4, pp. 1013–1021, Apr. 2012. stitute of Technology, Mumbai (formerly Bombay),
[3] A. M. A. Ali et al., “A 16-bit 250-MS/s IF sampling pipelined adc India, in 2005, and the M.S. degree in electrical
with background calibration,” J. Solid-State Circuits, vol. 45, no. 12, and computer engineering from the University of
pp. 2602–2612, Dec. 2010. Illinois, Urbana-Champaign, IL, USA, in 2007.
[4] S. Devarajan et al., “A 16 b 125 MS/s 385 mW 78.7 dB SNR CMOS In 2007, he joined the High Speed Converter group
pipeline ADC,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 86–87. at Analog Devices Inc., Greensboro, NC, USA, as a
[5] E. Siragusa and I. Galton, “A digitally enhanced 1.8-V 15-bit design engineer. He has since worked on high-per-
40-MSample/s CMOS pipelined ADC,” IEEE J. Solid State Circuits, formance A/D converter design and development and
vol. 39, no. 12, pp. 2126–2138, Dec. 2004. holds several patents in this area. His interests include
[6] A. Panigada and I. Galton, “A 130 mW 100 MS/s pipelined ADC with analog and mixed-signal circuit design in deep-submicron CMOS process.
69 dB SNDR enabled by digital harmonic distortion correction,” in
IEEE ISSCC Dig. Tech. Papers, 2009, pp. 162–163.
[7] N. Rakuljic and I. Galton, “Suppression of quantization-induced con-
vergence error in pipelined ADCs with harmonic distortion correc- Chris Dillon received the B.S.E.E. degree from
tion,” IEEE Trans. Circuits Syst. I, vol. 60, no. 3, pp. 593–602, Mar. North Carolina State University, Raleigh, NC, USA,
2013. in 1997.
[8] A. M. A. Ali, “Methods and structures that reduce memory effects in After graduating, he began work for Analog De-
analog-to-digital converters,” U.S. Patent 6,861,969, Mar. 1, 2005. vices in the High Speed Converter group as a mixed-
[9] ADS5474, 14b 400 MS/s ADC, Texas Instruments Inc. [Online]. Avail- signal design engineer. He has spent his entire ca-
able: [Link] reer to date designing and developing a wide range
[10] ADS5409, 12b 900 MS/s ADC, Texas Instruments Inc. [Online]. Avail- of circuits for high-speed high-resolution A/D con-
able: [Link] verter products. He has done most of his design work
[11] D. Vecchi et al., “An 800 MS/s dual-residue pipeline ADC in 40 nm in BiCMOS processes, and enjoys the flexibility and
CMOS,” J. Solid-State Circuits, vol. 46, no. 12, pp. 2834–2844, Dec. challenges these processes offer in switched-capac-
2011. itor designs. He holds several U.S. patents related to high-speed circuit design,
[12] J. P. Keane et al., “Digital background calibration for memory effects with more pending.
in pipelined analog-to-digital converters,” IEEE Trans. Circuits Syst. I,
vol. 53, no. 3, pp. 511–525, Mar. 2006.

Ahmed M. A. Ali (M’99) received the [Link]. and Scott Puckett received the B.S. degree in math-
[Link]. degrees, with distinction and highest honor ematics from Southern College, Collegedale, TN,
(summa cum laude), in electrical engineering from USA, in 1991, and the B.S.E.E., M.S., and Ph.D. de-
Ain Shams University, Cairo, Egypt, in 1991 and grees from the University of Tennessee, Knoxville,
1994, respectively. He received the Ph.D. degree TN, USA, in 1995, 1998, and 2001.
in electrical engineering from the University of He currently works as a mixed-signal design engi-
Pennsylvania, Philadelphia, PA, USA, in 1999. neer for Analog Devices, Greensboro, NC, USA.
He is currently a Principal Design Engineer with
the High Speed Converters Group (ADCs) at Analog
Devices, Greensboro, NC, USA, where he has led the
design and development of several of the industry
Authorized licensed use limited to: Nithin Poduval. Downloaded on June 06,2026 at 06:44:31 UTC from IEEE Xplore. Restrictions apply.
ALI et al.: A 14 BIT 1 GS/S RF SAMPLING PIPELINED ADC WITH BACKGROUND CALIBRATION 2867

Bryce Gray received the B.S.E.E. and M.S.E.E. de- Brad Jeffries received the B.S. degree in electrical
grees from the University of Tennessee, Knoxville, engineering and the B.S. degree in computer en-
TN, USA, in 1988 and 1990, respectively. gineering from North Carolina State University,
He joined Analog Devices in 1995 and is an IC Raleigh, NC, USA, in 2000. He received the M.S.
Design Engineer and Layout Manager for the High degree in electrical engineering from NTU School
Speed Converters group in Greensboro, NC, USA. of Engineering and Applied Science at Walden
His design work includes comparators, track & holds, University in 2006.
pipeline ADCs and ESD protection circuits. Before He joined Analog Devices, Greensboro, NC, USA,
joining Analog Devices, he worked at Battelle as an in 2000.
Analog Designer Engineer.

Carroll Speir received the B.S.E.E. degree from Clemson University, Clemson, Ushma Mehta received the B.E. degree in elec-
SC, USA, in 1996. tronics engineering from Mumbai University,
He is a design engineer at Analog Devices Inc. (ADI), Greensboro, NC, USA. India, in 2006, and the M.S. degree in computer
In his 18 years at ADI, he has worked on a variety of digital and mixed-signal engineering from North Carolina State University,
ASICs/ASSPs targeted for the communications market. Raleigh, NC, USA, in 2007.
She has been working for Analog Devices, Inc.,
San Diego, CA, USA, since January 2008. She is
a digital designer, primarily focused on high-speed
Jonathan Lanford received the M.S.E.E. degree data converters.
from North Carolina State University, Raleigh, NC,
USA, in 2003, with distinction and highest honor
(summa cum laude).
After graduating, he joined Analog Devices,
Greensboro, NC, USA, where he is currently Matthew McShea received the B.S. degree in
an analog design engineer with the High-Speed electrical engineering from the University of Kansas,
Converter Group, aiding in the implementation of Lawrence, KS, USA, in 2000, and the M.S. degree
calibration solutions for world-class ADCs. He has from the University of Colorado, Boulder, CO, USA,
also designed and taped out a variety of high-speed in 2005.
ADC circuits, as well as shepherded the release of He has worked in industry for over 13 years as
numerous high-performance high-speed 12 and 14 bit ADCs. Previous to the a design engineer at Lucent Technologies, Avaya,
converter group, he spent several years designing RF and mixed-signal produc- RFMD, and Analog Devices on high-performance
tion test for fully integrated transceivers supporting IEEE 802.16 standards. FPGA and ASIC digital designs.

Janet Brunsilius received the B.S. and [Link]. de-

grees in electrical engineering from the University of
California, San Diego, CA, USA. Russell Stop has worked for Analog Devices for
In 2000, she joined Analog Devices, San Diego, 20 years. His job responsibilities have included test
CA, USA, as a Design Engineer in the High Speed development, mixed-signal design, verification and
Converter Group. Since then, she has been involved project/team management.
in the design and development of a variety of ICs
for communications, instrumentation, and medical
imaging applications.

Peter R. Derounian (M’05) received the B.S. de-

gree in electrical engineering from Clarkson Univer-
sity, Potsdam, NY, USA, in 2003, and the M.S. degree
in electrical engineering from the University of Cal-
ifornia, Davis, CA, USA, in 2005.
He joined Analog Devices, Greensboro, NC,
USA, in 2005, where he currently works on analog
and mixed-signal circuits for high-speed pipelined
ADCs.

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