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Dr. Ch Amarendra
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6 Design of Active Fault-Tolerant Control System for
Multilevel Inverters to Achieve Greater Reliability with
Improved Power Quality
Abstract. In recent times, multilevel converters have risen in importance in renewable energy systems because they help
1
in improving power quality and make grid synchronization better. A multilevel converter is a power electronic device that
is able to deliver multiple voltage steps as its output terminal, generates voltage levels that better replicate a sinusoidal
31
signal. Because of this, the harmonic content gets reduced and the overall performance of the system becomes better. But
28
alongside, the operational efficiency of the converter mainly depends on the health of its switching devices. The failure of
4
a single switch can lead to an increase in THD or complete shutdown of the system. In this work, an 11-level Fault-Tolerant
Cascaded H-Bridge Multilevel Inverter (FT-CHB-MLI) is put forth to improve both reliability and power quality when
4
compared with the conventional 7-level system. To make the system fault tolerant, a Fault Detection and Isolation (FDI)
2
unit is added. This unit continuously checks the condition of the switches, detects the faulty one, and then replaces it with
1
a standby redundant switch. For identifying the fault, Total Harmonic Distortion (THD) and the normalized output voltage
14
factor are used. The switching pulses are generated using the Phase Disposition Pulse Width Modulation (PD-PWM)
methodology as it gives superior harmonic capability exceeding many other traditional schemes. The proposed 11-level
29
FT-CHB-MLI is designed and tested in MATLAB/Simulink. The simulation results validate that the proposed inverter
gives lower THD and better waveform quality than the existing 7-level inverter. A comparison with previous works
confirms that the proposed design performs better in terms of both power quality and reliability.
1
Key words: Fault-tolerant control, cascaded H-bridge MLI, 11-level multilevel inverter, FDI unit, PD-PWM, THD,
MATLAB/Simulink, Markov chain reliability.
INTRODUCTION
A. Multilevel Inverters
Multilevel inverters, or MLIs, have become very popular in recent years, especially in photovoltaic and renewable
energy systems. The main reason is simple — they can produce output waveforms of better quality, and they can also
1 handle higher power levels. Different converter topologies have been developed over time, specifically cascaded H-
35 bridge converters, neutral point clamped converters, and hybrid multilevel converters. These are especially useful in
8 medium- and high-power applications. They are structured into three tiers: Neutral Point Clamped (NPC), Flying
Capacitor (FC), and Cascaded H-Bridge (CHB) converters. One big advantage is that they generate the output voltage
in small steps. Because of these smaller voltage steps, the waveform becomes smoother, harmonics reduce, noise
decreases, and the power factor also improves. So overall, the power quality becomes much better.
1 B. Structure of a Cascaded H-Bridge MLI
17 Among all multilevel inverter topologies, the Cascaded H-Bridge Multilevel Inverter, or CHB-MLI, ranks among
the most widely used ones as shown in Fig. 1. This is mainly because of its modular structure. In simple words, we
can increase or decrease the voltage levels as desired. That makes this topology flexible and easy to expand. Every H-
bridge cell has four switching devices, and each switch has an anti-parallel diode connected across it. Also, each cell
3 gets its own separate DC source. For an n-level cascaded H-bridge inverter, the total of power switching devices
3
essential is given by (n−1) ×2,along with the quantity of DC sources required is (n−1)/2. The output voltage of the
first cell can be written as:
VCX1 = (S1 − S2) × Edc
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1 where
E dc = DC voltage source,
VCX1 = output voltage of the first power cell,
1 S1 and S2 = switches SW1 and SW2 for switching functions.
2 Additionally, for M number of cells, the desired output voltage associated with the arrangement is calculated as:
EOX = Vcx1 + Vcx2 + Vcx3+ ⋯ + Vcxm
2
FIGURE 1. Schematic diagram of 11-level cascaded H-Bridge multi-level inverter.
9 Every individual H-bridge gives three voltage levels, that is +Vdc, 0, and −Vdc. So when five H-bridge cells are
18
7 connected in series, an 11-level output waveform is obtained. It offers more output voltage levels for the same number
of DC sources and gives a modular and practical design structure.
1 C. Fault-Tolerant Control
Fault-Tolerant Control, or FTC, is used when a mechanism needs to continue working even after some fault
appears in it. A fault does not always mean complete failure right away. It usually means that the actual system output
is no longer matching the expected output. So the main aim of FTC is to stop a fault from turning into a total failure.
This becomes very important in systems where uninterrupted operation matters a lot. But there is a small problem here
with the escalation in the number of switches augments, the possibility of faults likewise rises. So even though
multilevel inverters improve performance, they can become more vulnerable if proper protection and fault
management are not used. If the inverter fails, it can cause interruption in power supply, loss of efficiency, and in
30 some cases economic damage too. To handle this, redundancy is often introduced into the system. In active fault-
tolerant control, fault detection, fault isolation, and controller reconfiguration are all included as shown in Fig. 2.
2
FIGURE 2. AFTCS architecture.
D. Literature Review
Many researchers have worked on multilevel inverter designs and fault-tolerant control methods. Daher et al. [1]
discussed different multilevel inverter configurations for stand-alone PV systems and gave a good base for MLI
39 design, but their work did not really go into fault detection. Dekka et al. [2] recommended a five-level inverter with
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reduced DC sources and better voltage balancing, though fault tolerance was not their focus. Some researchers focused
2 more directly on fault tolerance. Abbaspour discussed active fault-tolerant control with respect to nonlinear systems
3 in a general way. Ji et al. proposed a fault-tolerant control strategy for cascaded H-bridge converters using voltage
2 injection methods, but that method may not suit every possible inverter configuration. Ahmed et al. proposed a fault-
tolerant H-bridge system, but the THD reported there was around 48.3%, which is very high from a power quality
point of view. So, when all these works are looked at together, one thing becomes clear. Many systems either improve
power quality or improve reliability, but fewer systems try to improve both at the same time in a balanced way. In the
38 present work, an 11-level FT-CHB-MLI is proposed to achieve both these goals together. The complete system is
19 implemented in MATLAB/Simulink, and the results show that the THD is reduced to 9.87%, while the reliability of
the inverter is also improved significantly.
METHODOLOGY
A. 11-Level Cascaded MLI
34 The suggested 11-level cascaded multilevel inverter is built with five H-bridge cells connected in series as
37 displayed in Fig. 3. Each H-bridge has four MOSFET switches, so the complete inverter uses twenty MOSFETs in
5
total. Each H-bridge cell is supplied by its own 100 V DC source. Since five such cells are connected in cascade, the
21
overall peak output voltage reaches 500 V.
32
FIGURE 3. MATLAB/Simulink model of 11-level CHB MLI.
2 B. Phase Disposition Sinusoidal Pulse Width Modulation
10 Regarding controlling the switching elements, Phase Disposition Pulse Width Modulation (PD-PWM) is used as
9 shown in Fig. 4. This is one of the most used PWM techniques in multilevel inverters because it gives lower harmonic
13 distortion and a better output waveform. In PD-PWM, all the carrier signals are kept in the same phase and with the
24 same frequency. For N-level inverter, the sum of carrier signals required is N−1. So, for an 11-level inverter, ten
carrier signals are needed. Out of these ten carriers, five are placed above the zero axis and five below it. Since all of
them are in phase, the carrier signals produce the required gate pulses for the MOSFETs. This switching method is
selected because it provides good harmonic performance and is quite suitable for multilevel inverter applications.
2
FIGURE 4. MATLAB/Simulink model of PD-PWM. FIGURE 5. Algorithm for fault diagnosis.
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1 C. Fault Analysis of an Open-Circuit Switch for an 11-Level CHB Inverter
In practical inverter systems, switch faults can happen for many reasons. Sometimes it may be because of sudden
load variation, a gate driver problem, thermal stress, or semiconductor damage. In general, there are two types of
20 switch faults namely open-circuit faults and short-circuit switch faults. In this work, only open-circuit switch faults
36
5 are considered. For a single-phase 11-level CHB inverter, 20 switches are used. If it is enlarged to a three-phase
5
system, then the total number of switches becomes 60. So finding the exact faulty switch directly is not easy. That is
why a fault diagnosis method is used. The detection process is carried out in two steps. First, Total Harmonic
22 Distortion is measured. Then, the normalized voltage factor is calculated as depicted in Fig. 5. The THD of the output
voltage is obtained using FFT analysis. If one phase contains a faulty switch, then the THD of that phase becomes
much higher. Once the faulty phase is identified, the next step is to locate the exact switch. For that, the normalized
1 voltage factor is used. It is expressed as the ratio of the average phase voltage to the Park’s transformed voltage
quantity.
2 D. Simulation Circuit
25 The entire proposed 11-level fault-tolerant cascaded H-bridge inverter is implemented in MATLAB/Simulink as
2 depicted in Fig. 6. The complete model includes the Fault Injection Unit, Fault Control Block, PD-PWM Unit, Fault
2
Detection and Isolation Unit, and 11-Level CHB-MLI section. The Fault Injection Unit (Fig. 7) is used to create a
fault intentionally in any one of the 20 MOSFET switches. Once the fault is introduced, the Fault Control Block
responds to it. If the switch is healthy, it passes a logic value of 1; if not, it is zero after a reduced time of 0.2 seconds
as shown in Fig. 8.
11
FIGURE 6. Proposed 11-level FT-CHB MLI model.
FIGURE 7. Fault injection unit. FIGURE 8. Fault tolerant control block
1
.
The FDI unit is heart of the whole model as shown in Fig. 9. It checks the condition of the main MOSFET and the
standby redundant MOSFET. In normal operation, only the main MOSFET is active, while the redundant one remains
23 off. When a fault is detected, the defective switch is isolated and the rebundant switch is turned on, as shown in Fig.
10, after a very small delay. In this way, the inverter can continue operating even after the switch fault happens. Of
course, some assumptions are made in the model. The switching is assumed to happen instantly, and switch losses are
neglected. Also, because hardware redundancy is added, the physical size, cost, and complexity of the system increase
a little. If both the primary and redundant switch fail together, then the system cannot continue. Still, for a single
switch fault, the proposed approach works effectively.
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FIGURE 9. FDI unit. FIGURE 10. Internal blocks of FDI.
RELIABILITY ANALYSIS
To check how reliable the proposed inverter is, Markov chain analysis is used. One of the main parameters used
12 in reliability studies is Mean Time to Failure, or MTTF. The MTTF is written as:
MTTF = ∫0 ∞ R(t) dt
It may equally be written in a simpler way as the inverse of failure rate:
MTTF = 1 / λ
33 From this, the reliability function can be written as:
R(t) = P1(t) = e−2(2N−1)λ t
0
For the complete inverter, the failure rate depends on the sum of switching elements used. If λ0 is the failure rate
of one MOSFET switch, then the overall failure rate of the inverter becomes: λ1 = (2N − 1)λ. If no fault-tolerant control
is used, then the MTTF becomes lower because the inverter fails once an important switch stops working. But when
fault-tolerant control is added, the total reliability becomes a combination of different operating states represented by
the Markov probabilities. In that case, the reliability function is expressed as:
16 R(t) = P1(t) + P2(t) + P3(t) + P4(t)
1 RESULTS AND DISCUSSIONS
The simulation results of the proposed 11-level cascaded H-bridge inverter are shown in Fig. 11. In normal case
7 the inverter produces a peak output voltage of 500 V. The FFT analysis shows that the total harmonic distortion is
27
9.87%. This is quite low compared to the lower-level inverter systems, and it confirms that the 11-level configuration
1 gives better power quality.
FIGURE 11. THD without fault. FIGURE 12. THD with fault.
Now, when the FTC is activated as shown in Fig. 13, the output waveform comes back to normal. The peak voltage
is restored to 500 V and the THD is brought back down to 9.87%. So basically, the system recovers and continues
operating with almost the same performance as before the fault.
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FIGURE 13. THD with FTC.
This clearly shows that the proposed FTC strategy is effective. It not only detects the fault, but also isolates it and
restores normal operation. So the main goal of improving both reliability and power quality is achieved.
15 COMPARISON WITH EXISTING WORK
When the proposed work is compared with existing work, the proposed 11-level FT-CHB-MLI achieves a THD
of 9.87%, which is much lower than the 7-level system and clearly better than the other existing works. So, the
proposed system is not just giving lower harmonic distortion, it is also providing better operational continuity during
faults. This comparison makes one thing clear this frame work 11-level inverter performs better than the conventional
2 7-level inverter in terms of waveform quality, THD reduction, and reliability as shown in Table 1.
TABLE 1. Comparison of the previous and proposed model.
11 Type of MLI THD without Fault THD with Fault THD with FTC
7-Level 18.53% 19.20% 18.55%
11-Level 9.87% 12.73% 9.87%
CONCLUSION
26 The complete model is tested in MATLAB/Simulink, and the results show that the proposed inverter performs
better than the conventional lower-level inverter systems. Under fault-free condition, the inverter gives a THD of
9.87%. When a fault occurs without FTC, the THD rises to 12.73% and the output voltage drops. But when FTC is
enabled, the inverter recovers successfully, the output voltage is restored, and THD comes back to 9.87%. This proves
that the proposed system can maintain both reliability and power quality in a much better way.
REFERENCES
1. S. Daher, J. Schmid, and F. L. M. Antunes, “Multilevel inverter topologies for stand-alone PV systems,” IEEE
Trans. Ind. Electron., vol. 55, no. 7, pp. 2703–2712, Jul. 2008, doi: 10.1109/TIE.2008.922601.
2. A. Dekka, O. Beik, and M. Narimani, “Modulation and voltage balancing of a five-level series-connected multilevel
inverter with reduced isolated direct current sources,” IEEE Trans. Ind. Electron., vol. 67, no. 10, pp. 8219–
8230, Oct. 2020, doi: 10.1109/TIE.2019.2949537.
3. S. A. González, M. I. Valla, and C. F. Christiansen, “Five-level cascade asymmetric multilevel converter,” IET
Power Electron., vol. 3, no. 1, p. 120, 2010, doi: 10.1049/iet-pel.2008.0318.
4. S. S. Lee, “Single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter,” IEEE
Trans. Power Electron., vol. 33, no. 10, pp. 8204–8207, Oct. 2018, doi: 10.1109/TPEL.2018.2805685.
5. G. Konstantinou, S. R. Pulikanti, M. Ciobotaru, V. G. Agelidis, and K. Muttaqi, “The seven-level flying capacitor
based ANPC converter for grid integration of utility-scale PV systems,” in Proc. 3rd IEEE Int. Symp. Power
Electron. Distrib. Gener. Syst. (PEDG), Jun. 2012, pp. 592–597.
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