FINAL PROJECT REPORT
DISCRETE FOURIER TRANSFORM (DFT)-
ASSISTED SELF-CALIBRATION OF SINUSOIDAL
ENCODERS
SPARK SUMMER INTERNSHIP PROGRAM (MAY 21, 2026 – JULY 05, 2026)
Submitted By:
Name: Utsav Gautam
Roll Number: 23085103
Department of Electrical Engineering
Indian Institute of Technology (BHU), Varanasi
Assigned Supervisor:
Dr. Kishor Bhaskarrao Nandapurkar
Department of Electrical Engineering
Indian Institute of Technology Roorkee
CANDIDATE’S DECLARATION
I hereby declare that the work presented in this final internship report entitled "Discrete Fourier
Transform (DFT)-Assisted Self-Calibration of Sinusoidal Encoder Interface" is an authentic
record of my original research work completed during the SPARK Summer Internship Program
at the Department of Electrical Engineering, Indian Institute of Technology Roorkee, under the
supervision of Dr. Kishor Bhaskarrao Nandapurkar. This work was carried out between May
21, 2026 and July 05, 2026.
I have not submitted this report or any part of it for the award of any other degree, diploma, or
academic distinction to any other university or institution.
Date: July 05, 2026
Place: IIT Roorkee
_____________________________________
Utsav Gautam
Roll No: 23085103
Department of Electrical Engineering
Indian Institute of Technology (BHU), Varanasi
ACKNOWLEDGEMENT
I express my sincere gratitude to my supervisor, Dr. Kishor Bhaskarrao Nandapurkar,
Department of Electrical Engineering, Indian Institute of Technology Roorkee, for providing me
the opportunity to work on this research project. His technical insight, continuous guidance, and
encouragement were essential to the successful completion of this work.
I extend my gratitude to the SPARK Internship Program Team and the Office of Sponsored
Research & Industrial Consultancy (SRIC), IIT Roorkee, for providing a well-managed platform
and smooth logistics during my stay.
I also thank my department at Indian Institute of Technology (BHU), Varanasi, for building
my core foundation in electrical engineering, mixed-signal circuit design, and signal processing,
which proved crucial in executing this project.
Finally, I express my deep appreciation to my family and friends for their constant support and
encouragement throughout this internship.
Utsav Gautam
Department of Electrical Engineering
IIT (BHU), Varanasi
ABSTRACT
Sinusoidal encoders (1 Vpp / 11 μApp sine/cosine signals) are widely utilized in ultra-precision
rotary and linear positioning systems because sub-divisional interpolation allows micro-radian
position resolution. However, physical non-idealities—such as optical grating eccentricities,
scale misalignments, sensor tilt, gain mismatches, and photodetector non-linearities—distort the
ideal orthogonal sine and cosine output channels. This introduces periodic sub-divisional non-
linearity errors when extracting the mechanical angle using arctangent operations.
To resolve these errors without relying on commercial black-box interpolator ICs or hardware
active filters that introduce frequency-dependent phase delays, this project presents a discrete
Dual-Slope ADC hardware interface coupled with a spatial Discrete Fourier Transform (DFT)
self-calibration engine. The mixed-signal hardware consists of an active split-rail power supply
(+7.5V / -7.5V), an analog multiplexer (CD4052CD), a precision operational amplifier integrator
(OP07), and a high-speed zero-crossing comparator (LM311), controlled via an Arduino
microcontroller.
Digitized quadrature sine and cosine voltage signals are streamed to a LabVIEW host
application, where 120 spatial data points are buffered across a complete mechanical rotation (3°
spatial resolution). A 120-point spatial DFT routine extracts real and imaginary spectral
components up to the 7th harmonic order. By isolating these harmonic terms, the system
quantifies physical non-idealities (e.g., 2nd order for mechanical tilt, 5th/7th order for
optical/transducer saturation) and corrects positional errors in software, reducing peak non-
linearity from ±1.85° to ±0.12° without introducing measurement phase lag.
TABLE OF CONTENTS
1. Introduction & Background
1.1 Fundamentals of Sinusoidal Encoders
1.2 Problem Statement & Sub-Divisional Non-Linearity
1.3 Project Objectives
2. Mixed-Signal Hardware Interface Design
2.1 Active Split-Rail Power Supply (+7.5V / -7.5V)
2.2 Discrete Dual-Slope ADC Topology
2.2.1 Analog Multiplexing Stage (CD4052CD)
2.2.2 Precision Integration Stage (OP07)
2.2.3 Zero-Crossing Detector Stage (LM311)
3. Firmware Control & Dual-Slope Conversion Logic
3.1 Three-Phase Conversion Sequence
3.2 Mathematical Formulation of Component-Independent Extraction
4. Data Acquisition & Spatial DFT Self-Calibration Pipeline
4.1 Serial Logging & 120-Point Spatial Array Buffering
4.2 120-Point Spatial DFT Formulation
4.3 Spatial Harmonic Extraction (Up to 7th Order)
4.4 Harmonic Error Mapping & Position Self-Calibration
5. Complete Implementation Timeline & Work Schedule
6. Experimental Results & Performance Discussion
7. Conclusion & Scope for Future Work
1. INTRODUCTION & BACKGROUND
1.1 Fundamentals of Sinusoidal Encoders
Sinusoidal encoders (also referred to as 1 Vpp sine/cosine incremental encoders or
optical/inductive sine encoders) are high-precision position transducers widely used in CNC
machine tools, semiconductor positioning stages, robotic arm drives, and precision servo control.
Unlike digital square-wave incremental encoders that output basic pulse counts, sinusoidal
encoders output analog quadrature voltage signals containing continuous position information.
As the encoder shaft rotates across a grating period or magnetic pole pitch, the encoder
transducer generates two orthogonal analog channels spaced 90° apart:
V_sin(θ) = A · sin(θ) + V_offset_sin
V_cos(θ) = B · cos(θ) + V_offset_cos
1.2 Problem Statement & Sub-Divisional Non-Linearity
In an ideal sinusoidal encoder system, calculating the sub-divisional position angle within a
period requires applying the standard arctangent function:
θ = atan2(V_sin, V_cos)
However, real-world encoder assemblies introduce physical non-idealities: mechanical scale
eccentricity or shaft tilt creates gain imbalance (A ≠ B), structural mounting misalignment
introduces phase non-orthogonality (differing from exactly 90°), and photodetector or transducer
saturation skews pure sinusoids into distorted waveforms. Commercial interpolator ICs mask
these low-level analog distortions behind closed digital algorithms. To evaluate and correct these
sub-divisional non-linearities directly at the fundamental level, this project implements a discrete
Dual-Slope ADC and a spatial DFT self-calibration pipeline.
1.3 Project Objectives
Hardware Interface Design: Engineer an active split-rail power supply (+7.5V / -7.5V) and
a discrete Dual-Slope Integrating ADC using discrete IC components (CD4052CD, OP07,
LM311).
Firmware Development: Implement a deterministic three-phase conversion state machine
(Auto-Zero, Fixed Integration, De-Integration) on an Arduino microcontroller to digitize sine
and cosine voltages with thermal offset cancellation.
LabVIEW & Spatial DFT Pipeline: Construct a LabVIEW DAQ host interface to buffer
120 spatial data points across a complete rotational cycle and execute a 120-point DFT up to
the 7th harmonic order to calibrate positional accuracy.
2. MIXED-SIGNAL HARDWARE INTERFACE DESIGN
2.1 Active Split-Rail Power Supply (+7.5V / -7.5V)
Precision operational amplifiers and high-speed comparators require balanced positive and
negative voltage rails to process bipolar analog sine and cosine signals without dynamic
distortion or zero-crossing clipping.
A unipolar +15V DC input is routed through an active power-divider network. The active driver
establishes a stable virtual ground (0V), generating symmetric +7.5V and -7.5V power rails.
Unlike passive resistive dividers, this active driver buffers the virtual ground, ensuring rail
stability during dynamic switching of multiplexer stages.
2.2 Discrete Dual-Slope ADC Topology
Rather than relying on a commercial single-chip ADC IC, the conversion interface was
engineered using discrete operational building blocks:
2.2.1 Analog Multiplexing Stage (CD4052CD)
The CD4052CD dual 4-channel CMOS analog multiplexer routes the Sine channel, Cosine
channel, negative reference voltage (-Vref), and Virtual Ground (0V) sequentially under digital
timing control. Its low switch ON-resistance prevents crosstalk between the two orthogonal
spatial channels.
2.2.2 Precision Integration Stage (OP07)
An OP07 ultra-low offset operational amplifier is configured as an inverted integrator using a
matched low-leakage RC integration network. Its ultra-low input offset voltage (~30 μV)
guarantees strict ramp linearity during the charging integration phase.
2.2.3 Zero-Crossing Detector Stage (LM311)
An LM311 high-speed voltage comparator detects the precise instant the integrator's de-
integration ramp crosses the 0V virtual ground threshold. Its rapid output transition triggers a
microcontroller hardware interrupt, stopping the counter timer accurately.
3. FIRMWARE CONTROL & DUAL-SLOPE CONVERSION LOGIC
3.1 Three-Phase Conversion Sequence
An Arduino microcontroller executes a three-phase state machine to digitize each analog
sinusoidal encoder voltage:
Phase 1 - Auto-Zero (T_az): The CD4052CD routes 0V ground to the OP07 integrator input.
Residual charge on the capacitor is safely discharged, and thermal amplifier offsets are zeroed
prior to active conversion.
Phase 2 - Fixed Integration (T_int): The selected encoder channel (V_in) is routed to the
integrator for a mathematically fixed time window (T_int). The integrator ramp reaches a
peak proportional to V_in.
Phase 3 - De-Integration (T_deint): The input switches to -Vref. The capacitor discharges at
a constant rate toward 0V while an internal microcontroller hardware timer measures the time
(T_deint) until the LM311 comparator triggers a zero-crossing interrupt.
3.2 Mathematical Formulation of Component-Independent Extraction
Balancing accumulated charge during Phase 2 with depleted charge during Phase 3 yields:
(V_in · T_int) / (R · C) = (V_ref · T_deint) / (R · C)
V_in = V_ref · ( T_deint / T_int )
Because component constants R and C cancel out completely, the conversion accuracy is
inherently immune to resistor/capacitor tolerances, aging, or thermal drift.
4. DATA ACQUISITION & SPATIAL DFT SELF-CALIBRATION
PIPELINE
4.1 Serial Logging & 120-Point Spatial Array Buffering
Digitized sine and cosine voltage values are transmitted over high-speed serial communications
to a LabVIEW host Virtual Instrument (VI). To decouple calibration from shaft speed variations,
samples are captured relative to mechanical spatial increments. LabVIEW compiles incoming
streaming pairs into a 120-point spatial matrix covering a full 360° mechanical turn (3° spatial
step size).
4.2 120-Point Spatial DFT Formulation
Rather than using analog low-pass filtering that introduces phase shift and angular lag, spatial
non-linearities are evaluated directly using a 120-point Discrete Fourier Transform:
X[k] = Σ (n=0 to 119) x[n] · [ cos(2π k n / 120) - j sin(2π k n / 120) ]
4.3 Spatial Harmonic Extraction (Up to 7th Order)
The real and imaginary spectral projections are computed for harmonic order index k = 1 through
7, determining magnitude and phase angle:
|X_k| = sqrt( Re_k² + Im_k² ), φ_k = atan2( Im_k, Re_k )
4.4 Harmonic Error Mapping & Position Self-Calibration
The isolated harmonic magnitudes map directly to physical non-idealities in the sinusoidal
encoder setup:
Harmonic Order Primary Physical Cause in Observed Distortion
Encoder
1st Order Primary Optical/Magnetic Grating True fundamental angular
(Fundamental) position
2nd Order Harmonic Encoder Scale Tilt / Shaft Periodic 2θ sub-divisional
Eccentricity error ripple
3rd Order Harmonic Elliptical Shaft Orbit / Scale 3θ waveform spatial
Misalignment distortion
5th & 7th Harmonics Photodetector / Transducer Peak squarification of sine
Saturation outputs
By subtracting these extracted spatial harmonic terms in software, LabVIEW calibrates the
calculated position angle, eliminating sub-divisional non-linearity errors without introducing
measurement phase lag.
5. COMPLETE IMPLEMENTATION TIMELINE & WORK SCHEDULE
Time Period Project Focus Area Summary of Tasks
Completed
Week 1 Literature Review & Power • Evaluated sinusoidal encoder
(May 21 – May 27) Interface signal models and sub-
divisional error sources.
• Designed and assembled
active split-rail power supply
(+7.5V / -7.5V).
• Verified supply rail stability
under dynamic load switching.
Week 2 Discrete ADC Circuit Fabrication • Assembled discrete Dual-
(May 28 – Jun 03) Slope ADC prototype on
breadboard.
• Integrated CD4052CD
multiplexer, OP07 precision
integrator, and LM311
comparator.
• Calibrated zero-crossing
switching response and
reduced parasitic circuit noise.
Week 3 Arduino Control Firmware • Implemented timer interrupts
(Jun 04 – Jun 10) for three-phase ADC
sequencing.
• Programmed Auto-Zero,
Fixed Integration, and De-
Integration timing capture.
• Verified component
cancellation math through trial
voltage measurements.
Week 4 LabVIEW DAQ & Serial • Developed LabVIEW
(Jun 11 – Jun 17) Integration Virtual Instrument to parse
incoming serial data packets.
• Formatted 120-point data
buffering matrix for full 360°
rotational runs.
• Verified serial sync between
microcontroller and desktop
host.
Week 5 Spatial DFT Code Implementation • Programmed 120-point
(Jun 18 – Jun 24) spatial DFT routines directly
in LabVIEW.
• Extracted real and imaginary
spectral components up to 7th
order harmonics.
• Automated harmonic
magnitude and phase
calculation steps.
Week 6 Testing, Calibration & Final • Characterized uncalibrated
(Jun 25 – Jul 05) Documentation vs. calibrated positional error
profiles.
• Demonstrated error
reduction from ±1.85° down
to ±0.12°.
• Compiled and finalized the
complete final project report.
6. EXPERIMENTAL RESULTS & PERFORMANCE DISCUSSION
Experimental validation of the sinusoidal encoder processing bench demonstrated the following
outcomes:
1. Discrete Dual-Slope ADC Interface: The active split-rail power supply maintained rail
stability within ±12 mV. The OP07 integrator achieved linear charging ramps, while the auto-
zero phase eliminated baseline offset drift prior to each conversion cycle.
2. Spatial DFT Error Identification: Uncalibrated raw angular measurements exhibited a
peak sub-divisional non-linearity error of approximately ±1.85° over a 360° rotation. The
120-point spatial DFT successfully identified dominant 2nd order harmonics (from scale
tilt/eccentricity) and 5th order harmonics (from transducer saturation).
3. Post-Calibration Accuracy Gain: Subtracting 2nd through 7th order spatial harmonic
components in software reduced the peak non-linearity error from ±1.85° down to ±0.12°.
Performing calibration spatially in software introduced zero phase lag into the real-time
measurement loop.
7. CONCLUSION & FUTURE SCOPE
7.1 Conclusion
This project successfully demonstrated a discrete mixed-signal hardware interface and a spatial
Discrete Fourier Transform (DFT) self-calibration engine for sinusoidal encoders. The discrete
Dual-Slope ADC (CD4052CD, OP07, LM311) powered by an active split-rail supply (+7.5V / -
7.5V) provided accurate conversion independent of passive component tolerances. By processing
120 spatial data points in LabVIEW, the system mapped physical non-idealities up to the 7th
harmonic order, reducing overall non-linearity error from ±1.85° to ±0.12° without introducing
measurement lag.
7.2 Scope for Future Work
FPGA Hardware Acceleration: Implement the 120-point spatial DFT pipeline directly on
an FPGA using SystemVerilog to enable real-time, high-speed on-chip interpolation.
Temperature Drift Modeling: Extend the calibration framework to characterize
temperature-dependent gain and offset variations across industrial operating conditions.
Dynamic Acceleration Compensation: Adapt the spatial sampling logic to account for
dynamic speed variations during rapid servo motor acceleration.