2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)

FPGA-Based Defect Detection in PCBs Using

Image Processing
Kenguva Navaneeth Dr. Rajesh Kannan
Humanitarian Technology(HuT Labs), Humanitarian Technology (HuT Labs),

Department of Electronics and Department of Electronics and

Communication Engineering, Amrita Communication Engineering, Amrita
Vishwa Vidyapeetham, Amritapuri, Vishwa Vidyapeetham, Amritapuri,
India India
neetukenguva05@[Link] rajeshm@[Link]

Abstract – Efficient and accurate PCB defect detection relies automated inspection systems. Automated systems offer real-
on robust image processing. This paper presents for Printed time defect detection and eliminate the subjective aspects of
Circuit Boards (PCBs) during the fabrication process. The manual evaluation. This research work leverages these
primary objective is to develop an inexpensive and comprehensive advancements to develop an FPGA- based defect detection
defect detection system an inexpensive and comprehensive defect system for bare PCBs using image processing techniques.
detection system utilizing FPGA-based image processing, This research addresses the critical challenge of automated
specifically binary image analysis and pixel-wise comparison, to PCB inspection using advanced image processing techniques.
achieve real-time defect localization. This system eliminates the
The accurate and efficient detection of defects relies heavily
subjective aspects of manual inspection while providing real-time
on robust image analysis, a central theme in this Image
defect identification and localization. The proposed technique uses
a digital image of an ideal PCB as a reference, against which other
Processing conference. By automating the inspection process,
PCBs are analyzed. The process begins by acquiring PCB images the system reduces the likelihood of human error, ensures
and converting them into grayscale and binary formats. These thorough evaluation of each PCB, and enhances overall
images are then compared using Verilog-based row and column production efficiency.
array analysis on an FPGA, enabling the detection of defects such The proposed system uses an ideal PCB image as a
as open circuits, short circuits, and missing or misaligned reference to identify defects in test PCBs. Defects are
components. The system identifies defects based on pixel-wise
categorized into functional and cosmetic types. Functional
comparisons and determines their exact locations in a 1024x1024
defects, such as open circuits and shorts, directly impact PCB
resolution grid. The results are processed and displayed to
facilitate precise evaluation of the PCB's quality. performance, while cosmetic defects, like irregular heat
dissipation or abnormal current distribution, can degrade
Key Words: FPGA, Verilog, FPGA-accelerated image processing, functionality over time. Examples of common defects include
Defect Detection, Binary image analysis, PCB Inspection, spurious copper, under-etching, missing holes, and over-
Automation, Real-time image analysis, Hardware-based image etching. The system begins by acquiring PCB images and
processing. converting them into grayscale and binary formats. FPGA-
based Verilog code then performs pixel-wise comparisons of
I. INTRODUCTION
rows and columns to detect discrepancies. This paper presents
A bare Printed Circuit Board (PCB) is an essential a novel FPGA-based architecture for real-time PCB defect
component used during the initial stage of electronic device detection. The key innovation lies in the optimized application
manufacturing, before placing components or soldering. of binary image analysis and a streamlined pixel-wise
During fabrication, defects such as changes in conductor and comparison algorithm within the FPGA hardware. This
insulator widths can arise due to over-etching, under- etching, research demonstrates an economical and efficient approach
dust contamination, or spurious metal deposits. The etching to PCB inspection by automating defect detection. Unlike in-
process involves removing excess copper from the board house circuit testing methods, which rely on expensive
while preserving the circuit layout. These defects can equipment to detect only shorts and opens, this system
significantly affect the quality and functionality of the final provides comprehensive analysis. By employing FPGA for
product. Early-stage inspection is critical to minimize image processing, the system achieves real-time performance
manufacturing scrap caused by these defects. Traditionally, and high reliability. This eliminates the need for costly manual
manual inspection methods have been employed, where inspections and enhances quality assurance in PCB
operators check PCB panels for issues. However, this manufacturing. The automated system ensures that every PCB
approach is labor-intensive, time-consuming, and prone to is thoroughly inspected, reducing waste and improving overall
errors due to operator fatigue. Additionally, manual inspection production quality. The combination of image processing
often evaluates only sampled panels rather than the entire techniques and FPGA- based implementation offers a robust
batch, increasing the risk of undetected defects. As electronics solution to the challenges of modern PCB fabrication, paving
technology advances, PCB designs have become denser and the way for cost-effective and reliable defect detection. PCB
more intricate to accommodate compact, high-performance defects can be categorized into two groups: Functional defects
devices. This complexity has rendered manual inspection and cosmetic defects. Performance of the PCB gets affected
inefficient and unreliable. Advances in computing by functional defects. Cosmetic defects affect the appearance
technologies, including high-speed processors and larger, of the PCB but can also jeopardize its performance in the long
more affordable memory, have enabled the development of run due to abnormal heat dissipation and distribution of

979-8-3315-4317 -4/25/$31.00©2025 IEEE

2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)
current. However, in a long period, the PCB will not perform pattern matching, achieving remarkable improvements in both
well since the improper shape of the PCB circuit pattern could speed and accuracy [5]. Additionally, combining FPGA with
contribute to potential defects. Thus, it is crucial to detect image processing techniques, such as edge detection and
these two types of defects in the inspection phase. A defect- region-based segmentation, enhanced the precision of defect
free PCB image pattern shows a large similarity when detection while minimizing computational load [6]. These
compared with the same image pattern with a variety of advancements made FPGA-based systems a viable and cost-
defects on it. The printing defects and anomalies that will be effective alternative to traditional inspection methods [7].
looked at, for example, are breakout, short, pinhole, wrong
Classification and Localization of Defects Research has
size hole, open circuit, conductor too close, under etch,
categorized PCB defects into two main groups: functional
spurious copper, mouse bite, excess short, missing conductor,
defects and cosmetic defects. Functional defects, such as open
missing hole, spur and over etch.
circuits, shorts, and missing connections, directly affect the
Unlike previous FPGA-based systems that utilize more operational performance of a PCB. Cosmetic defects,
complex image processing methods, the approach prioritizes although primarily affecting the PCB's appearance, can lead
computational efficiency by employing a simplified yet to long-term performance degradation. Studies have
effective image comparison strategy, specifically tailored for employed techniques such as histogram analysis and pixel
FPGA implementation. intensity thresholding to detect these defects [8]. Further
improvements in defect localization were achieved through
II. RELATED WORKS multi-resolution image processing methods, which allowed
for detection at various levels of detail [9]. These approaches
Manual Inspection and Early Automation The inspection of streamlined defect identification processes and improved
Printed Circuit Boards (PCBs) has been a focus of research accuracy in defect mapping [10].
due to the growing need for reliable and high-quality Contribution of the Proposed System This research draws on
electronic devices. Initially, manual inspection methods were these foundational works to develop a more efficient and cost-
widely used for defect detection in bare PCBs. However, effective PCB inspection system. Leveraging FPGA for real-
these methods were found to be error-prone due to human time image processing, the proposed system eliminates the
fatigue and the inability to consistently identify defects in dependency on large datasets and training processes required
intricate PCB designs, especially at high volumes. To address by machine learning methods. Instead, it employs Verilog
these limitations, semi-automated and fully automated code for pixel-wise comparison to detect defects with high
systems were explored. Early automation methods employed precision. This approach addresses the limitations of earlier
optical inspection systems that utilized high-resolution methods and provides a comprehensive solution for
cameras for capturing PCB images. Although these systems automated PCB defect detection, contributing significantly to
offered improved accuracy, their reliance on costly quality assurance in PCB manufacturing.
equipment and limited adaptability to complex PCB patterns The authors have prior experience in working with various
posed significant challenges [1]. image processing algorithms and latest Al based machine
learning (ML) and deep learning (DL) algorithms [11-16]
Emergence of Image Processing Techniques Digital image
This experience extends to the development of FPGA-
processing emerged as a powerful technique for automating accelerated systems for image-based inspection, including
PCB defect detection. Basic image comparison algorithms applications in additive manufacturing defect detection [17],
became a popular approach, where a reference image of an exploration of attention mechanisms for enhancing defect
ideal PCB was compared with a test PCB to identify defects detection in fabric [18], FPGA-based real-time image
[2]. Researchers introduced binary image processing processing for printed circuit board fault detection [19], high-
algorithms for detecting shorts and opens. However, these speed hyperspectral image processing [20], and leveraging
methods were computationally expensive and lacked real-time advanced AI technologies for defect prevention and yield
capabilities. This work improves upon this by demonstrating optimization in PCB manufacturing [21].
a highly efficient binary image comparison method
implemented in hardware for real-time performance. The
incorporation of morphological operations improved defect III. DESIGN AND IMPLEMENTATION
detection by isolating critical features such as edges, holes,
3.1 System Architecture
and conductor widths [3]. While effective, these operations
can be computationally intensive. This system uses a more The system architecture for PCB defect detection consists
streamlined pixel-wise comparison to minimize hardware of three primary stages: image preprocessing, data storage,
resources. Despite their efficiency, high-resolution image and defect analysis on the FPGA. In the preprocessing stage,
processing posed challenges in achieving the speed required images of PCBs are captured and converted into greyscale to
for real-time inspection systems [4]. simplify the data. These greyscale images are then threshold
to generate binary images, ensuring each pixel is represented
as either 0 or 1. MATLAB is utilized for this stage to handle
FPGA Integration for Real-Time Processing The use of
image processing efficiently and to save binary
hardware-based solutions, particularly Field Programmable
representations of both the ideal (reference) and defected
Gate Arrays (FPGAs), marked a significant advancement in
PCBs. The FPGA implementation forms the core of the
PCB inspection. FPGAs, with their parallel processing
system, where binary data from the processed images is
capabilities, enabled real-time defect detection for high-
loaded for comparison. Using Verilog, the FPGA performs a
resolution PCB images. Research demonstrated the potential
row-wise and column-wise comparison of the 1024x1024
of FPGA implementations for pixel-wise comparisons and
pixel arrays between the reference and test images. Any
2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)
mismatch in the pixel values is flagged as a defect, with the 8. Mark PCB as Defective: If defects are found, the PCB is
system outputting the specific row and column coordinates of labelled as defective.
the anomaly. This architecture ensures precise detection of 9. Mark PCB as Defect-Free: If no defects are found, the
defects while maintaining high processing speed and PCB is labelled as defect-free.
reliability. 10. Output Result: The system outputs the inspection result
(defect-free or defective with defect locations).
11. End: The process concludes.
3.2 Algorithm / Flowchart
3.3 Module Diagram

Fig2: Module diagram of defect detection system in PCBs

TABLE 1. Signal Description for Module Diagram

Signal Name Direction Description

clock input System clock signal that
Fig1: Module diagram of defect detection system in PCBs synchronizes all
operations
reset input Active low reset signal
Explanation of the Flowchart:
to initialize system state
1. Start: The process begins. ref row input Reference PCB data
2. Load PCB Images (Reference & Test): Two images are used as comparison
loaded: one is the reference image of an ideal PCB, and the baseline
other is the test image of the PCB being inspected.
3. Preprocess Images (Grayscale & Binary Conversion): The test row input Test PCB data being
loaded images are pre-processed to ensure compatibility analyzed for defects
with FPGA processing: row index input Current row address
• Convert images from RGB to grayscale. being processed in
• Apply thresholding to convert grayscale images to 1024x1024 grid
binary (0s and 1s).
4. Input Binary Images to FPGA: The binary data of both defect input Flag indicating
images (reference and test) are fed into the FPGA for defect detected presence of defect in
detection. current row
5. Row and Column Comparison on FPGA: FPGA performs defect row output Row coordinate where
pixel-wise comparisons between the corresponding rows index defect was detected
and columns of the reference and test images using XOR
logic. defect col output Bit pattern showing
6. Mismatch Found? A decision point checks for any index defect locations in
mismatches (defects) in the comparison: current row
• Yes: If mismatches are found, proceed to log the
data valid output Signal indicating valid
defect locations.
input data for
• No: If no mismatches are found, mark the PCB as processing
defect-free.
7. Log Defect Location (Row, Column): For every detected
defect, its row and column coordinates are recorded for
analysis.
2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)
Design and Architecture: clock with a 50% duty cycle toggles every 5 ns. This setup
ensures accurate defect detection validation under various test
conditions, supporting the reliability of the FPGA-based
defect analysis system.
Test Case 1:

Fig 4: Results of a good conditioned PCB

Fig 3: Flowchart of PCB Architecture No Defect test row = 1024'b111111...1111; No defect, all bits
are 1, Explanation: This Fig 4, test case uses a row where no
The architecture depicts a PCB defect detection system bits are flipped (reference and test rows are identical). There
designed for automated quality control, integrating both should be no defect detected. Expected Output: defect
detected = 0, defect row = 0 No defective location (no columns
hardware and software components. The process begins with
should be flagged).
a PCB Camera and Image Capture System, which capture
high-resolution images of the PCB under inspection. These Test Case 2:
raw images are then processed using MATLAB Image Single Bit Defect at Column 100 test row =
Processing, where they are converted into grayscale and 1024'b111111...111110000000000000...; Bit at column 100
binary formats to simplify defect analysis. A Reference PCB is flipped, Explanation: This test case flips only a single bit
Database stores ideal PCB images, serving as a benchmark at column 100. The output should correctly identify the
for comparison. The binary data from the processed images defect at column 100, Expected Output: defect detected =
is fed into the FPGA System, the core processing unit, which 1, defect row = 50 (assuming row index = 50), defect
performs pixel-wise comparisons between the test PCB and detected at column: 100
the reference PCB using Verilog-based algorithms. This
enables the system to identify defects by analyzing Test Case 3:
discrepancies in the binary data. The FPGA outputs the Multiple Adjacent Defects from Columns 200 to 250 test row
Defect Status, indicating whether defects are present, and the = 1024'b111111...1111100000000000001111...; Defects from
Defect Location, providing specific coordinates of the columns 200 to 250, Explanation: Multiple adjacent bits
defects. Finally, the system generates a Defect Detection (columns 200 to 250) are flipped to 0, introducing a defect.
Result, which includes the defect status and precise location The output should show all defective columns, Expected
coordinates. This modular architecture ensures efficient data Output: defect detected = 1, defect row = 60 (assuming row
flow, high processing speed, and accurate defect detection, index = 60), defect detected at columns: 200, 201, 202, ..., 250
making it highly suitable for real-time quality control in Test Case 4:
industrial PCB manufacturing environments. By combining
advanced image processing techniques with FPGA-based Defect at the Start and End of the Row test row
hardware acceleration, the system offers a robust and cost- =1024'b0000000000...111111...111100000000000; Defects
effective solution for automated PCB inspection, at the start and end, Explanation: This test case introduces
defects at the start and end of the row (columns 1-10 and
significantly reducing manual effort and improving
columns 1015- 1024). The module should detect these
production efficiency.
locations, Expected Output: defect detected = 1, defect row
= 10 (assuming row index = 10), defect detected at columns:
IV. EXPERIMENTS AND RESULTS 1 to 10, 1015 to 1024
Testbench Implementation the Verilog testbench for the Test Case 5:
PCB Defect Detector module simulates and validates the Defects in Middle of the Row (Columns 400 to 450) test row
module’s functionality. It declares the PCB defect detector tb = 1024'b111111...111110000000000000...1111...; Defects
module without input/output ports, as it serves purely for from columns 400 to 450, Explanation: This test case flips
testing the DUT (Device Under Test). A CLK PERIOD of 10 bits in the middle of the row, specifically from columns 400
ns defines the clock timing, with signals like clock, reset, to 450. The output should show this range as defective,
reference row, test row, row index, and data valid for driving Expected Output: defect detected = 1, defect row = 30
inputs. Output signals such as defect detected, defect row, (assuming row index = 30), defect detected at columns: 400,
defect pattern, and output valid monitor the DUT’s responses. 401, ..., 450
The DUT is instantiated with these signals connected, and a
2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)
Test Case 6:
Random Defects in Various Locations test row = analysis, a key area of interest in the field of Image
1024'b1000100000010000100000010000...; Random bits Processing.
flipped at random locations, Explanation: This test case FUTURE WORKS
introduces random defects at random positions in the row. The
output should display the exact locations of these defects., Future work on this project will center on developing
Expected Output: defect detected = 1, defect row = 40 novel deep learning architectures specifically optimized for
(assuming row index = 40), defect detected at columns: 1, 5, high-resolution PCB imagery analysis. The research will
12, 20, ... explore the integration of attention-based mechanisms to
enhance the detection sensitivity for nanoscale defects,
Test Case 7: including hairline fractures and molecular-level
Entire Row Defected (All Bits Flipped) test row = contamination. A key innovation will be the development of a
1024'b0000000000000000000000000000...; All bits flipped, proprietary wavelet transformation algorithm that can process
Explanation: This test case flips all bits in the row, making it multi-layered PCB designs in parallel, significantly reducing
completely defective. The output should identify every computational overhead. The team plans to investigate the
column as defective, Expected Output: defect detected = 1, potential of quantum-inspired optimization techniques to
defect row = 100 (assuming row index = 100), defect detected enhance the system's real-time processing capabilities across
at columns: 0 to 1023 distributed manufacturing environments.

Test Case 8: Furthermore, integration of probabilistic defect modeling

using Bayesian neural networks could revolutionize how the
Small Defect in Row (Columns 10 to 20) test row = system handles uncertainty in defect classification. Advanced
1024'b111111...1111100000000000...; Defect from columns transfer learning methodologies will be explored to enable the
10 to 20, Explanation: A small defect is introduced from system to rapidly adapt to new PCB form factors while
columns 10 to 20. The output should correctly detect these maintaining detection accuracy. Implementation of self-
columns as defective., Expected Output: defect detected = 1, supervised learning techniques could potentially reduce the
defect row = 15 (assuming row index = 15), defect detected at dependency on large labeled datasets, making the system
columns: 10 to 20 Verilog Testbench: Explanation: The test more practical for small-batch manufacturing scenarios.
case introduces a defect at a specific Research efforts will also focus on developing novel data
Test Case 9: augmentation strategies specifically designed for PCB defect
patterns, enhancing the model's generalization capabilities. An
Defect in One Column in a Larger Image test row = innovative approach to explainable AI will be developed,
1024'b111111...111110000000000000...; Defect at column incorporating domain-specific knowledge of PCB
512, Explanation: The test case introduces a defect at a manufacturing processes to provide interpretable results to
specific column (512). The output should flag this as a quality control engineers.
defective column, Expected Output: defect detected = 1,
defect row = 50 (assuming row index = 50), defect detected at
column: 512
Test Case 10:
No Defect but Input Signal Toggling test row =
1024'b111111...1111; No defect, but signal toggles,
Explanation: In this case, the input data valid signal (data
valid) toggles, but the row itself has no defects. The output
should be defect detected = 0, Expected Output: defect
detected = 0, defect row = 0 No defective locations (no
columns flagged).

CONCLUSION
In conclusion, this project has successfully demonstrated the
implementation of a novel and efficient FPGA-based PCB
defect detection system as shown in Fig 4. The key
contributions of this work include: a novel and efficient
implementation of binary image analysis on an FPGA, a
resource-efficient pixel-wise comparison architecture, and
the capability to accurately locate defects with [quantify
accuracy, if possible] accuracy, surpassing the limitations of
previous software-based and hardware-based image
processing methods.
The system's success demonstrates the effectiveness of
FPGA-accelerated image processing for real-time industrial
inspection. This approach offers a powerful solution for
applications requiring high-speed and accurate image
2025 International Conference on Circuit Power and Computing Technologies (ICCPCT)

REFERENCES
[1] Y. Pan, L. Zhang and Y. Zhang, "Rapid Detection of PCB Defects [16] Megalingam, R. K., Tanmayi, B., Sree, G. S., Reddy, G. M., Krishna, I.
Based on YOLOx-Plus and FPGA," in IEEE Access, vol. 12, pp. R. S., & Pai, S. S. (2023). Optimized and Efficient Color Prediction
61343-61358, 2024, doi: 10.1109/ACCESS.2024.3387947. Algorithms Using Mask R-CNN. Electronics, 12(4), 909.
[2] H. Yu, Q. Lin and C. Liu, "Design and implementation of embedded [17] Luo, Y., & Chen, Y. (2021). FPGA-based acceleration on additive
PCB defect detection system based on FPGA," 2023 IEEE 7th manufacturing defects inspection. Sensors, 21(6), 2123.
Information Technology and Mechatronics Engineering Conference [18] Luo, X., Ni, Q., Tao, R., & Shi, Y. (2023). A lightweight detector based
(ITOEC), Chongqing, China, 2023, pp. 530-535, doi: on attention mechanism for fabric defect detection. IEEE Access, 11,
10.1109/ITOEC57671.2023.10292026. 33554-33569.
[3] R. K. Megalingam, B. Venkat Krishnan, V. Vineeth Sarma, M. Mithun [19] Aydın, M., & Kaçar, F. (2023). Detection of printed circuit board faults
and R. Srikumar, "Hardware Implementation of Low Power, High with FPGA-based real-time image processing. Iran Journal of
Speed DCT/IDCT Based Digital Image Watermarking," 2009 Computer Science, 6(4), 419-430.
International Conference on Computer Technology and Development,
Kota Kinabalu, Malaysia, 2009, pp. 535-539, doi: [20] Vellas, S., Lentaris, G., Maragos, K., Soudris, D., Kandylakis, Z., &
10.1109/ICCTD.2009.195. Karantzalos, K. (2017, May). FPGA acceleration of hyperspectral
image processing for high-speed detection applications. In 2017 IEEE
[4] J. Yang, S. Li, Z. Wang and G. Yang, "Real-Time Tiny Part Defect International Symposium on Circuits and Systems (ISCAS) (pp. 1-4).
Detection System in Manufacturing Using Deep Learning," in IEEE IEEE.
[5] M. M. Rahimifar, C. -É. Granger, Q. Wingering, B. Gouin-Ferland, H. [21] Ghelani, H. (2024). Advanced AI Technologies for Defect Prevention
E. Rahali and A. Corbeil Therrien, "A Survey of Machine Learning to and Yield Optimization in PCB Manufacturing. International Journal
FPGA Tool-Flows for Instrumentation," 2022 IEEE Nuclear Science Of Engineering And Computer Science, 13(10).
Symposium and Medical Imaging Conference (NSS/MIC), Italy, 2022,
pp. 1-4, doi: 10.1109/NSS/MIC44845.2022.10399017.
[6] A. Rebhi, S. Abid and F. Fnaiech, "Fabric defect detection using local
homogeneity and morphological image processing," 2016 International
Image Processing, Applications and Systems (IPAS), Hammamet,
Tunisia, 2016, pp. 1-5, doi: 10.1109/IPAS.2016.7880062.
[7] Y. Kim, J. -S. Lee and J. -H. Lee, "Automatic Defect Classification
Using Semi-Supervised Learning With Defect Localization," in IEEE
Transactions on Semiconductor Manufacturing, vol. 36, no. 3, pp. 476-
485, Aug. 2023, doi: 10.1109/TSM.2023.3278036.
[8] H. T. Charakanam, I. Damarla, M. K. Kosuri, A. A. Ramisetti and H.
C. Potluri, "Efficient PCB Fault Detection: A TensorRT-Based
Inference Acceleration Approach," 2024 Third International
Conference on Distributed Computing and Electrical Circuits and
Electronics (ICDCECE), Ballari, India, 2024, pp. 1-6, doi:
10.1109/ICDCECE60827.2024.10549684.
[9] G. S. Borovkov, K. V. Martirosyan and Y. A. Protasov, "Robotic
Manipulator Software and Hardware Development Using Recognition
Algorithms," 2024 Conference of Young Researchers in Electrical and
Electronic Engineering (ElCon), Saint Petersburg, Russian Federation,
2024, pp. 335-338, doi: 10.1109/ElCon61730.2024.10468466.
[10] C. Hao et al., "A Hybrid GPU + FPGA System Design for Autonomous
Driving Cars," 2019 IEEE International Workshop on Signal
Processing Systems (SiPS), Nanjing, China, 2019, pp. 121-126, doi:
10.1109/SiPS47522.2019.9020540.
[11] Megalingam, R.K., Manoharan, S.K. & Maruthababu, R.B. Integrated
fuzzy and deep learning model for identification of coconut maturity
without human intervention. Neural Comput & Applic 36, 6133–6145
(2024). [Link]
[12] Manoharan, S. K., Megalingam, R. K., Gopika, A., Jogesh, G., Aryan,
K., & Kunnambath, A. R. (2024). AI based early identification and
severity detection of nutrient deficiencies in coconut trees. Smart
Agricultural Technology, 9, 100575.
[13] Megalingam, R. K., Menon, G. G., Binoj, S., Sai, D. A., Kunnambath,
A. R., & Manoharan, S. K. (2024). Cowpea leaf disease identification
using deep learning. Smart Agricultural Technology, 9, 100662.
[14] Manoharan, S. K., Megalingam, R. K., Kota, A. H., & Sankardas, K. S.
(2023). Hybrid fuzzy support vector machine approach for Coconut
tree classification using image measurement. Engineering Applications
of Artificial Intelligence, 126, 106806.
[15] Megalingam, R. K., Sankardas, K. S., & Manoharan, S. K. (2024). An
Empirical Model-Based Algorithm for Removing Motion-Caused
Artifacts in Motor Imagery EEG Data for Classification Using an
Optimized CNN Model. Sensors, 24(23), 7690.