Electronic Devices

Workbook

Electronics & Communication Engineering

GATE & ESE

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Electronic Devices
Workbook
Electronics & Communication Engineering

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GATE Syllabus
Electronic Devices : Energy bands in intrinsic and extrinsic semiconductors,
equilibrium carrier concentration, direct and indirect band-gap semiconductors.
Carrier Transport: diffusion current, drift current, mobility and resistivity,
generation and recombination of carriers, Poisson and continuity equations.
P-N junction, Zener diode, BJT, MOS capacitor, MOSFET, LED, photo diode and
solar cell.

ESE Syllabus
Basic Electronics Engineering : Basics of semiconductors; Diode/Transistor basics
and characteristics; Diodes for different uses; Junction & Field Effect Transistors
(BJTs, JFETs, MOSFETs); Transistor amplifiers of different types, oscillators and
other circuits; Basics of Integrated Circuits (ICs); Bipolar, MOS and CMOS ICs;
Basics of linear ICs, operational amplifiers and their applications
linear/non-linear; Optical sources/detectors; Basics of Opto electronics and its
applications.
Contents
Sr. Chapters Pages

1. Basic Semiconductor Physics 1 - 19

2. P-N Junction Diode 20 - 31

3. Basics of BJT 32 - 40

4. MOSFET 41 - 54

5. MOS Capacitor 55 - 63

6. CMOS 64 - 71

7. Special Purpose Diodes 72 - 79

 1 Basic Semiconductor Physics
Introduction :
The vast majority of all solid state device on market today are fabricated from a class of material
known as “Semiconductor”.
Since, semiconductor is solid we should discuss how atoms are arranged in the semiconductor
and the main constitutes of atoms i.e. electrons, protons and neutrons, among which we mainly
look into the behaviour of electrons dominantly because it is actually current carrier, surprisingly
in semiconductor the “absence of electron in covalent bond” is also act as current carrier known
as hole.
 Silicon and Germanium are example of Semiconductor.
 Atoms in Semiconductor are arranged in tetrahedral pattern.

Number of atoms per unit volume in Silicon i.e. atomic density is 5  10 atom/cm .
22 3


Number of atoms per unit volume in Germanium is 4.4 10 atom/cm .

22 3

 Silicon and Germanium are intrinsic Semiconductor.
 Temperature, electric field and photon change the behaviour and properties of
Semiconductor.
 As we increase temperature the free electron and holes generations take place in the solid
semiconductor body.
 Natural temperature of 300 K excite the electron present in the covalent bond by providing
energy and electrons are moved out from covalent bond and become a free electron and
the vacant place in the covalent bond is known as hole. Thus electron-hole pair (EHP) is
generated.
 Intrinsic Semiconductor are Insulator at 0 K because no mobile charge carriers are present,
hence the conductivity () is zero.

  nq n  pq p

At 0 K, n  p  0

 At 300 K a the intrinsic concentration of Silicon and Germanium are,

ni  1.5 1010 electron/cm3 for Silicon and

ni  2.5 1013 electron/cm3 for Germanium.

also, ni  n  p

There are two diagrams which will help you to understand the position and energy of electrons
in a semiconductor.
1. Bond Diagram  Covalent Bond between atom of Silicon.
2. Band Diagram  A Graphical plot between energy of electrons and interatomic distance.

Electronic Devices & Circuits 1

1. Bond Diagram

Si
Covalent Bond
Silicon Atom .

Si Si Si

Bounded Electron .
Si

Fig. Bond Diagram of Silicon at 0 K

2. Band Diagram
Energy (eV)

Conduction Band
EC

Bounded Energy Gap ( EG)

Electrons
EV
Valance Band

Allowed Energy x (Interatomic distance) .

States
Fig. Energy Band Diagram of a Semiconductor at 0 K
Where, EC  Lowest energy state of conduction Band,
EV  Highest energy state of Valance Band.
EG  ( EC  EV )  The distance between EC and EV is known as energy gap and it depends
upon temperature.
For Silicon, EG (T )  [1.21  3.6 104 T] eV
For Germanium, EG (T )  [0.785  2.26 104 T] eV
1. Drift Velocity (Vd ) :
qE
Vd 
m*
Where,   Average relaxation time/Mean time, m *  Effective mass of electron or
holes.
2. Mobility (  ) :
Vd q
 
E m*
The mobility of free electron is always greater than the mobility of hole. (i.e.  n   p )
3. Conductivity (  ) :
It’s the property of a material by which it allows flow of current through it.
From Ohm’s Law, J  E
J
  … (i)
E

2 Electronic Devices & Circuits

 also, J  nqn E
Put the value of J into equation (i)
   nq n
the overall conductivity,   n   p
   nq n  pq p
4. Drift Current :
The current in a material due to applied electric field is known as drift current.
In a Semiconductor, the drift current density ( J d )  n E   p E
( J d )  nq n E  pq p E
Also, the Drift current, I d  J d  A
 I d  nq n EA  pq p EA
5. Intrinsic Semiconductor :
At any temperature , n  p  ni
So, i  ni q ( n   p )
also, J  i E
6. Mass-Action Law :
Under Thermal equilibrium condition, np  ni2
EG

Where, n  A0T e
2
i
3 kT

3/ 2

EG
 2mn* kT 
also, ni  NC NV e 2 kT where, NC  2  2 
 h 
3/ 2
 2m*p kT 
NV  2  2 
 h 
7. Charge Densities in a Semiconductor :
 By neutrality of a Semiconductor material, N D  p  N A  n
Where, N D  Donor ion concentration, N A  Acceptor ion concentration
p  Hole Concentration and n  Free electron concentration.
 In thermal equilibrium, minority charge carrier concentration is constant.
 Minority concentration can be increased by increasing the temperature only.
 Majority concentration depends upon Doping concentration.
8. Diffusion Current :
dp( x)
Hole diffusion current density, J p  qDp
dx
Here,
 p1  p2
 x1  x2
 here, J p is " ve".
 p in changing linearly from x1 to x2 ,
dp ( x) p1  p2
i.e.   –ve
dx x1  x2

Electronic Devices & Circuits 3

 Here, ‘+ve’ J p represents the direction of diffusion current due to holes is in positive “x-
direction”.
dn( x) n [concentration of
Similarly, J n  qDn free electron] (cm–3 )
dx n1
Here,
 n1  n2 n2
 x1  x2
 J n is " ve". x(cm)
0 x1 x2
 n in changing linearly from x1 to x2 ,
dn( x) n1  n2
i.e.   –ve
dx x1  x2
Here, ‘– ve’ J n represents the direction of diffusion current due to electrons is in negative
“x-direction”.
 Key Point
In a Semiconductor, both diffusion and drift current exist.
i.e. I total  I diffusion  I drift

9. Contact potential / Built-in-potential :

 p1 
Here, Vbi  V2  V1  VT ln  
 p2 
kT
where, VT   Thermal voltage
q
and, p1 and p2 are concentrations at X1 and X 2 length of
Fig. Non uniformly doped p-
semi- conductor respectively. type semiconductor
10. Einstein relationship :
Dn D p
   VT
n  p
T (0 K )
 VT  volt
11600
 At 300 K (Room Temperature), VT  26 mV or VT  0.026 eV
 Key Point
In a compensated semiconductor
Where we dope donor ( N D ) and acceptor ( N A ) in intrinsic semiconductor the majority
carriers are
Case 1: If N D  N A
N D  N A  N D'
 N D'  n are Majority carrier and resultant semiconductor is n-type.
Case 2 : If N A  N D
N A  N D  N A'
 N A'  p are majority carriers and resultant semiconductor is p-type.

4 Electronic Devices & Circuits

 11. Hall effect :
 sample is n-type
 and placed in an electric and magnetic field both mutually perpendicular
 Then the majority carriers are accumulated at bottom surface of semiconductor ( S2 )
.
 Reason : Lorentz force, Fm  q (vx  Bz )
 Where direction of force will be xˆ  zˆ   yˆ . S1
 Electrostatic force, Fe   E  q IX VH
– ve sign indicates electrons are attracted to + ve
S2 HZ
terminal.
 At equilibrium, Fm  Fe BZ

BZ I X
 Which resuts Hall voltage, VH 
WZ
1 1 1 1
 Hall co-efficient, RH    
 Charge density nq q
 Application of Hall experiment
(i) Mobility and conductivity can be found.
(ii) Type of semiconductor can be detected.
(iii) Charge density can be found.
n
 n  Conductivity  nqn 
RH
p
 Similarly,  p  pq p 
RH
12. Injection of Minority Charge Carriers / Low Level Injection:
 Charge carriers can be generated by either
(a) Light source-Optoelectronic Device
(b) Temperature-Used to increase minority carrier.
(c) Electric Field-Breakdown of device
 Low level Injection Meaning :
Case 1 : n-type semiconductor
Due to light illumination pn  nn0 i.e. injected minority carriers are lesser than
majority carriers at thermal equilibrium.
Similarly,
Case 2 : p-type semiconductor n p  p p0 .
 At steady state :
Generation rate = Recombination rate
i.e. G  R
Excess carriers generated
 Generation rate 
Life time of carriers
p
 Generation rate of holes  (cm3s1 )
p
 Optical generation rate  Gopt

Electronic Devices & Circuits 5

  p ( x)
GL ( x) 
p
pn' (0) 3 1
 Generation rate at x  0 , GL (0)  cm s
p
Generation rate at any distance x.
 x / Lp
pn' (0)e  x / Lp
 GL ( x )   GL (0)e
p
 x 
For linear change in minority, GL ( x)  GL (0) 1  
 Lp 

 Charge carriers lifetime is a function of distance and time.
 With respect to time ‘t’ :
Total concentration at any time ‘t’ of minority charge carriers.
For N-type : pn (t )  pn 0  pn' (t )
t

p
 pn (t )  pn 0  pn' (0 ) e
pn (t) cm3
concentration)

pn' (0 ) pn' ( 0 )
e
pn 0 pn 0
t0 t  p

Here, pn' (0 )  p  Excess carrier

 With respect to distance ‘x’
x

For N-type : pn ( x)  pno  pn' (0 ) e
Lp

 Relationship between Lp ,  p and D p :

L2p  D p  p , in n-type Semiconductor

L2n  Dn n , in p-type Semiconductor
Change in light intensity with distance in a material :
Consider a thin slab of semiconductor which is
illuminated by a beam of light propagating
along the direction of its length (x-direction).
2
Let I be the radiation intensity (in watts/m ) at
a position x from one end of the
semiconductor. If   Absorption coefficient
per unit length, the power absorbed per unit
length is I . The change in the intensity with
distance along the sample length is given by,
dI
  I
dx
Which has solution, I  I 0ex

6 Electronic Devices & Circuits

  Key Point
1. At Steady state,
(Rate of Generation) = (Rate of Recombination)
n p
2. Generation rate of electrons and holes are : Gn  and Gp 
n p
where, ( n, p  excess majority, excess minority carrier concentration and n ,  p 
mean life times of excess carrier concentration)

13. Fermi level :

1
 Fermi dirac probability function, f ( E )eletrons  ( E  EF )/ kT
1 e
1
 Probability of non-existence of electron, f ( E )holes  ( EF  E )/ kT
1 e
where, f ( E )  Fermi dirac distribution function  0  f ( E )  1
f ( E )  Probability of existence of electron in an energy level “E”
f ( E )  Fermi dirac probability function.
(A) The position of Fermi-Level in an “Intrinsic” semiconductor
 ( EC  EF )

(i) n  N C e kT

Where NC  effective density of energy states at the edge of conduction Band ( EC )

3
 m*T  2
and NC  4.82 10  n  15
cm 3
 m 
where, mn*  Effective mass of electron, m  Rest Mass  9.110 31 kg
 ( EF  EV )

(ii) p  NV e kT

3
 m*pT  2

and NV  4.82 10 

15
 cm 3
 m 
(iii) For an intrinsic Semiconductor,
(Concentration of electron) = (Concentration of holes)
i.e., n  p
 ( EC  EF )
EC  EV kT
 ( EF  EV )
N
 NV e EFi   [here, EF  EFi ]
kT
NC e kT
, ln C
2 2 NV
N C NV
Energy gap by using mass-action Law, EG  kT ln
ni2
(B) Location of “Fermi-level” in n-type Semiconductor
 ( EC  EFn )
NC
n  ND , n  N D  NC e kT
, Then, EFn  EC  kT ln
ND
(C) Location of “Fermi-level” in p-type Semiconductor.
 ( EFp  EV )

p  NA , p  N A  NV e kT

NV
Then, EFp  EV  kT ln
NA
Electronic Devices & Circuits 7
 (D) Location of “Extrinsic Fermi-level” with respect to “Intrinsic fermilevel”, also called
Fermi potential energy
ND
For n-type, EFn  EFi  kT ln
ni

NA
For p-type, EFi  EFp  kT ln
ni
(E) Conclusion :
(i) Changing doping concentration (keeping temperature constant)
As doping concentration increases in n-type /p-type semiconductor, Fermi-level moves
closer and closer to the Conduction Band /Valence Band.
(ii) Changing temperature (keeping doping constant)
As temperature increase, the Fermi-level moves closer and closer to centre of EG in n-
type/p-type Semiconductor.
14. Continuity Equation :
 It is based on conservation of charge.
 In n-type Semiconductor,

dn 1  d J n ( x) 
  Gn  Rn
dt q  dx 
By continuity Equation, the increase in the
no. of electrons per unit time within a small
strip x can be calculated by rate of change of the inflow of current within the S.C. strip
and the generation rate subtracted from the recombination rate.

dp 1  d J p ( x) 
For p-type Semiconductor,     Gp  Rp
dt q  dx 

Direct & Indirect Band Gap Semiconductor

S. No. Direct Band Gap Semiconductor Indirect Band Gap Semiconductor
1. The minima of the conduction band The minima of the conduction band
and the maxima of the valence band and the maxima of the valence band
occur at the same value of k. occur for different values of k.
2. This implies an electron making the The smallest energy transition for an
smallest energy transition from the electron requires a change in
conduction band to the valence band momentum.
can do so without a change in
momentum.
3. Direct band gap semiconductors give Recombination in indirect band gap
up the energy released during this semiconductors occurs through
transition (= Eg ) in the form of some defect states within the band
gap, and the energy is released in the
light, that’s why it is used for
form of heat.
optoelectronic applications (e.g.,
LEDs and LASERs).

8 Electronic Devices & Circuits

 S. No. Direct Band Gap Semiconductor Indirect Band Gap Semiconductor
4. E E

hv  E g Ei
Eg

k k

Q.1 A silicon bar is doped with donor in the sample, at T  300 K , will
impurities N D  2.25 1015 atoms/cm3 . be________.
Given the intrinsic carrier concentration [GATE 2014 Set-04, IIT Kharagpur]
of silicon at T  300 K is Q.4 The resistivity of a uniformly doped n-
3
ni  1.5 10 cm . Assuming complete
10 type silicon sampled is 0.5   cm If the
impurity ionization, the equilibrium electron mobility (μ n ) is 1250cm2 /V-sec
electron and hole concentrations are and the charge of an electron is
[GATE 2014 Set-02, IIT Kharagpur] 1.6 1019 coulomb, the donor impurity
3 3
(A) n0  1.5 10 cm , p0  1.5 10 cm
16 5
concentration (N D ) in the sample is
(B) n0  1.5 1010 cm3 , p0  1.5 1015 cm 3 [GATE 2004, IIT Delhi]
(C) n0  2.25 1015 cm 3 , p0  1.5 1010 cm 3 (A) 2 10 /cm (B) 1 10 /cm
16 3 16 3

(C) 2.5  10 / cm (D) 5 10 /cm

15 3 15 3
(D) n0  2.25 1015 cm 3 , p0  1105 cm 3
Q.5 A piece of silicon is doped uniformly
Q.2 A Silicon Sample is uniformly doped
16 3 with phosphorous with a doping
with 10 phosphorus atoms /cm and 16 3
concentration of 10 /cm . The expected
2  1016 3
boron atoms /cm . If all the
dopants are fully ionized the material is value of mobility versus doping
concentration for silicon assuming full
[GATE 1991, IIT Madras]
dopant ionization is shown below. The
(A) n-type with carrier concentration of 19
1016 /cm3 charge of an electron is 1.6  10 C . The
-1
(B) p-type with carrier concentration of conductivity (in S cm ) of the silicon at
1016 /cm3 300 K is ________.
(C) p-type with carrier concentration of [GATE 2015 Set-02, IIT Kanpur]
2 1016 /cm3
(D) n-type with carrier concentration of
2 1016 /cm3
Q.3 Consider a silicon sample doped with
N D  11015 /cm3 donor atoms. Assume
that the intrinsic carrier concentration
ni  1.5 1010 /cm3 . If the sample is
additionally doped with
N A  110 /cm
18 3
acceptor atoms, the
3
approximate number of electrons /cm
Electronic Devices & Circuits 9
Q.6 A dc voltage of 10 V is applied across
an n -type silicon bar having a
rectangular cross-section and length of
1 cm as shown in figure. The donor
doping concentration N D and the
16 –3
mobility of electrons  n are 10 cm
2 1 1
and 1000 cm V s , respecti-vely. The
average time (in μs ) taken by the The slope of the line can be used to
electrons to move one end of the bar estimate
to other end is ________. (A) Band gap energy of silicon ( E g )
[GATE 2015 Set-02, IIT Kanpur]
(B) Sum of electron and hole mobility in
silicon ( n   p )
(C) Reciprocal of the sum of electron
and hole mobility in silicon
( n   p ) 1
(D) Intrinsic carrier concentration of
Q.7 A silicon sample is uniformly doped silicon ( ni )
with donor type impurities with a
16 3
concentration of 10 /cm . The electron Statement for Linked
and hole mobilities in the sample are Answer Q.10 (a) & 10 (b)
1200cm2 /V-s and 400cm2 /V-s The silicon sample with unit cross-sectional
respectively. Assume complete area shown below is in thermal equilibrium.
ionization of impurities. The charge of The following information is given : T = 300 K
0
19
an electron is 1.6  10 C . The , electronic charge  1.6  10
19
C, thermal
resistivity of the sample (in  -cm) is voltage = 26 mV and electron mobility =
____. 1350 cm2 /V-s.
[GATE 2015 Set-01, IIT Kanpur]
Q.8 A heavily doped n-type semiconductor
has the following data :
Hole-electron mobility ratio : 0.4
Doping concentration : 4.2  108 atoms/m3
Intrinsic concentration :
1.5  104 atoms/m3
Q.10a The magnitude of the electric field at
The ratio of conductance of the n-type
x  0.5 m is
semiconductor to that of the intrinsic
semiconductor of same material and at (A) 1 kV/cm (B) 5 kV/cm
same temperature is given by (C) 10 kV/cm (D) 26 kV/cm
[GATE 2006, IIT Kanpur] Q.10b The magnitude of the electron drift
(A) 0.00005 (B) 2,000 current density at x  0.5 m is
(C) 10, 000 (D) 20,000 (A) 2.16 104 A/cm2 (B) 1.08 104 A/cm2
Q.9 In the figure, ln (i ) is plotted as a
(C) 4.32 103 A/cm2 (D) 6.48 102 A/cm2
1
function of , where i is the intrinsic
T Common Data for
resistivity of silicon, T is the Questions 11 & 12
temperature, and the plot is almost
linear. Q.11 Suppose an n-type sample of silicon as
[GATE 2014 Set-04, IIT Kharagpur] a doping density that changes linearly

10 Electronic Devices & Circuits

 from 1015 to 1012 /cm3 over a 1 μm
distance for the given cross sectional
area of 10 6 cm2 and Dn  35 cm 2 /sec .
The diffusion current is
(A) 65 A (B) 56 A
(C)  56 A (D) 86 A (A)  4.4 10
2
(B) 2.2 10
2

Q.12 For the sample given in the above (C) 0 (D) 2.2  10
2

problem what voltage to be applied to Q.15 For the figure assuming p-type
the sample to cross a drift current semiconductor as specimen the
equal in magnitude to diffusion current.
mobility (in cm /V-sec ) of hole is given
2

Assuming doping density 5 1014 / cm3

Bz  0.1 wb/m2 , d y  Wz  3 mm ,
as constant throughout the length
(Given  n  1300 cm 2 /Vsec ).
VH  50 mV , I x  10 A ,   200000 cm

(A) 53.8 mV (B) 1.1 mV

(C) 86.1 mV (D) 9.3 mV
Q.13 The dependence of drift velocity of
electrons on electric field in a
semiconductor is shown below. The
semiconductor has a uniform electron (A) 860 (B) 750
concentration of n  11016 cm3 and (C) 810 (D) 900
Q.16 A p-type silicon is exhibiting Hall effect
electronic charge q  1.6 1019 C . If a
given Bz  0.05 wb/m 2 , E y  750 V/m ,
bias of 5 V is applied across a 1 m
region of this semiconductor, the d y  0.009 m the induced hall voltage in
resulting current density in this region, y direction is
in kA/cm2, is ______. (A) 6.75 V (B) 2.85 V
[GATE 2017 Set-01, IIT Roorkee] (C) 6.54 V (D) 8 V
Q.17 A semiconductor is used as specimen
for measuring Hall voltage Ex and E y
given N D  1020 /cm3 , Bz  100 wb/cm 2 ,
I x  2 mA , Vx  100 V, Lx  1 cm ,
d y  0.1 cm and Wz  0.01 cm the Ex

Q.14 The energy band diagram and the and E y respectively are
electron density profile n(x) in a (A) 100 V/cm, 12.5 V/cm
semiconductor are shown in the (B) 200 V/cm, 13.5 V/cm
figures. Assume that
(C) 300 V/cm, 14.5 V/cm
 qx 
15  kT 
n( x)  10 e cm , with   0.1 V/cm
-3 (D) 100 V/cm, 14.5 V/cm
and x expressed in cm. Given
Common Data for
kT Questions 18 & 19
 0.026 V, Dn  36 cm 2s-1 and
q
Si hall device at T  300 K as the following
D kT
 . The electron current density geometry d  103 cm, w  102 cm, l  101 cm .
 q
The following parameters are measured
(in A/cm ) at x  0 is
2
I x  0.75 mA, Vx  15 V, VH  5.8 V
[GATE 2015 Set-02, IIT Kanpur]
Bz  1000 Gauss  101 Wb/m2
Electronic Devices & Circuits 11
 S1 20
z = 1.5 × 10 cm−3𝑠−1 throughout the
VH
sample. The incident radiation is turned
Ix
d z off at t = 0. Assume low-level injection
to be valid and ignore surface effects.
x The carrier lifetimes are  p 0 = 0.1 µs
w y
and  n 0 = 0.5 µs.
l
S2

Vx

Q.18 Si hall device is

(A) p type (B) n type The hole concentration at t = 0 and the
(C) intrinsic (D) can’t determine hole concentration at t = 0.3 µs,
Q.19 The majority charge carrier concentra- respectively, are
tion will be [GATE 2016 Set-01, IISc Bangalore]
(A) 4.64 1014 cm3 (B) 0.08 1014 cm3 (A) 1.5 10 cm
13 3
and 7.47 1011 cm3
(C) 4.64 1018 cm3 (D) 0.08 1018 cm3 (B) 1.5 10 cm
13 3
and 8.23 1011 cm3
Q.20 A Semiconductor is irradiated with light 3
such that carriers are uniformly
(C) 7.5 10 cm
13
and 3.73 1011 cm3
3
generated throughout its volume. The (D) 7.5 10 cm
13
and 4.12 1011 cm3
semiconductor is n-type with
Q.23 An n-type silicon sample is uniformly
N D  10 /cm . If the excess electron
19 3
illuminated with light which generates
concentration in the steady state is
10 20 electron-hole pairs per cm 3 second.
n  10 /cm
15 3
and if  p  10 μsec , The minority carrier lifetime in the
(minority carriers life time) the sample is 1s . In the steady state, the
generation rate due to irradiation
hole concentration in the sample is
[GATE 1992, IIT Delhi] x
20 3 approximately 10 , where x is an
(A) is 10 e-h pairs/cm /s
integer. The value of x is ________.
24 3
(B) 10 e-h pairs/cm /s [GATE 2015 Set-02, IIT Kanpur]
10 3
(C) is 10 e-h pairs/cm /s Common Data for
(D) Cannot be determined because the Questions 24, 25 & 26
given data is insufficient
An n-type silicon bar is illuminated at one end
Q.21 Under low level injection assumption,
(x = 0) the minority carrier concentration
the injected minority carrier current for
variance is shown in figure below.
an extrinsic semiconductor is
essentially the Given ni  1.5 1010 /cm3 at 3000 K and
[GATE 2006, IIT Kharagpur] D p  13 cm 2 /sec .
(A) Diffusion current
Pn (x) / cm3
(B) Drift current
(C) Recombination current 2 108
1
(D) Induced current 108
e
Q.22 Consider a silicon sample at T = 300 K,
1108
with a uniform donor density N D = 5 ×
1016 cm−3, illuminated uniformly such
x (mm)
that the optical generation rate is Gopt 0.02

12 Electronic Devices & Circuits

Q.24 The electron concentration at thermal position of the fermi level with respect
equilibrium is ________ cm . 3 to the intrinsic level depends on
Q.25 The diffusion length of holes is [GATE 1989, IIT Kanpur]
_________ mm. (A) N A  N D (B) N A  N D
Q.26 The life time of holes is _______ sec . N AND
(C) (D) ni
Q.27 As shown, a uniformly doped Silicon ni2
(Si) bar of length L = 0.1 m with a
Common Data for
donor concentration N D  1016 cm 3 is Questions 30, 31 & 32
illuminated at x = 0 such that electron
and hole pairs are generated at the rate A Ge sample is doped with phosphorous to an
of extent of 1 in 108 . Assume effective mass of
 x electron = half of corresponding true value.
GL  GL0 1   , 0  x  L , Given Ge concentration  4.411022 / cm3
 L
Q.30 The location of fermi level is
where GL0  1017 /cm 3 s .
(A) 1.257 eV below EC
Hole life time is 10 4 s electronic charge (B) 1.257 eV above EC
19
q  1.6 10 C, hole diffusion (C) 0.257 eV below EC
coefficient D p  100 cm /s and low level
2
(D) 0.0257 eV below EC
injection condition prevails. Assuming a Q.31 At what doping level E F coincide with
linearly decaying steady state excess
edge of conduction band?
hole concentration that goes to 0 at x
= L, the magnitude of the diffusion (A) 8.85 1012 cm3 (B) 8.98 1016 cm3
current density at x = L/2, in A/cm2, is (C) 8.85 1018 cm3 (D) 8.81109 cm3
________. Q.32 If impurity concentration is increased
[GATE 2017 Set-02, IIT Roorkee] to 4.411019 /cm3 the location of E F is
(A) – 0.0417 eV above EC
(B) 0.0417 eV above EC
(C) 0.198 eV above EC
(D) – 0.168 eV below EC
Q.28 Silicon is doped with boron to a
Q.33 In an n-type semiconductor fermi level
concentration of 4  10 atoms/cm .
17 3

lies 0.3 eV below conduction band at

Assume the intrinsic carrier
concentration of silicon to be 300 0 K . If temperature is increased to
kT 330 0 K the new position of fermi level
1.5  10 /cm and the value of
10 3
to be
q assume N C to be constant with
25 mV at 300 K. Compared to undoped temperature is
silicon, the Fermi level of doped silicon (A) 0.86 eV below EC
[GATE 2008, IISc Bangalore] (B) 0.198 eV above EC
(A) goes down by 0.13 eV
(C) 0.33 eV below EC
(B) goes up by 0.13 eV
(C) goes down by 0.427 eV (D) 0.56 eV above EC
(D) goes up by 0.427 eV Q.34 Given donor concentration as
Q.29 The Concentration of ionized acceptors 2.63 10 /cm in a Silicon sample. The
19 3

and donors in a Semiconductor are temperature at which fermi level

N A , N D respectively. If N A  N D and ni coincide with edge of conduction band
is the intrinsic concentration, the is (assume M n  m)

Electronic Devices & Circuits 13

 (A) T  3100 K (B) T  1200 K (towards conduction band). The
(C) T  350 K 0
(D) T  300 K 0 conductivity of the bar is [in ( cm) 1 ]
Q.35 In a p-type semiconductor Fermi level (Given ni  11013 /cm3 ,
lies 0.04 eV above valance band if the
n  3500 cm2 /Vsec ,  p  1500 cm 2 /Vsec
concentration of acceptor atoms is
doubled the new position of Fermi level )
is (A) 12.26 (B) 13.92
(A) 0.022 eV above valence band (C) 13.68 (D) 1.168
(B) 0.33 eV above valence band Q.37 Effective mass of electron = thrice
(C) 0.62 eV below valence band effective mass of hole. The distance of
(D) 0.62 eV above valence band fermi level in an intrinsic
Q.36 The fermi level of an n-type Ge bar is semiconductor from the center of
0.2 eV above the intrinsic fermi level forbidden gap is _______ below the
center of EG .

microsecond and 100 centimeter

Common Data for
square per second, the diffusion length
Questions 1 to 3 of carrier is
(A) 0.1 cm (B) 0.01 cm
A pure Ge is doped with donor impurities of
(C) 0.0141 cm (D) 1 cm
1:107 , let ni  2.5 1013 atoms/ cm 3 and total
Q.6 The concentration of holes in a
number of atoms in Ge is 4.42  10 / cm
22 3
semiconductor is as shown in figure. It
Q.1 Find the donor concentration. linearly decreases from x  0 to x  w
(A) 4.42×10 /m
15 3
(B) 44.2×10 /m
15 3 :

(C) 4.42 10 /cm (D) 4.42 10 /cm

15 3 29 3

Q.2 Find the concentration of electron.

(A) 4.42  10 /m (B) 44.2×10 /m
15 3 15 3

(C) 4.42 10 /cm (D) 4.42 10 /cm

15 3 29 3

Q.3 Find the concentration of holes.

11
(A) 1.4110 holes/m3
(B) 1.4110 holes/m
11 3 The potential developed between the
points x (0) and x(w) if the ratio of the
(C) 1.411017 holes/m3
concentrations at x  0 and x  w is
3
(D) 1.4110 holes/m
3
103. Assume room temperature of
Q.4 Which of the following elements act as
270 C.
donor impurities ?
(A) 179.6 mV (B) 431 mV
1. Ag 2. P
(C) 12.4 mV (D) None of these
3. B 4. Bi
Q.7 An n-type semiconductor as a whole is
5. As 6. In
(A) Positively charged
Select the correct answer using the
code given below (B) Negatively charged
(A) 1, 2 and 3 (B) 1, 2, 4 and 6 (C) Positively or negatively charged
depending upon doping
(C) 2, 3 and 4 (D) 2, 4 and 5
(D) Electrically neutral
Q.5 The minority carrier life time and
diffusion constant in a semiconductor Q.8 Fermi level represents the energy level
with probability of its occupation of
material are respectively 100

14 Electronic Devices & Circuits

 (A) 0 % (B) 50 % (A) 0.385 eV (B) 0.485 eV
(C) 75 % (D) 100 % (C) 0.585 eV (D) None of these
Q.9 For the intrinsic semiconductor with
energy gap of 0.7 eV, the position of Common Data for
Fermi-level at 300 K if m p = 6 m e is Questions 16 and 17

(A) 0.35 eV (B) 0.385 eV

A specimen of silicon has a square cross
(C) 0.375 eV (D) 0.405 eV
section of 3  3 mm2 and its length is 5 cm. It
Q.10 The value of forbidden gap for silicon at
is subjected to a voltage of 1 V and the current
the temperature of 350 C .
flowing through it is 6 mA.
(A) 1.21 eV (B) 1.099 V
Q.16 The concentration of free electrons is.
(C) 1.11 V (C) None of the
these (A) 1.6 1021 atoms/m3
Q.11 The Fermi level in an n-type material is (B) 1.6 1015 atoms/m3
expressed as
(C) 1.6 1027 atoms/m3
N  N 
(A) Ec  kTln  c  (B) Ec  kTln  c 
(D) 2.6 1027 atoms/m3
 nn   nn 
Q.17 The drift velocity of electrons is.
N  N 
(C) Ev  kTln  c  (D) Ev  kTln  c  (A) 1.6 m/sec (B) 2.6m/sec
 nn   nn  (C) 3.6m/sec (D) 4.6m/sec
Q.12 The density of impurity atoms that
Q.18 The electron concentration in a sample
must be added to an intrinsic silicon
4 of Ge at 3000 K vary linearly from
crystal to convert it to 10  - m n-type
silicon if e  0.138m2 /V - sec , 1017 /cm3 at x = 0 to 6 1016 /cm3 at
x  2 μm . The current density in the Ge
 h  0.046m 2 /V - sec for silicon, will be
bar is. (Assume n type sample).
(A) 4.528  10 /m (B) 13.586 10 /m
23 3 23 3
(A) 3136 A/cm2 (B) 3136 A/cm2
(C) 1.234 10 /m (D) 9.143 10 /m
17 3 17 3

(C) 2136A/cm2 (D)  2136 A/cm2

Q.13 Excess carriers are generated in a
sample of n-type semiconductor by
Common Data for
shining light at one end. The current
Questions 19 and 20
flow in the sample will be made up of
(A) Diffusion flow of carriers
In germanium semiconductor at T  300 K, the
(B) Drift flow of carrier
impurity concentration are
(C) Both
(D) None of these N d  5 1015 cm 3 and N a  0
Q.14 Due to illumination by light, the Q.19 The thermal equilibrium electron
electron and hole concentration in a concentration n0 is
heavily doped n-type semiconductor,
n and  p respectively. If (A) 5 1015 cm3 (B) 1.15 1011 cm3
increases by
(C) 1.15 109 cm3 (D) 5 106 cm3
ni is the intrinsic concentration then
Q.20 The thermal equilibrium hole
(A) n  p (B) n  p
concentration p0 is
(C) n  p (D) n  p  ni
(A) 3.96 1013 cm3 (B) 1.25 1011 cm3
Q.15 In a p-type semiconductor, the Fermi-
level lies 0.4 eV above the valance
band. If the concentration of acceptor (C) 4.36 1012 cm3 (D) 3.96 1013 cm3
atom is tripled, the new position of
Q.21 A sample of silicon at T  300 K is
Fermi level is (Assume kT  0.03 eV)
doped with boron at a concentration of
Electronic Devices & Circuits 15
 2.5  1013 cm 3 and with arsenic at a (B) Both A and R are true but R is not
the correct explanation of A
concentration of 1.5  107 cm 3 . The
material is (C) A is true but R is false
(D) A is false but R is true
(A) p-type with p0  2.5 1013 cm3
Q.28 Assertion (A) : In intrinsic elemental
(B) p-type with p0  1.5 107 cm3 semiconductors, electrons and holes
are created in pairs.
(C) n-type with n0  1.5 1013 cm 3
Reason (R) : In intrinsic silicon, the
(D) n-type with n0  1.5 107 cm 3 electron mobility is 2.81 times greater
Q.22 Six volts is applied across a 2 cm long than the hole mobility.
semiconductor bar. The average drift (A) Both A and R are true and R is the
correct explanation of A
velocity is 104 cm/s . The electron
(B) Both A and R are true but R is not
mobility is
the correct explanation of A
(A) 4396 cm2 /V-s (B) 3 104 cm2 /V-s (C) A is true but R is false
(C) 6 104 cm2 /V-s (D) 3333 cm2 /V-s (D) A is false but R is true
Q.23 An n – type silicon sample has a Q.29 If an intrinsic semiconductor is doped
resistivity of 5  - cm at T  300 K. The with a very small amount of boron,
then in the extrinsic semiconductor so
mobility is  n  1350 cm 2 / V-s . The formed, the number of electrons and
donor impurity concentration is holes will
(A) 2.86 1014 cm3 (B) 9.25 1014 cm3 (A) decrease
(B) increase and decrease respectively
(C) increase
(C) 11.46 1015 cm3 (D) 1.11015 cm3
(D) decrease and increase respectively
Q.24 Which of the following will serve as a Q.30 If a sample of geranium and a sample
donor impurity in silicon? of silicon have the same impurity
(A) Boron (B) Indium density and are kept at room
(C) Germanium (D) Antimony temperature
Q.25 n-type semi-conductors (A) Both will have equal value of
(A) are-negatively charged. resistivity
(B) are produced when Indium is added (B) Both will have equal negative
as an impurity to Germanium. resistivity
(C) are produced when phosphorus is (C) Resistivity of germanium will be
added as an impurity to Silicon. higher than that of silicon
(D) none of the above. (D) Resistivity of silicon will be higher
Q.26 In the Fermi-Dirac statistics, the than that of germanium
probability of electron, occupation of Q.31 Measurement of Hall coefficient
an energy level equal to the Fermi level enables the determination of
is (A) Mobility of charge carriers
(A) 0 (B) 0.25
(C) 0.5 (D) 1.0 (B) Type of the conductivity and
concentration of charge carriers
Q.27 Assertion (A) : The mobility of the
conduction electrons is greater than (C) Temperature coefficient and
that of holes. thermal conductivity
Reason (R) : Recombination of (D) Fermi level and forbidden energy
electrons and holes obeys a logarithmic gap
decay pattern Q.32 Equation for time dependence of
carriers in reaching a steady state
(A) Both A and R are true and R is the
condition in p-n junction is given by
correct explanation of A

16 Electronic Devices & Circuits

 6
p(t )  5 1010  (4 1012 ) e  t /10 cm 3 ,
then Find the conductivity of
semiconductor, assuming 50 percent of
excess carrier generation rate is given o
3 1 the donors are ionized at 300 K.
by g '  _______ 10 cm s .
18

[  n (Si)  1000,  p (Si)  350,

Q.33 The intrinsic carrier concentration of
Si ( Eg  1.12 eV) at 300 K is
0
n (Ge)  3500,  p (Ge)  1500 are in
1.5 1010 cm 3 then the value of ni for Si cm 2 / V-sec ]
at 400 K (Boltzmann constant
0
(A) 8 ( -cm)1 (B) 12 ( -cm)1
K  8.62 105 eV/K ) (C) 16 ( -cm)1 (D) 10 ( -cm)1
(A) 1.5 1010 cm3 (B) 3.2 1011 cm Q.37 The Si-sample under thermal
equilibrium at with unit cross section
(C) 5.2 1012 cm3 (D) 6.8 1013 cm3
area is shown below
Q.34 For a Si semiconductor, the electron Thermal voltage VT = 26 mV election
mobility  n  1500 cm 2 /Vsec , the hole
charge is q  1.6 1019 C and electron
mobility  p  750 cm /Vsec
2
and
mobility  n  1350 cm2/V- sec.
intrinsic carrier concentration 6 m
ni  1.8 10 /cm .
11 3
The maximum
ND  1016 /cm3
resistivity will be _______ k-cm .
Q.35 For a particular semiconductor sample,
hole concentration
  x  1.2V
P  1013 exp   /cm3 , x  0
The magnitude of electron drift current
 Lp 
density in (A/cm2) is
L p  2  10 3 cm Q.38 In a Si sample the electron
concentration drops linearly from 1017
Electron concentration
cm–3 to 1015 cm-3
 x  If electron diffusion constant is 40
n  2  1014 exp   /cm , x  0
3
cm2/s, the current density due to
 Ln 
electron diffusion current (A/mm2)
Ln  104 cm, D p  20 cm 2 /sec, ______ (up to 1 decimal)
Q.39 All n-type silicon sample is uniformly
Dn  10 cm 2 /sec illuminated which generates 1020 e-
The total diffusion current density at x holes/cm3-sec. The minority carrier
=0
conductivity in the sample in steady
(A) 0.232 A/cm2 (B) 0.658 A/cm2
state is _______ ( /m ) [Mobility  n 
(C) 3.2 102 A/cm2 (D) 3.216 A/cm2 500 cm2/sec]
Q.36 The conductivity of the n-type silicon,
which is doped with N D  1017 cm 3 .

Assignment 1 electron diffusion current is

In a silicon sample the electron D n  35cm /s  .
2

concentration drops linearly from

(A) 9.3 10 A/cm (B) 2.8 10 A/cm
4 2 4 2
1018 cm3 to 1016 cm3 over a length of
2.0 μm . The current density due to the (C) 9.3 10 A/cm (D) 2.8 10 A/cm
9 2 9 2

Electronic Devices & Circuits 17

Assignment 2 (A) 4 1019 cm 3 s1 (B) 4 1014 cm 3 s1
In a GaAs sample the electrons are
moving under an electric field of 5 (C) 4 1024 cm 3 s 1 (D) 4 1011 cm 3 s1
kV/cm and the carried concentration is Assignment 6
3
uniform at 10 cm . The electron
16
A semiconductor in thermal
velocity is the saturated velocity of equilibrium, has a hole concentration of
107 cm/s . The drift current density is p0  1016 cm 3 and intrinsic
(A) 1.6 104 A/cm2 (B) 2.4 104 A/cm2 concentration of ni  1010 cm 3 . The
(C) 1.6 10 A/cm
8 2
(D) 2.4 10 A/cm 8 2
minority carrier life time is 4  40 s .
7

Assignment 3 The thermal equilibrium recombination

A gallium arsenide semiconductor at rate of electrons is
T  300K is doped with impurity (A) 2.5 1022 cm3 s1 (B) 5 1010 cm3 s1
concentration N d  1016 cm3 . The (C) 2.5 1010 cm3 s 1 (D) 5 1022 cm3 s1
mobility  n is 7500 cm /V-s . For an 2
Assignment 7
applied field of 10 V/cm the drift The minimum energy of a photon
current density is required for intrinsic excitation is equal
(A) 120 A/cm2 (B) 120A/cm2 to
(C) 12 104 A/cm2 (D) 12 104 A/cm2 (A) Energy of bottom of conduction
band
Assignment 4
(B) Energy of top of valence band
For a particular semiconductor sample
consider following parameters : (C) Forbidden gap energy
Hole concentration (D) Fermi energy
 x 
 
15  Lp 
p0  10 e cm3 , x  0
Hole diffusion coefficients
D p  10 cm 2 /s
4
Hole diffusion length L p  5  10 cm
Electron concentration
 x 
 
n0  5 10 e 14  Ln 
cm3 , x  0
Electron diffusion coefficients
Dn  25cm2 /s
Electron diffusion length Ln  103 cm
The total current density at x  0 is
(A) 1.2 A/cm2 (B) 5.2 A/cm2
(C) 3.8A/cm2 (D) 2A/cm2
Assignment 5
In a semiconductor n0  1015 cm 3 and
ni  1010 cm 3 . The excess-carrier life
time us 10 6 s. The excess hole
3
concentration is  p  4  10 cm . The
13

electron-hole recombination rate is

18 Electronic Devices & Circuits

 Classroom Questions
1. D 2. B 3. 225 4. B 5. 1.92
6. 100 7. 0.520 8. D 9. A 10. C, A
11. C 12. A 13. 1.6 14. C 15. B
16. A 17. A 18. A 19. B 20. A
21. A 22. A 23. 14 24. 2.25 25. 0.02
26. 0.3 27. 16.02 28. C 29. A 30. C
31. C 32. B 33. C 34. A 35. A
36. A 37. 0.21
Practice Questions
1. C 2. C 3. C 4. D 5. A
6. A 7. D 8. B 9. B 10. B
11. A 12. A 13. C 14. C 15. D
16. A 17. B 18. A 19. A 20. B
21. A 22. D 23. B 24. D 25. C
26. C 27. C 28. B 29. D 30. B
31. B 32. 4 33. C 34. 15.41 35. D
25 to
36. A 37. 4320 38. 39. 0.8
26
Assignment Questions
1. B 2. A 3. A 4. A 5. A
6. C 7. C

Note : For detailed solutions, scan the QR code Given below,



Electronic Devices & Circuits 19

 2 P-N Junction Diode
Introduction :
 A p-n junction diode is two-terminal or two-electrode semiconductor device, which allows
the electric current in only one direction while blocks the electric current in opposite or
reverse direction. The p-n junction, which is formed when the p-type and n-type
semiconductors are joined, is called as p-n junction diode.
 The p-side or the positive side of the semiconductor has an excess of holes and the n-side
or the negative side has an excess of electrons. In a semiconductor, the p-n junction is
created by the method of doping.
1. Built-In Potential ( V0 )
kT N D N A
V0  ln , Open-circuited Potential
q ni2
2. Depletion and Concentration Relation
WN D

(a) N xn0  N x p0 
(b) x p0  
N A  N D
D A

For N D  N A , x p0  W

WN A
Also, xn0 
N A  N D
For N D  N A , xn0  W [ N D  N D and N A  N A ]

3. Junction Voltage
V j  V0  VD
Where, VD  Applied voltage across diode.

4. Law of Junction
Used to find the concentration of carriers crossing the junction when it is biased (p-n
junction)
(a) Concentration of holes in n-region at the junction.
V

pn (0)  pn0 e VT

where, V  Terminal voltages.

Also, concentration of electron in p-region at junction.
V

n p (0)  n p0 e VT

(b) Diode current, I  I  e 0

V
 VT 
1
where,   1 (For Ge ),   1 (by default) and   2 (For Si).
AqD p pn 0 AqDn n p 0
I0    Reverse saturation current
Lp Ln

where, pn 0  Holes in n-side and n p 0  e in p-side.

20 Electronic Devices & Circuits

  Key Point
I   I 0 ( ve sign represents that in Reverse Bias, the flow of current is opposite to the
direction of forward current).
5. Diode Resistance
(1) Static Resistance ( RDC ) :
V1
RDC 
I1
where, V  Cut-in voltage.
(2) Dynamic Resistance ( rac ) :
(a) Various forms of rac [k] in forward bias :
dV V2  V1 1
(i) rac   (ii) rac 
dI I 2  I1 tan 
 VT VT
(iii) rac  (iv) rac 
V
 VT
I  I0
I0 e
VT
(v) rac  [ I  I 0 ]
I
dV
(b) In reverse bias, rac 
dI
In ideal cases, dI  0 [ in R.B ]
dV
 rac  
0
6. Electric Field at Junction
(1) In depletion region :
(No. of ( ) ions)  (No. of (  ) ions)
qA xn 0 N D  qAx p 0 N A
xn 0 N D  x p 0 N A
(2) Electric field at junction, Emax  E0

E (V/cm)

Electronic Devices & Circuits 21

 q N D xn 0  q N A xP 0
E0 max   (Derived using Poisson’s Equation)
 

7. Contact Potential (V0 ) and Depletion Width (W)

1 2  1 1 
(1) V0   E0 W (2) W    V j
2 q  N A ND 
where, V j  V0  VD (junction potential).

8. Diode Capacitance

 Diffusion Capacitance, CD   Transition Capacitance, CT 

A
(a) Transition capacitance, CT  where, 0r
W
CT0
CT'  n
, where, CT0 is the capacitance when VD  0 V.
 VD 
1  
 V0 
1 1 1
i.e., CT   1 
W V 2 V  V  12
j 0 D

(i) For step Graded n  0.5 (ii) For Linearly Graded n  0.33
I
(b) Diffusion capacitance, CD 
VT
where I  Forward current of diode.
  n   p (under Non- equilibrium)
 Key Point
CD  I  VD
 
(Forward (Forward
current) voltage)

9. Effect of temperature on VI Characteristics of Diode


0
For every 10 rise in temperature, the reverse saturation current will be doubled.
 T2 T1 
 10 
 I 02  I 01  2
 

 Reverse saturation current, I 0

VG 0

I 0  kT em  kT
m  1.5 for Si , m  2 for Ge .

22 Electronic Devices & Circuits

 d [ln I0 ] m VG0
 
dT T T VT
 Key Point
d [ln I0 ] 8%
(1) For Si at 300 K ,  0 .
dT C
d [ln I0 ] 11%
(2) For Ge at 300 K ,  0 .
dT C
dV mV
 Effect of temperature on terminal voltage of diode,  2.5 0
dT C

Q.1 Drift current in semiconductor depends temperature T,

assume complete
upon kT
impurity ionization,  25 mV and
(A) Only the electric field q
(B) Only the carrier concentration intrinsic carrier concentration to be
gradient ni  11010 cm 3 .
(C) Both the electric field and carrier
What is the magnitude of the built-in
concentration
potential of this device?
(D) Both the electric field and the
[GATE 2017 Set-01, IIT Roorkee]
carrier concentration gradient
(A) 0.748 V (B) 0.460 V
Q.2 In a p-n junction diode at equilibrium,
which one of the following statements (C) 0.288 V (D) 0.173 V
is NOT TRUE? Q.5 A junction is made between p Si with


[GATE 2018, IIT Guwahati] 3

doping density N A1  10 cm and p Si
15

(A) The hole and electron diffusion 3

with doping density N A2  10 cm .
17
current components are in the same
direction. Given : Boltzmann constant
(B) The hole and electron drift current k  1.38 10 23 1
J-K , electronic charge
components are in the same 19
direction. q  1.6 10 C . Assume 100% acceptor
(C) On an average, holes and electrons ionization. At room temperature
drift in opposite direction. (T  300 K) , the magnitude of the built-
(D) On an average, electrons drift and in potential (in volts, correct to two
diffuse in the same direction. decimal places) across this junction
Q.3 For a pn diode, the change in contact will be ____________.
potential if doping on n side is [GATE 2018, IIT Guwahati]
increased by a factor of 1000 and Q.6 The figure below shows the doping
doping on p side is unaffected. distribution in a p-type semiconductor
(A) 1 V (B) 0.18 V in log scale.
(C) 0.86 V (D) 1.3 V
Q.4 An n -n Silicon device is fabricated with
+

uniform and non-degenerate donor

doping concentrations of
3
N D1  1  10 cm
18
and N D2  1  10 cm 3
15


corresponding to the n and n regions
respectively. At the operational

Electronic Devices & Circuits 23

 The magnitude of the electric field (in field in the depletion region,
kV/cm) in the semiconductor due to respectively, are
non-uniform doping is _________. [GATE 2014 Set-02, IIT Kharagpur]
[GATE 2018 Set-01, IISc Bangalore] (A) 2.7 m and 2.3 10 V/cm
5

Q.7 An abrupt p-n junction (located at (B) 0.3 m and 4.15 105 V/cm
x  0 ) is uniformly doped on both p and
n sides. The width of the depletion (C) 0.3 m and 0.42 105 V/cm
region is W and the electric field (D) 2.1 m and 0.42 105 V/cm
variation in the x-direction is E ( x) .
Q.9 The donor and accepter impurities in an
Which of the following figures abrupt junction silicon diode are
represents the electric field profile
1 1016 cm 3 and 5 1818 cm3 , respectively.
near the p-n junction?
Assume that the intrinsic carrier
[GATE 2017 Set-02, IIT Roorkee]
concentration in silicon
(A)
kT
ni  1.5 1010 cm  3 at 300K,  26 mV
q
and the permittivity of silicon
12
si  1.04 10 F/cm . The built-in
potential and the depletion width of
the diode under thermal equilibrium
(B) conditions, respectively, are
[GATE 2014 Set-03, IIT Kharagpur]
4
(A) 0.7 V and 110 cm
4
(B) 0.86 V and 110 cm
5
(C) 0.7 and 3.3  10 cm
5
(D) 0.86 V and 3.3  10 cm
(C)
Q.10 The electric field profile in the
depletion region of a p-n junction in
equilibrium is shown in the figure.
Which one of the following statements
is NOT TRUE?
[GATE 2015 Set-03, IIT Kanpur]
(D)

Q.8 When a silicon diode having a doping

3
concentration of N A  9 10 cm on p-
16
(A) The left side of the junction is n-
side and N D  11016 cm 3 on n-side is type and the right side is p- type
reverse biased, the total depletion (B) Both the n- type and p- type
width is found to be 3 m . Given that depletion regions are uniformly
the permittivity of silicon is doped
12
1.40 10 F/cm, the depletion width on (C) The potential difference across the
the p-side and the maximum electric depletion region is 700 mV

24 Electronic Devices & Circuits

 (D) If the p- type region has a doping applied to the diode. Given : kT/q = 26
15
concentration of 10 cm , then the
3 mV, ni = 1.5 × 1010 cm−3 ,  Si  120 ,
doping concentration in the n- type 0  8.85 1014 F/m and q = 1.6 × 10−19 C.
16 3
region will be 10 cm . The charge per unit junction area (nC
Q.11 A p-n step junction diode with a cm−2) in the depletion region on the p-
contact potential of 0.65 V has a side is ___________.
depletion width of 1 μm at equilibrium.
Q.15 In a forward biased pn junction diode,
The forward voltage (in volts, correct to the sequence of events that best
two decimal places) at which this width describes the mechanism of current
reduces to 0.6 μm is ______. flow is
Q.12 Consider a region of silicon devoid of [GATE 2013, IIT Bombay]
electrons and holes, an ionized donor (A) injection, and subsequent diffusion
density of N D  1017 cm 3 . The electric and recombination of minority
carriers
field at x  0 is 0 V/cm and the electric (B) injection, and subsequent drift and
field at x  L is 50 kV/cm in the positive generation of minority carriers
x direction. Assume that the electric (C) extraction, and subsequent
field is zero in the y and z directions diffusion and generation of minority
at all points. carriers
(D) extraction, and subsequent drift
and recombination of minority
carriers

Common Data for

Questions 16 and 17
Given q  1.6 1019 coulomb,
0  8.85 1014 F/cm ,  r  11.7 for For a Germanium pn diode given
silicon. The value of L in nm is
N D  1016 3
cm and N A  3 10 cm3 .
18

____________. Q.16 Fermi level position in p, n regions with

[GATE 2016 Set-02, IISc Bangalore] respect to intrinsic fermi level.
Q.13 Consider an abrupt PN junction (at T = (A) 1.303 eV, 1.155 eV
300 K) shown in the figure. The (B) 0.303 eV, 0.155 eV
depletion region width X n on the N-side (C) 1.603 eV, 1.255 eV
(D) 2.303 eV, 2.155 eV
of the junction is 0.2 m and the Q.17 The position of E0 , shift in energy level
permittivity of silicon ( si ) is using (a).
1.044 10 12
F/cm . At the junction, the (A) 1.458 eV (B) 0.458 eV
approximate value of the peak electric (C) 1.488 eV (D) 2.458 eV
field (in kV/cm) is __________. Q.18 Consider the following statements :
[GATE 2014 Set-02, IIT Kharagpur] E nf and are E fp the energies of the Fermi
levels on the n and p sides of p-n
junction diode, respectively. They will
vary with applied bias as follows :
1. E nf  E fp with no bias applied
Q.14 Consider a silicon p-n junction with a n p
2. E f increase and E f decreases with
uniform acceptor doping concentration forward bias.
of 1017 cm−3 on the p-side and a uniform n p
3. E f decrease and E f increases with
donor doping concentration of 1016 cm−3
on the n-side. No external voltage is reverse bias

Electronic Devices & Circuits 25

 4. E nf decrease and E fp increases with Q.20 Given  p  1 ( cm) 1 , n  0.1 ( cm) 1 ,
forward bias Ln  Lp  0.15 cm the ratio of hole
5. E nf increases and E p
f
decreases diffusion current to electron diffusion
with reverse bias. current crossing a junction in pn diode
Select the correct answer using the is
codes given below (A) 10 (B) 20
(A) 1, 4 and 5 (B) 2 and 3 (C) 100 (D) 0.1
(C) 4 and 5 (D) 1, 2 and 3 Q.21 The voltage across silicon diode if 90%
Q.19 An N-type semiconductor having of reverse saturation current is flowing
uniform doping is biased as shown in
in forward bias ( Given :   2 )
the figure.
(A) 3.38 mV (B) 0.38 mV
(C) 33.38 mV (D) 40 mV
Q.22 The voltage at which reverse saturation
current in Germanium diode will reach
If EC is the lowest energy level of the 90% of its saturation value is
(A) 0.059 V (B) – 0.059 V
conduction band, EV is the higher
(C) 0.018 V (D) – 0.018 V
energy level of the valance band and
Q.23 Assuming I 0 for Germanium diode
E F is the Fermi level, which one of the 13
following represents the energy band given in circuit as 10 A the magnitude
diagram for the biased N-type of VD (in volt) is
semiconductor? 2 k
(A)
ID
5V
VD

(A) 0.5 (B) 5

(C) 0.619 (D) 1
(B)
Q.24 A germanium diode D1 was carrying a
forward current of 1.2 mA when a
voltage VD1 is applied across it (Assume
I 0  4 1015 A ). It was replaced by a
(C) silicon diode D2 which needed a
voltage of 0.265 V more than VD1 to
carry same current as D1 the reverse
saturation current I 02 of D2 is (Given :
for Si   2 and for Ge   1 )
Si
(D) D1
Ge
D2

Circuit

26 Electronic Devices & Circuits

 (A) 13.4 pA (B) 13.8 pA Q.30 A Germanium diode has I 0  30 A at
(C) 13 pA (D) 13.4 nA
1250 C the dynamic resistance under
Q.25 Reverse saturation current density of a
Forward bias 0.2 V and Reverse bias 0.2
Germanium diode is 1 mA/ m 2 . The
V are respectively is
voltage required to be applied across it
in forward bias to get a current density (A) 0.36  , 388.92 k
of 105 mA/ m 2 is (B) 3.36  , 388.92 k
(A) 0.0993 V (B) 0.2993 V (C) 1.36  , 488.92 k
(C) 1.2993 V (D) 2 V (D) 0.36  , 388.92 M
Q.26 At 300 K, for a diode current of 1 mA, a Q.31 Consider an abrupt p-n junction. Let
certain germanium diode requires a Vbi be the built-in potential of this
forward bias of 0.1435 V, whereas a
certain silicon diode requires a forward junction and VR be the applied reverse
bias of 0.718 V. Under the conditions bias. If the junction capacitance ( C j ) is
stated above, the closest
approximation of the ratio of reverse 1 pF for Vbi  VR  1V, then for
saturation current in germanium diode Vbi  VR  4 V, C j will be
to that in silicon diode is
(A) 1 (B) 5 (A) 4 pF (B) 2 pF
(C) 0.25 pF (D) 0.5 pF
(C) 4  10 3
(D) 8  103
Q.27 For a silicon diode with long P and N Q.32 A Silicon diode has a diffusion
regions, the accepter and donor capacitance of 1 F when carrying a
impurity concentrations are 11017 cm3 current of 1 mA assuming N A  N D .
3
and 110 cm , respectively. The
15
The diffusion length ( L p ) at room
lifetimes of electrons in P region and
temperature given D p  13 cm 2 /sec .
holes in N region are both 100 s . The
electron and hole diffusion coefficient (A) 0.026 cm (B) 2.26 cm
are 49cm2 /s and 36cm2 /s , respectively. (C) 2.14 cm (D) 2.86 cm
Assume kT / q  26 mV , the intrinsic Q.33 Consider a step graded silicon pn diode
at T  3000 C with V0  0.637 V given
carrier concentration is 11010 cm3 , and
transition capacitance at zero bias is
q  1.6 1019 C . When a forward voltage
0.5 pF. The transition capacitance at a
of 208 mV is applied across the diode, reverse bias of 5 V is
2
the hole current density (in nA/cm ) (A) 0.168 pF (B) 1.168 pF
injected from P region to N region is
(C) 2.168 pF (D) 0.168 F
_______.
Q.28 A silicon diode operates at a fixed Q.34 As shown, two Silicon (Si) abrupt p-n
forward bias of 0.4 V the factor by junction diodes are fabricated with
which current will get multiplied when uniform donor doping concentrations
0
its temperature is raised from 25 C to of N D1 = 1014 cm–3 and N D2 = 1016 cm–3 in

1500 C is the n-regions of the diodes, and

uniform Accepter doping
(Given :   2)
concentrations of N A1  10 cm–3 and
14
(A) 580 times (B) 680 times
(C) 690 times (D) 700 times N A2  1016 cm–3 in the p-regions of the
Q.29 For a silicon diode at t  270 C , diodes, respectively. Assuming that the
reverse bias voltage is much greater
Vd  0.6 V its value at 87 0 C assuming
than built-in potentials of the diodes,
current through diode as constant is C2
(Given :   2) the ratio of their reverse bias
C1
(A) 0.05 V (B) 0.35 V
capacitances for the same applied
(C) 0.45 V (D) 1 V reverse bias, is _____.
Electronic Devices & Circuits 27
 Q.35 When a diode is reverse bias with 8 V it
has a junction capacitance of 15 pF
when the reverse bias is increased to 12
V the capacitance drop to 13.05 pF
whether it is abrupt or graded junction?

Q.1 In an abrupt p-n junction, calculate the

junction capacitance for a junction
voltage of 4 V, if the junction
capacitance for a junction voltage of 1
V is 1 pF.
(A) 4 pF (B) 2 pF
(C) 0.25 pF (D) 0.5 pF (A) Capacitance increases and
Q.2 Assertion (A) : The diffusion resistance decreases.
capacitance increases with the (B) Capacitance decreases and
increase in the forward bias. resistance increases.
Reason (R) : The diffusion capacitance (C) Capacitance decreases and
is much higher than the depletion resistance increases.
capacitance when the junction is under
(D) None of these.
forward bias.
Q.6 The transition capacitance of a diffused
(A) Both A and R are individually true
junction varicap diode at a reverse
and R is the correct explanation of
potential of 4.2 V, if the capacitance at
A.
zero bias is 80 pF and the cut in voltage
(B) Both A and R are individually true
is 0.7 V.
but R is not a correct explanation
of A. (A) 10 pF (B) 20 pF
(C) A is true and R is false. (C) 30 pF (D) 40 pF
(D) R is true but A is false. Q.7 The reverse bias saturation current for
a p - n junction diode is 1μA at 300 K.
Common Data for Its ac resistance at 150mV forward bias
Questions 3 and 4 is
(A) 51.4  (B) 61.4 
An ideal Ge p-n junction diode has a reverse
saturation current of 30 μA at a temperature (C) 71.4  (D) 81.4 
of 125 C .
Common Data for
Q.3 At this temperature the dynamic Questions 8 and 9
resistance of the diode at a forward
voltage of 0.2 V is
Consider a silicon junction with N A  N D . The
(A) 50  (B) 5.37 
resistivity of p side is 3.5 -cm. and internal
(C) 30  (D) 3.36 
contact potential is 0.35 V (  p  500 cm /Vsec,
2
Q.4 At this temperature, the dynamic
resistance of the diode at a reverse si  1.04 1014 F/cm ).
voltage of 0.2V is
Q.8 A reverse bias of 5 V is applied to the
(A) 0.50 M  (B) 5.37 M 
junction. The depletion width for this
(C) 0.70 M  (D) 0.389 M  junction is
Q.5 For the circuit shown, if we increase
(A) 1.4 μm (B) 2.4 μm
the value of Va
(C) 3.4 μm (D) 4.4 μm

28 Electronic Devices & Circuits

Q.9 If the junction has the circular cross- 1 1 1 1 1 1
(A) , , (B) , ,
section with diameter of 1000 μm . The 2 3 2.5 3 2 2.5
junction capacitance is 1 1 1 1 1 1
(A) 40 pF (B) 50 pF (C) , , (D) , ,
2 2.5 3 3 2.5 2
(C) 60 pF (D) 70 pF
Q.16 A uniformly doped silicon p-n junction
Q.10 The change in barrier potential of a Si
has N a  5 1017 / cm3 and Nd  1017 / cm3
p-n junction diode with temperature is
(A) 2.5 mV (B) 0.25 mV . The junction has a cross-sectional
(C) 0.30 mV (D) None of these. area of 104 cm2 and has an applied
Q.11 Silicon diodes are preferred to Ge diode reverse bias voltage of VR  5 V . The
for high temperature operation
total junction capacitance is
because
(A) 10 pF (B) 5 pF
(A) Doping of silicon is a simple process
(B) Rate of increase of reverse (C) 7 pF (D) 3.5 pF
saturation current with temperature Q.17 For a particular junction for which
is more in the case of Si C j0  0.6 pF , V0  0.75V , and m  1/ 3 ,
(C) The reverse saturation current of the capacitance at reverse-bias voltage
silicon diodes is smaller than that of of 1 V is.
germanium (A) 0.25 pF (B) 0.35 pF
(D) Silicon diodes can be used to rectify (C) 0.45 pF (D) 0.55 pF
even very small voltages.
Q.18 In a p-n junction, to make the depletion
Q.12 Given that C D at forward current of 1 region extend predominantly into p-
mA is 0.8 F , its value for a current of region the concentration of impurities
4 mA is in the p-region must be
(A) 0.8 F (B) 0.2 F (A) Much less than the concentration of
impurities in n-region
(C) 1.6 F (D) 3.2 F
(B) Much higher than the concentration
Q.13 The ratio of hole to electron current of impurities in n-region
crossing a p-n junction is given by (C) Equal to concentration of impurities
I pn (0) in n-region

I np (0) (D) Equal to zero
p  p Lp Q.19 A series silicon p-n junction with
(A) (B)  doping profile of N A  1016 /cm3 and
n  n Ln
 p Ln L N D  1015 /cm3 has a cross sectional area
(C)  (D) n 2
 n Lp of 10 cm . The length of the p-region
2
Lp
is 2 mm and length of the n-region is 1
Q.14 The leakage current in a certain diode
mm. The approximate series resistance
is 25 A at 25 C . The change in
0
of the diode is
temperature required to have leakage (A) 62  (B) 43 
current of 40 μA ?
(C) 72  (D) 81 
(A) 31.77 0 C (B) 6.77 0 C
Q.20 A silicon abrupt junction has dopant
0
(C) 13.77 C 0
(D) 27.77 C concentration N a  2 1016 /cm3 and
Q.15 In a p-n junction, the space charge
N d  2 1015 /cm3 . The applied reverse
capacitance is proportional to V  n .
Where V is the applied bias voltage and bias voltage is VR  8V . The space
'n' is a constant. The value of 'n' for charge region is
step, linearly graded and diffusion (A) 2.5 μm (B) 25 μm
junctions would be respectively.
(C) 50 μm (D) 100 μm

Electronic Devices & Circuits 29

Q.21 Consider a step graded Germanium p-n (D) Equal to the mean carrier life time
junction. It has N D  10
13
and NA  for the excess minority carriers
Q.25 In the circuit shown below, the switch
corresponds to 1 atom per 108 Ge was connected to position 1 at t < 0 and
atoms. The junction potential is at t = 0, it is changed to position 2.
(A) 0.328 V (B) 0.428 V Assume that the diode has zero voltage
(C) 0.528 V (D) None of these drop and a storage time t s . for 0  t  t s ,
Q.22 If reverse saturation current of diode
VR is given by (all in Volts)
D1 is 1010 A and D2  1012 Amp. The
magnitude of V from the figure is

(A) 0.23 V (B) 0.43 V

(A) VR  5 (B) VR  5
(C) 0.53 V (D) 4.3 V
Q.23 A p-n junction in series with a 100 ohm (C) 0  VR  5 (D) 5  VR  0
resistor, is forward biased so that a Q.26 Given power dissipated in the diode is
current of 100 mA flows. If the voltage to be no more than 1.05 mW. The I D (max)
across this combination is
instantaneously reversed to 10 V at and Rmin are respectively
t  0 , the reverse current that flows R
through the diode at t = 0 is ID
approximately given by
10 V
(A) 0 mA (B) 100 mA 0.7 V
(C) 200 mA (D) 50 mA
Q.24 When a junction diode is used in
(A) 1.5 mA, 6.2 k (B) 2.5 mA, 6.2 k
switching applications, the forward
recovery time is (C) 1.5 mA, 5 k (D) 1.5 mA, 5.2 k
(A) Of the order of the reverse recovery Q.27 For a pn diode surface leakage current
time is 2 nA for a reverse voltage of 25 V. The
surface leakage current for a reverse
(B) Negligible in comparison to the
voltage of 35 V is
reverse recovery time
(A) 0.8 nA (B) 1.8 nA
(C) Greater than the reverse recovery
(C) 2.8 nA (D) 0.8 A
time

Assignment 1 current in the circuit is 2 mA, the

The ratio of the current for a forward voltage drop across each diode is.
bias of 0.06 V to the current for the (Assume   1)
same value of reverse bias applied to a (A) 0.136 V (B) 0.236 V
Ge pn diode at 27 C is
0
(C) 0.336 V (D) 0.436 V
(A) 10.15 (B) – 10.15 Assignment 3
(C) 20.15 (D) – 20.15 The anticipated factor by which the
Assignment 2 reverse saturation current of a
A diode with a reverse saturation germanium diode is multiplied when
12 the temperature is increased from 25
current of 10 A is connected in 0
parallel to another diode having reverse to 80 C is
10 (A) 25.25 (B) 35.25
saturation current of 10 A. If the total
(C) 45.25 (D) 55.25
30 Electronic Devices & Circuits
Assignment 4 decrease in capacitance for a 1 V
A silicon diode operates at a forward increase in bias is
voltage of 0.4 V. The factor by which (A) 1.75 pF (B) 2.75 pF
the current will be multiplied when the (C) 3.75 pF (D) 4.75 pF
temperature is increased from 25 to
Assignment 7
1500 C
Consider a step graded silicon pn diode
(A) 577 (B) 677
with V0  0.637 V , zero bias capacitance
(C) 777 (D) 877
Assignment 5 0.5 pF . CT for reverse bias of 5 V is
In an abrupt pn junction the doping (A) 0.68 pF (B) 0.168 pF
concentration on the p side and n side
(C) 0.268 pF (D) 0.368 pF
are N A  9 1016 atoms/cm3 and
Assignment 8
N D  1016 atoms/cm3 . The pn junction is Given a forward-biased silicon diode
reverse biased and the total depletion with I = 1 mA. If the diffusion
width is 3μm . The depletion width on capacitance is CD  1μF , the diffusion
p side is
length L p is? (Assume that doping of
(A) 0.1μm (B) 0.2 μm
the p side is much greater than that of
(C) 0.3μm (D) 0.4 μm the n side.)
Assignment 6
(A) 0.016 cm (B) 0.026 cm
The transition capacitance of an abrupt
junction diode is 20 pF at 5 V. The (C) 0.036 cm (D) 0.046 cm

Classroom Questions
1. C 2. D 3. B 4. D 5. 0.119
6. 1.137 7. A 8. B 9. D 10. C
11. 0.416 12. 3236 13. 30.65 14. 4.89 15. A
16. B 17. B 18. D 19. D 20. A
21. C 22. B 23. C 24. A 25. B
26. C 27. 2860 28. A 29. C 30. B
Graded
31. D 32. A 33. A 34. 10 35.
junction
Practice Questions
1. D 2. A 3. D 4. D 5. A
6. C 7. D 8. A 9. C 10. A
11. C 12. D 13. C 14. A 15. A
16. D 17. C 18. A 19. C 20. A
21. D 22. B 23. B 24. B 25. A
26. A 27. C
Assignment Questions
1. B 2. D 3. C 4. A 5. C
6. A 7. B 8. B

Note : For detailed solutions, scan the QR code Given below,

Electronic Devices & Circuits 31

 3 Basics of BJT
Introduction :
 The Bipolar junction transistor was the first solid-sate active electronic device. Before BJT
the electronic amplifier was based on vacuum tubes. The BJT concept was experimentally
and theoretically established in 1948 at Bell laboratory.
 The device is called "bipolar" since its operation involves both types of mobile carriers,
electrons and holes.
 The BJT consists of two back-to-back p-n junctions, one is emitter junction ( J E ) in between
emitter and base region and another one is collector junction ( J C ) which is in between
collector and base region.
Emitter Junction Collector Junction Region of
Application
(J E ) (JC ) operation
FB FB Saturation ON Switch
FB RB Active Amplifier
RB FB Inverse Active Attenuator
RB RB Cut-off OFF Switch


Fig. Profile of minority carrier concentration in the Base, Emitter and

Collector of an n-p-n transistor operating in the active mode
 Current I n is directly proportional to the slope of the straight line concentration profile,
dn p ( x)
I n  AE qDn
dx
The collector current in active biasing, I C  I S e BE T
V /V

where, I S is the reverse saturation current, which is given by,

n p0
I S  AE qDn
W
1. Equilibrium Condition
Conditions :
(a) J E  VEB  0 (Externally) [Emitter junction biasing]

(b) J C  VBC  0 (Externally) [Collector junction biasing]

32 Electronic Devices & Circuits

2. Energy Band Diagram of PNP Transistor at Equilibrium Condition
p++ n p+
EC

Ei
EF
EV

3. Active Mode :  J E  FB, J C  RB 

ICO

(F.B.) (R.B.)

where, I pE  Current due to diffusion of holes from p to n

I nE  Current due to diffusion of electrons from n to p.
Results :
(a) I C  I pC  I CO
(b) IC   I E  I CO (Common base Equation).
I pE
(c) Emitter injection Efficiency/ Emitter Insertion factor, * 
I pE  I nE
I pC
(d) Base Transport Factor, *  T 
I pE
(e) I E  I pE  I nE
(f) I E  I B  IC
I pC
(g)  * *     Amplification Factor
I pE  I nE
Known as Amplification factor of Current Gain (CB) configuration
(h) IC  I E  ICBO , 𝐼𝑐 = 𝐼𝑆 𝑒 𝑉𝐵𝐸 ⁄𝑉𝑇
where, I CBO is current between Collector & Base when emitter is Open Circuited.

 VCE 
(i) I C  I E  I CO  e VT  1
 
 
 IC 
V
I  VBET
(j) Base current in BJT can be given by, I B   S e  IB   
   

Electronic Devices & Circuits 33

 VBE
I  VT  IC 
(k) Emitter current in BJT is given by, I E   S e  IE   
   
4. Ebers Moll Model
I IC N I E

E C
 
IE I0
VEB   VCB
B
where,  I  Inverted mode  and  N  Normal mode  .
 Two diodes are connected in back to back configuration, we cannot construct a
transistor until, a dependent current source is connected in parallel with the diodes.
 The given Model can work in all 3 conditions i.e. (Active, cut-off and saturation)

5. CB, CE, CC Configuration

(A) CB Configuration :
IC
 
IE
 IC  I E  ICBO
(Where I CBO is the reverse saturation current in CB configuration when emitter
terminal is open circuited).
 CB amplifier circuit is used, where the low input impedance is required, like RF
amplifier.
(B) CE Configuration :
 
  and    IC  I B  (  1) ICBO
1  1 
 IC  I B  ICEO  ICEO  (  1) ICBO
 CE configuration, commonly used in low noise amplifier.
(C) CC Configuration :
1
    1 
1 
 Application in “Super- Heterodyne Receiver”.
 Practically, the below configuration is not possible.
 Better “Current Amplifier”
ICBO
 I E  I B 
1 
 CC is basically used for “Voltage Follower”.
6. Early Effect /Base-Width Modulation
Consequences of Early- Effect.
(i) I E , I B , IC  (ii)  
(iii) Punch through / Reach Through occurs

34 Electronic Devices & Circuits

 Explanation :
Due to large R.B of J BC , the effective base-width may be reduced to zero. This is known as
“Punch Through” occurs.
At “Reach through” condition, the usefulness of the transistor is lost.
Then, the depletion region, resistance increases. Hence more F.B. of the junction J EB is
required.
7. Early Voltage (VA )
 In CE, early voltage, is the voltage [VCE ] at which the collector current will become zero.
i.e., at Early voltage, I C  0 Amp
 VVEB  V 
 Modified CE Output, current, I C  I s  e T  1 1  CE 
   VA 
 
When, VCE  VA , I C  0
IC I B4

I B3

I B2

I B1
VCE
VA 0

8. Reverse Saturation Current, I CBO & Breakdown Voltage

 After R.B. breakdown, large current, I C Flows
1
For CB: Multiplication factor ( M )  n
 V 
1   CB 
 BVCBO 
Where, n  Emperical number.
1/ n
1
For CE and CB configuration, BVCEO  BVCBO  


Q.1 Which of the following statements is Q.2 In a uniformly doped BJT, assume that
true with regards to the BJT ? N E , N B and N C are the emitter, base
(A) The base width must be designed to and collector doping in atoms/cm3,
be much larger than the minority respectively. If the emitter injection
carrier diffusion length. efficiency of the BJT is close to unity,
(B) The base width must be designed to which one of the following conditions
be much smaller than the minority is TRUE?
carrier diffusion length. [GATE 2010, IIT Guwahati]
(C) The base region should be heavily (A) N E  N B  NC
doped. (B) N E  N B and N B  NC
(D) Base region should be doped more
(C) N E  N B and N B  NC
than emitter.
(D) N E  N B  NC

Electronic Devices & Circuits 35

Q.3 For a narrow base p-n-p BJT, the Which one of the following is correct?
excess minority carrier concentrations [GATE 2004, IIT Delhi]
( nE for emitter, pB for base, nC (A) S1 is FALSE and S2 is TRUE.
for collector) normalized to equilibrium (B) Both S1 and S2 are TRUE.
(C) Both S1 and S2 are FALSE.
minority carrier concentrations ( nE0 for
(D) S1 is TRUE and S2 is FALSE.
emitter, pB0 for base, nC0 for collector) Q.7 The neutral base width of a bipolar
in the quasi-neutral emitter, base and transistor, biased in the active region, is
collector regions are shown below. 0.5 m . The maximum electron
Which one of the following biasing concentration and the diffusion
modes is the transistor operating in? constant in the base are 10 /cm and
14 3

[GATE 2017, IIT Roorkee]

Dn  25 cm 2 /sec respectively.
Assuming negligible recombination in
the base, the collector current density
19
is (the electron charge is 1.6 10
Coulomb)
[GATE 2004, IIT Delhi]
(A) 800 A/cm2 (B) 8 A/cm2

(A) Forward active (B) Saturation (C) 200 A/cm2 (D) 2 A/cm2
(C) Inverse active (D) Cutoff Q.8 For an n-p-n transistor connected as
Q.4 The parameters for the base region in shown in figure, VBE  0.7 volts. Given
an npn BJT are given by Dn  20 cm /s,
2
that reverse saturation current of the
3 4
nB 0  10 cm , ABE  10 cm . The base
4 2 junction at room temperature 3000 K is
width is 1 micron. When the base- 1013 A, the emitter current is
emitter voltage is 0.7 V and the [GATE 2005, IIT Bombay]
collector-base junction is reverse
biased. The collector current ( I C ) is
(Assume thermal voltage is 26 mV).
(A) 7.5 A (B) 0.33 mA
(C) 17 mA (D) 82 A
Q.5 In a bipolar transistor at room
temperature, if the emitter current is
doubled, the voltage across its base- (A) 30 mA (B) 39 mA
emitter junction (C) 49 mA (D) 20 mA
[GATE 1997, IIT Madras]
Q.9 The DC current gain (  ) of a BJT is 50.
(A) doubles
(B) halves Assuming that the emitter injection
(C) increases by about 20 mV efficiency is 0.995, the base transport
(D) decreases by about 20 mV factor is [GATE 2007, IIT Madras]
Q.6 Consider the following statements S1 (A) 0.980 (B) 0.990
and S2. (C) 0.985 (D) 0.995
S1 : The  of a bipolar transistor Q.10 For a BJT, the common-base current
reduces if the base-width is gain  = 0.98 and the collector base
increased. junction reverse bias saturation current
S2 : The  of a bipolar transistor ICO  0.6 A This BJT is connected in
increases if the doping the common emitter mode and
concentration in the base is operated in the active region with a
increased. base drive current I B  20 A The

36 Electronic Devices & Circuits

 collector current I C for this mode of (C) the effective base width decreases
operation is [GATE 2011, IIT Madras] and common-emitter current gain
increases.
(A) 0.98 mA (B) 0.99 mA
(D) the effective base width decreases
(C) 1.0 mA (D) 1.01 mA and common-emitter current gain
Q.11 Consider two BJTs biased at the same decreases.
collector current with area Q.15 Match the following :
A1  0.2 m  0.2 m and [GATE 1994, IIT Kharagpur]
List-I
A2  300 m  300 m
A. The current gain of a BJT will be
Assuming that all other device increased.
parameters are identical, kT /q  26 mV , B. The current gain of a BJT will be
the intrinsic carrier concentration is reduced.
1 1010 cm -3 and q  1.6 1019 C , the C. The break-down voltage of a BJT
will be reduced.
difference between the base-emitter
List-II
voltages (in mV ) of the two BJTs (i.e.
1. The collector doping concentration
VBE1  VBE2 ) is________.
is increased.
[GATE 2014, IIT Kharagpur] 2. The base width is reduced.
Q.12 In a transistor having finite  , forward 3. The emitter doping concentration to
bias across the base emitter junction is base doping concentration ratio is
kept constant and the reverse bias reduced.
across the collector base junction is 4. The base doping concentration is
increased. Neglecting the leakage increased keeping the ratio of the
current across the collector base emitter doping concentration to
junction and the depletion region base doping concentration
generation current, the base current constant.
will (increase / decrease / remains 5. The collector doping concentration
constant). is reduced.
[GATE 1992, IIT Delhi] Q.16 The breakdown voltage of a transistor
with its base open is BVCEO and that
Q.13 Early voltage represents the voltage at
which with emitter open is BVCBO , then
(A) Break-down occurs at the junctions [GATE 1995, IIT Kanpur]
(B) Saturation of collector current (A) BVCEO  BVCBO
begins (B) BVCEO  BVCBO
(C) Curves on collector-current
(C) BVCEO  BVCBO
characteristics intersect the voltage
axis, when extrapolated to zero (D) BVCEO is not related to BVCBO
collector current value. Q.17 For a BJT   100 collector junction
(D) None of the above breakdown voltage CB emitter open is
Q.14 An n-p-n bipolar junction transistor 120 V assuming empirical constant is 3.
(BJT) is operating in the active region. Calculate collector junction breakdown
If the reverse bias across the base voltage in common emitter base open
collector junction is increased, then circuited
(A) the effective base width increases (A) 13 V (B) 20 V
and common-emitter current gain (C) 23 V (D) 26 V
increases. Q.18 The Ebers-Moll model of a BJT is valid
(B) the effective base width increases [GATE 2016, IISc Bangalore]
and common-emitter current gain (A) only in active mode.
decreases. (B) only in active and saturation mode.
Electronic Devices & Circuits 37
 (C) only in active and cutoff mode. manufacturing variations. The
(D) in active, saturation and cutoff maximum emitter current (in μA ) is
mode. ______.
Q.19 In the circuit shown, I1  80 mA and [GATE 2015, IIT Kanpur]
I 2  4 mA . Transistors T1 and T2 are Q.21 The injected excess electron
identical. Assume that the thermal concentration profile in the base region
of an n-p-n BJT, biased in the active
voltage VT is 26 mV at 27 C . At 50 0 C ,
0
region, is linear, as shown in the figure.
the value of voltage V12  V1  V2 (in mV) If the area of the emitter-base junction
is _____. is 0.001 cm2,  n = 800 cm2/(V-s) in the
[GATE 2015, IIT Kanpur] base region and depletion layer widths
are negligible, then the collector
current I C (in mA) at room temperature
is _____.
(Given : thermal voltage VT  26 mV at
room temperature, electronic charge
q  1.6 1019 C )
[GATE 2016, IISc Bangalore]

Q.20 An n-p-n BJT having reverse saturation

current I S  1015 A is biased in the
forward active region with
VBE  700 mV. The thermal voltage (VT )
is 25 mV and the current gain () may
vary from 50 to 150 due to

nE 0 pE 0 nC 0
Common Data for
Questions 1 to 3 (A) 2.25 102 2.25  105 4.5 103
(B) 2.25 102 4.5 103 2.25  105
A uniform doped silicon pnp transistor is
(C) 4.5 103 2.25 102 2.25  105
biased in the forward-active mode Its
geometry has been shown in the figure below. (D) 4.5 103 2.25  105 2.25 102
The doping concentrations are Q.2 For VEB  0.650 V , total minority carrier
3 3 3
N E  10 cm , N B  5 10 cm and NC  10 cm .
18 16 15
hole concentration, pB at x  0 will be
(A) 4.68 103 cm 3 (B) 7.93 1013 cm 3
(C) 5.54 104 cm 3 (D) 3.57 1014 cm 3
Q.3 For VEB  0.650V , total minority carrier
(electron) concentration, nE at x '  0
will be
(A) 1.78  1013 cm 3 (B) 7.91 1012 cm 3
Q.1 The thermal equilibrium minority
(C) 2.34 102 cm 3 (D) 4.31102 cm 3
carrier concentrations, nE 0 , pE 0 and nC 0
Q.4 Consider the transistor shown in figure
(in cm-3) is
below.
38 Electronic Devices & Circuits
 Q.8 Consider the transistor whose IC-VCE
Curves are shown in figure.

The mode of operation of the transistor

is
(A) reverse active mode
(B) cut of mode
(C) forward active mode The value of early voltage (in V) is
(D) saturation mode (A) 11 (B) 0.5
Q.5 The parameters in the base region of an (C) 100 (D) – 20
npn bipolar transistor are Dn  20cm2 / s
Q.9 The collector current of bipolar is
nBO  104 cm3 , xB  1 m, and
iC  2mA if the output resistance is
ABE  104 cm2 . The collector current (in greater than 10kΩ. The value of early
 A ) for VBE = 0.5 V is _____ mA. voltage VA for the transistor is
Q.6 A uniformly doped silicon pnp bipolar (A) VA  20V (B) VA  10V
transistor at T=300 K with doping of
(C) VA  10V (D) VA  20V
N E  5 1017 cm 3 , N B  1016 cm3 and
Q.10 Consider two BJTS biased at the same
NC  5 1014 cm 3 is biased in the
collector current with area
inverse-active mode. The maximum B-
A1  0.2 μm  0.2μm and
C voltage (in-volt) so that the low-
injection condition applied is ______. A2  300 μm  300 μm
Q.7 The collector current of a n-p-n Assuming that all other device
transistor operating at 300K is 2 mA. prameters are identical, kT/q = 2 6 mV,
Other device parameters are given as   1 the intrinsic carrier concentration
  1, ni  1.5 1010 cm3 , VT  26mV . If the 3
is 1 10 cm and q  1.6 1019 C , the
10

base emitter voltage is increased by difference between the base-emitter

0.052 V then the value of new collector voltages (in mV) of the two BJTS (i.e.
3
current will be …………. 10 A (up to 2 VBE1  VBE2 ) is _______.
decimal places).

Q.1 A uniformly doped silicon pnp bipolar

Common Data for
transistor at T = 300K with dopings of
Questions 2 & 3
N E  5 1017 cm3 , N B  1016 cm3 and
NC  5 1014 cm 3 is biased in the inverse-
A Si pnp BJT with N AE  5 1017 / cm3 ,
active mode. The maximum B-C voltage
(in volt) so that the low-injection N DB  1015 / cm3 , N AC  1014 / cm3 and WB  3 m
condition applied is ______. is maintained under equilibrium conditions at
room temperature.

Electronic Devices & Circuits 39

Q.2 The net potential difference (in volt) The net potential difference between
between the collector and emitter is the collector and emitter is_____ V.
______. Q.5 A Si n-p-n transistor is biased in
Q.3 If built in potential of E-B junction is forward active mode at quiescent point
0.757 V, then the maximum magnitude Q (6V, 3mA) and has a total emitter
of the electric field in the E-B depletion base capacitance of 25 pF with base
transit time of 520 psec. Values of
region is_____ 104 V/cm .
diffusion and depletion capacitances
Q.4 Consider a Si pnp BJT with respectively are
N DE  10 / cm , N AB  10 / cm ,
18 3 16 3
(A) 15 pF, 10 pF (B) 5 pF, 20 pF
(C) 20 pF, 5 pF (D) 22pF, 3pF
N DC  1015 / cm3 .

Classroom Questions
1. B 2. B 3. C 4. C 5. C
6. D 7. B 8. C 9. C 10. D
A-2,B-
11. 380.28 12. Decreases 13. C 14. C 15.
3, C-1
16. C 17. D 18. D 19. 83.85 20. 1475
21. 6.656
Practice Questions
1. B 2. D 3. A 4. C 5. 7.75
6. 0.48 7. 14.77 8. A 9. D 10. 280.28
Assignment Questions
1. 0.48 2. – 1.179 3. 1.52 4. 0.221 5. C

Note : For detailed solutions, scan the QR code Given below,



40 Electronic Devices & Circuits

 4 MOSFET
Introduction :
 MOSFET is invented 1959 by Mohamed Atalla and Dawon Kahng at Bell labs and first
presented in 1960.
 In the construction of MOSFET , a lightly doped substrate, is diffused with a heavily doped
region. Depending upon the substrate used, they are called as P-type and N-type MOSFETs.
The voltage at gate controls the operation of the MOSFET.
 MOSFET is used for switching and amplifying electronics signals in the electronic devices.
It is used as an inverter. It can be used in digital circuit. MOSFET can be used as a high
frequency amplifier.

… ….
1. Operation of Enhancement MOSFET
Biasing :
(a) Gate  Biasing should be such that, it will enhance the channel between source & drain
For NMOS, VGS  ve
PMOS, VGS   ve
(b) Drain  Biasing should be such that, it will attract the majority charge carriers from
source to drain.
For NMOS, VDS  ve
PMOS, VDS   ve
(c) Source is always taken as “Reference” terminal
For NMOS  Lowest potential
PMOS  Highest potential
2. Current Characteristic
I D(mA)
Saturation Region

VDS  (VGS  Vt )
ohmic (linear region)

VDS  (VGS Vt )

VDS
VDS (sat) VGS Vt

Electronic Devices & Circuits 41

3. Capacitance Per Unit Area
ox
Cox'  fF/m 2
tox
ox A
where, Cox  F
tox
Cox 
 Cox'  ox fF/m 2
A tox
4. Drain Current
W  2
VDS 
(A) In Triode region, I D   nCox  
'
 GS
(V Vt )VDS 
L  2  NMOS
 nCox' W
(B) In saturation region, I D  (VGS  Vt ) 2 
2 L NMOS

5. Transconductance Parameter

(a)  nCox
'
 K n' (b)  P Cox
'
 K P'
' '
where, K n , K p is the process transconductance parameter

cm2 F F C 1
Unit of  P Cox
'
  2   
V sec cm V sec V .sec V
A
Unit is
V2
6. Drain Resistance, rd (valid in Triode Region)
1
rd 
W
Kn ' (VGS  Vt )
L
W Width of channel
where, aspect ratio  
L Length of channel

7. “Finite Output Resistance” in Saturation Region

Under channel length modulation,

Here after VDS , there is a finite output Resistance.

42 Electronic Devices & Circuits

8. Equation of I D under “Channel Length Modulation”
1 W
I D  nCox' VGS  Vt  1  VDS NMOS
2

2 L
'
where   [  is fixed at the time of fabrication process]
L
 '  Process technology parameter.
1
Here, I D  0, if VDS  

1
Unit of  is (Volt)

9. Drain Resistance Under Channel Length Modulation

1 V
Output resistance, r0   A
I D I D
I D
Drain conductance g d 
VDS
10. Results for PMOS
W  2
VSD 
In triode region, I D  K p  
'
(i)  SG
(V | Vt |) VSD 
L  2 
where, K p'   p Cox
| Vt | Vtp  Threshold voltage.
1 W
(ii) In saturation region, I D   p Cox' (VSG  | Vt |)2
2 L
(iii) In saturation region, considering “channel length modulation,
1W
ID   p Cox' (VSG  | Vt |)2 1   VSD 
2 L
11. Body Effect
For NMOS VB  VS  ,

Threshold voltage, Vt  Vto    2 f  VSB  2 f 

 
where,  is the fabrication process parameter,
2qN A si 2qN A si
  tox
Cox ox
where, N A  doping concentration of p-type substrate in NMOS
 f  Process technology parameter of MOSFET
 f  Fermi potential = Bulk potential and  f  0.6V (approx) for an NMOS.
 Key Point
1.    ve (NMOS)
2. VSB  ve (NMOS)

For PMOS VB  VS  : Vt  Vto    2 f  | VSB |  2 f 

 
 
 ve  ve

Electronic Devices & Circuits 43

 S. No. Parameter Depletion type Enhancement type
1. Symbols

2. Channel Exists permanently Channel is physically absent It is

induced after application of
positive gate voltage above the
threshold value for n-channel
enhancement type MOSFET and
negative gate voltage above
threshold value for p-channel
enhancement type MOSFET.
3. Operation Can be operated In Can only be operated in
depletion mode as well enhance mode.
as enhance mode.
4. Current flow Drain current flows on Practically no current flows on
application of drain to application of drain to source, at
source voltage, at VGS  0 . Current flows only when
VGS  0 VGS is above threshold level.

Output Transfer
Type Cross section
characteristics characteristics
n-channel
Enhancement
(Normally OFF)

n-channel
Depletion
(Normally ON)

p-channel
Enhancement
(Normally OFF)

p-channel
Depletion
(Normally ON)

12. Effect of Temperature on MOSFET

 mV 
Threshold voltage, Vt decreases by 2   and as Vt decreases so I D increases if
 0C 
temperature increase.
44 Electronic Devices & Circuits
 But, also  decreases with increase in temperature [   T  m ]
Practically, mobility is dominating. So, I D is constant with respect to temperature. Hence,
practically, I D decreases.
 Key Point
Channel length modulation occurs only in E- MOSFET. It does not exist in depletion
MOSFET.

Q.1 What is the main difference between Q.2 The source-body junction capacitance
MOSFET's and BJTs in terms of their I is approximately
– V characteristics? (A) 2 fF (B) 7 fF
(A) Current is quadratic with VGS for (C) 2 pF (D) 7 pF
MOSFET's and linear with VBE for Q.3 The gate-source overlap capacitance is
BJTs approximately
(B) Current pis linear with VGS for (A) 0.7 fF (B) 0.7 pF
(C) 0.35 fF (D) 0.24 pF
MOSFT's and exponential with VBE
Q.4 An n-channel silicon ( Eg  1.1 eV)
for BJTs

(C) Current is exponential with VGS / VBE MOSFET was fabricated using n poly-
silicon gate and the threshold voltage
in both these devices, but rise is
faster in MOSFETs was found to be 1 V . Now, if the gate

(D) Current is quadratic with VG for is changed to p poly-silicon, other
MOSFET's and exponential with VBE things remaining the same, the new
threshold voltage should be
for BJTs
[GATE 1996, IISc Bangalore]
Common Data for (A)  0.1 V (B) 0 V
Questions 2 & 3 (C) 1.0 V (D) 2.1 V
Q.5 When the gate-to-source voltage ( VGS )
In the three dimensional view of a silicon n-
channel MOS transistor shown below, of a MOSFET with threshold voltage of
  20 nm .The transistor is of width 1 m . The 400 mV, working in saturation is
900 mV, the drain current is observed
depletion width formed at every p-n junction
to be 1 mA. Neglecting the channel
is 10 nm. The relative permittivities of Si and
modulation effect and assuming that
SiO 2 , respectively, are 11.7 and 3.9, and
the MOSFET is operating at saturation,
0  8.9 1012 F/m . the drain current for an applied VGS of
[GATE 2012, IIT Delhi] 1400 mV is
[GATE 2003, IIT Madras]
(A) 0.5 mA (B) 2.0 mA
(C) 3.5 mA (D) 4.0 mA
Q.6 In a MOSFET used as a switch, which of
the following represents the ON-
resistance of the MOSFET when
VDS  VGS  Vth
(A) Cox W / L
(B) Cox W / L (VGS  Vth )

Electronic Devices & Circuits 45

 1 (B)
(C)
Cox W / L (VGS  Vth )
(D) 
Q.7 For an n-channel MOSFET and its
transfer curve shown in the figure, the
threshold voltage is
[GATE 2005, IIT Bombay] (C)

(D)

Q.9 Both transistors T1 and T2 shown in the

figure, have a threshold voltage of 1
volt. The device parameters K1 and K2
of T1 and T2 are, respectively, 36 A/V
2
(A) 1 V and the device is in active region.
(B) –1 V and the device is in saturation and 9 A/V . The output voltage V0 is
2

region.
[GATE 2005, IIT Bombay]
(C) 1 V and the device is in saturation
region.
(D) –1 V and the device is in active
region.
Q.8 The measured transconductance gm of
an NMOS transistor operating in the
linear region is plotted against the gate
voltage VG at a constant drain voltage
VD . Which of the following figures
(A) 1 V (B) 2 V
represents the expected dependence (C) 3 V (D) 4 V
of gm on VG ? Q.10 The source of a silicon ( ni  1010 per cm3)
[GATE 2008, IISc Bangalore] n-channel MOS transistor has an area
of 1 square m and a depth of 1 m . If
(A)
the dopant density in the source is
1019/cm3, the number of holes in the
source region with the above volume is
approximately
[GATE 2012, IIT Delhi]
(A) 107
(B) 100
(C) 10 (D) 0

46 Electronic Devices & Circuits

Q.11 In the circuit shown below, for the MOS
transistors;  nCox  100 A/V 2 and the
threshold voltage VTh  1 V . The voltage
Vx at the source of the upper transistor
is
[GATE 2011, IIT Madras]

The value of I D (in mA) is __________.

[GATE 2014 Set-02, IIT Kharagpur]
Q.14 The slope of the I D vs. VGS curve of an
n-channel MOSFET in linear region is
(A) 1 V (B) 2 V 103  1 at VDS  0.1 V . For the same
device, neglecting channel length
(C) 3 V (D) 4 V
modulation, the slope of the I D vs.
Q.12 For the n-channel MOS transistor
shown in the figure, the threshold VGS curve (in A /V ) under saturation
voltage VT is 0.8 V . Neglect channel region is approximately_____.
length modulation effects. When the [GATE 2014 Set-03, IIT Kharagpur]
drain voltage VD  1.6 V, the drain Q.15 For the circuit shown, assume that the
NMOS transistor is in saturation. Its
current I D was found to be 0.5 mA. If VD
threshold voltage VTh  1 V and its
is adjusted to be 2 V by changing the
transconductance parameter
values of R and VDD , the new value of
W 
I D (in mA) is  nCox    1 mA/V 2
L
[GATE 2014 Set-02, IIT Kharagpur] Neglect channel length modulation and
body bias effects. Under these
conditions, the drain current I D in mA
is _______.
[GATE 2017 Set-01, IIT Roorkee]

(A) 0.625 (B) 0.75

(C) 1.125 (D) 1.5
Q.13 For the MOSFETs shown in the figure,
the threshold voltage VTh  2 V and
1 W  Q.16 In a MOSFET operating in the saturation
K  Cox    0.1mA/V .
2
region, the channel length modulation
2 L 
effect causes [GATE 2013, IIT Bombay]

Electronic Devices & Circuits 47

 (A) an increase in the gate-source identical. The threshold voltage VT for
capacitance.
both transistors is 1.0 V. Note that VGS
(B) a decrease in the
transconductance. for M 2 must be > 1.0 V.
(C) a decrease in the unity-gain cutoff
frequency.
(D) a decrease in the output resistance.
Q.17 An n-channel enhancement mode
MOSFET is biased at VGS  VTh and
VDS  (VGS  VTh ) , where VGS is the gate-
to-source voltage, VDS is the drain-to- Current through the NMOS transistors
source voltage and VTh is the threshold can be modeled as
voltage. Considering channel length W  1 2 
I DS  Cox    (VGS  VT )VDS  VDS  for
modulation effect to be significant, the  L  2 
MOSFET behaves as a VDS  VGS  VT
[GATE 2017 Set-01, IIT Roorkee]
W 
(A) voltage source with zero output I DS  Cox   (VGS  VT ) 2 / 2
impedance. L
(B) voltage source with non-zero for VDS  VGS  VT
output impedance. The voltage (in volts, accurate to two
(C) current source with finite output decimal places) at V x is _______.
impedance.
[GATE 2018, IIT Guwahati]
(D) current source with infinite output
Q.20 In the circuit shown below, both the
impedance.
enhancement mode NMOS transistors
Q.18 Assuming that transistors M 1 and M 2 have the following characteristics :
are identical and have a threshold kn   nCox (W / L)  1 mA/V 2 ; VThN  1 V.
voltage of 1 V , the state of transistors Assume that the channel length
M1 and M 2 are respectively modulation parameter  is zero and
body is shorted to source. The
[GATE 2017 Set-02, IIT Roorkee]
minimum supply voltage VDD (in Volts)
needed to ensure that transistor M 1
operates in saturation mode of
operation is ______.
[GATE 2015 Set-03, IIT Kanpur]

(A) saturation, saturation

(B) linear, linear
(C) linear, saturation
(D) saturation, linear
W  Q.21 The threshold voltage for each
Q.19 In the circuit shown below, the  
 L transistor in the figure is 2 V. For this
value for M 2 is twice that for M 1 . The circuit to work as an inverter, Vi must
two NMOS transistors are otherwise take the values [GATE 1998, IIT Delhi]

48 Electronic Devices & Circuits

 Assume that, for both transistors, the
magnitude of the threshold voltage is 1 V and
the product of the transconductance
parameter and the (W/L) ratio i.e. the quantity
Cox (W /L) , is 1 mA/V2 .
[GATE 2009, IIT Roorkee]

(A)  5 V and 0 V (B)  5 V and 5 V

(C) 0 V and 3 V (D) 3 V and 5 V
Q.22 In the CMOS inverter circuit shown, if
the transconductance parameters of
the NMOS and PMOS transistors are
W Wp
kn  k p  nCox n   p Cox  40 A/V 2
Ln Lp
Q.23 For small increase in VG beyond 1 V,
and their threshold voltages are
which of the following gives the correct
VThn  VThp  1V, the current I is description of the region of operation
[GATE 2007, IIT Kanpur] of each MOSFET?
(A) Both the MOSFETs are in saturation
region.
(B) Both the MOSFETs are in triode
region.
(C) n-MOSFET is in triode and
p-MOSFET is in saturation region.
(D) n-MOSFET is in saturation and
p-MOSFET is in triode region.
Q.24 Estimate the output voltage
(A) 0 A (B) 25 A
V0 for VG  1.5 V . [Hint : Use the
(C) 45 A (D) 90 A
appropriate current-voltage equation
for each MOSFET, based on the answer
Statement for Linked
Answer Q.23 & 24 to previous question]
1 1
(A) 4  V (B) 4  V
Consider the CMOS circuit shown below, 2 2
where the gate voltage VG of the n-MOSFET
3 3
is increased from zero, while the gate voltage (C) 4  V (D) 4  V
of the p-MOSFET is kept constant at 3 V. 2 2

Q.1 The parameter of the transistor in (A) 1.69 V (B) 1.52 V

below figure are VTN  1.2 V , (C) 1.84 V (D) 0
Q.2 In the circuit of given figure the
K n  0.5mA / V 2 and   0 . The voltage
transistor parameters are VTN  1.7 V
VDS is
and K n  0.4 mA / V .
2

Electronic Devices & Circuits 49

 Q.6 The value of VDS is
(A) 4.59 V (B) 3.43 V
(C) 7.78 V (D) 6.48 V
Q.7 Consider the circuit shown in below
figure. The transistor parameters are
1
VTH  1V and    n cox  18 A / V .
2

2
Determine the width to length ratio
If I D  0.8mA and VD  1V , then value required in each transistor such that I D
of resistor RS and RD are respectively = 0.5 mA, V1  2 V and V2  5V .
(A) 2.36 k , 5 k (B) 5 k , 2.36 k
(C) 6.43k , 8.4 k (D) 8.4 k , 6.43k
Q.3 The parameters for the transistor in
circuit of given figure are VTN  2 V and
K n  0.2 mA / V 2 . The power dissipated
in the transistor is

W W W

(A)    1.74,    2.74,    3.74
 L 1  L 2  L 3
W W W
(A) 5.84 mW (B) 2.34 mW (B)    1.74,    6.94,    27.8
(C) 0.26 mW (D) 58.4 mW
 L 1  L 2  L 3
W W W
Common Data for (C)    3.74,    6.94,    6.94
 L 1  L 2  L 3
Questions 4 to 6
W W W
In the circuit shown in below figure the
(D)    2.74,    27.8,    16.94
 L 1  L 2  L 3
transistor parameters are as follows :
Threshold voltage VTN  2 V Conduction Common Data for
Questions 8 and 9
parameter K n  0.5mA / V 2
An NMOS transistor with vTH  1V has a drain
current I D = 0.8 mA when VGS = 3V and VDS =
4.5 V
Q.8 When VGS = 2 V, VDS = 4.5 V then the
drain current is
(A) 0.1 mA (B) 0.2 mA
(C) 0.3 mA (D) 0.4 mA
Q.9 When VGS = 3 V, VDS = 1 V then the drain
Q.4 The value of VGS is current is
(A) 2.86 V (B) 6.43 V (A) 0.4 mA (B) 0.5 mA
(C) 4.86 V (D) 3.91 V (C) 0.6 mA (D) 0.7 mA
Q.10 For the circuit shown in the below
Q.5 The value of I D is
figure, the MOSFET has IDSS  10mA and
(A) 1.863 mA (B) 1.485 mA
(C) 0.369 mA (D) 0.885 mA
Vp   4 V . The voltage VDS is

50 Electronic Devices & Circuits

 n Cox  100 A / V2 , L  1m and
W  32 m .
Neglect the channel-length modulation
effect (i.e. assume that   0 ).
Determine the value of R S .

(A) 5 V (B) 20 V
(C) 10 V (D) 0 V
Q.11 A MOSFET having  n  600 cm 2 /Vs ,
t ox  10nm , VT  1V , W/L= 50 with an
oxide layer of dielectric constant
ox  11.30 . Assuming transistor is in
saturation, the trans conductance is
(A) 5 k (B) 3.25 k
(C) 1.25 k (D) 2.25 k

Common Data for

Questions 14 to 16

An enhancement PMOS transistor has

k p' (W / L)  80 A / V ,
2
Vt  1.5V , and
   0.02V1 . The gate is connected to ground
and the source to + 5 V.
4 3
(A) 4.52 10 A/V (B) 7.75 10 A/V Q.14 Find the drain current for VD   4 V .
2 4
(C) 3.18 10 A/V (D) 7.75 10 A/V (A) 0.14 mA (B) 0.24 mA
Q.12 A MOSFET having VGG  5V , VT  1V (C) 0.34 mA (D) 0.44 mA
and RD  6 k , The minimum value of Q.15 Find the drain current for VD   1.5V .
VDD for transistor to be in saturation (A) 0.32 mA (B) 0.42 mA
is (C) 0.52 mA (D) 0.62 mA
Q.16 Find the drain current for VD   5V .
(A) 0.39 mA (B) 0.49 mA
(C) 0.59 mA (D) 0.69 mA
Q.17 The PMOS transistor in the circuit of
given figure has Vt   0.7 V ,
p C0x  60 A / V 2 , L  0.8 m and   0 .
Find the values required for R and W in
order to establish a drain current of
115 A and a voltage VD of 3.5 V.

(A) 8 V (B) 12 V
(C) 6 V (D) 10 V
Q.13 The circuit of below figure operates at
ID  0.4 mA and VD  0.5V . The NMOS
transistor has Vt  0.7 V,

Electronic Devices & Circuits 51

 (A) 3.04 k, 9.6 m (B) 3.04 k, 4.8 m (A) 0.125 mA (B) 1.125 mA
(C) 1.04 k, 9.6 m (D) 1.04 k, 4.8 m (C) 2.125 mA (D) 3.125 mA
Q.18 The transistor operates in saturation Q.20 Determine the current I Q in a MOSFET
with ID  0.5mA and VD   3V . Let the constant-current source. For the
enhancement type PMOS transistor circuit shown in given figure, the
transistor parameters are :
have Vt  1V and k 'p (W / L)  1mA / V 2
k n1  0.2 mA / V 2 ,
. Assume   0 . Determine the value of
VGS . k n 2  k n3  k n 4  0.1mA / V 2 and
VTh1  VTh2  VTh3  VTh4  1V .

(A) – 1 V (B) – 2 V
(C) 1 V (D) 2 V
Q.19 The NMOS and PMOS transistors in the
circuit of given figure are matched with (A) 0.225 mA (B) 0.115 mA
k 'n (Wn / Ln )  k 'p  Wp / Lp   1mA / V 2 (C) 0.335 mA (D) 0.445 mA
and Vtn  Vtp  1V . Assuming   0 for Q.21 Consider an n-channel enhancement-
mode MOSFET with the following
both devices, find the drain current, for
parameters : VTh  0.75V , W  40 m ,
vI  0V .
L  4 m ,  n  650cm 2 / V  sec ,
t 0x  450 A 0 and
ox  (3.9) (8.85 1014 ) F / cm . Determine
the current when VGS  2 VTh , for the
transistor biased in the saturation
region.
(A) 0.14 mA (B) 0.24 mA
(C) 0.34 mA (D) 0.44 mA

Assignment 1 space change width is –0.518 V. The

Assuming a  2 f , where  s  voltage semiconductor doping is ________
at strong inversion and is the voltage 1013 cm3 . (Assume ni  1.5 1010 cm 3 ,
developed at the metal semiconductor VT  25.9 milli Volts)
junction interface at zero bias, then the Assignment 3
value of  s (given N A  1016 and In a MOS capacitor, the gate voltage
ni  1.5 1010 ) for MOS capacitor will be exceeds the threshold voltage by 1 V. If
_____ V? the oxide thickness is 25 nm, then the
inversion charge density of the channel
Assignment 2
Consider n-type silicon in MOS is _______ 108 C/cm2 . (Assume
14
structure at T = 300 K. The surface ox  3.90 , 0  8.85 10 F/cm )
potential that results in maximum
52 Electronic Devices & Circuits
Assignment 4 Assignment 7
Consider a process technology for For a depletion-type NMOS transistor
which W 
with Vt  2 V and kn'    2 mA/V ,
2

Lmin  0.4 μm, tox  8 nm, n  450 cm /V  s, 2

L 
and Vt  0.7 V. find the minimum vDS required to
operate in the saturation region when
(a) Find Cox and k n' . vGS  1 V. What is the corresponding
W 8 μm value of iD ?
(b) For a MOSFET with  ,
L 0.8 μm Assignment 8
calculate the values of VGS and The depletion-type MOSFET in figure
VDS min needed to operate the W 
has kn'    4 mA/V 2 and Vt  2 V.
transistor in the saturation region L
with a dc current I D  100 μA. What is the value of I DSS ? Neglecting
(c) For the device in (b), find the value the effect of vDS on iD in the saturation
of VGS required to cause the device region, find the voltage that will appear
to operate as a 1000- resistor for at the source terminal.
every small vDS .
Assignment 5
For a 0.8 - m process technology for
which tox  15 nm and  n  550c m /V  s,
2

'
find Cox , kn , and the over-drive voltage
VOV  VGS  Vt required to operate a
W
transistor having  20 in saturation
L Assignment 9
with I D  0.2 mA. What is the minimum Find i as a function of v for the circuit
value of VDS needed? in figure. Neglect the effect of vDS on iD
Assignment 6 in the saturation region.
Us the expression for operation in the
triode region to show that an n-channel
MOSFET operated in saturation with an
overdrive voltage VOV  VGS  Vt and
having a small VDS across it behaves
approximately as a linear resistance
rDS ,
1
rDS 
 'W 
 kn L VOV 

Calculate the value of rDS obtained for

a device having kn'  100 μA/V 2 and
W
 10 when operated with an
L
overdrive voltage of 0.5 V.

Electronic Devices & Circuits 53

 Classroom Questions
1. D 2. B 3. A 4. D 5. D
6. C 7. C 8. A 9. C 10. D
11. C 12. C 13. 0.9 14. 0.07 15. 2
16. D 17. C 18. C 19. 0.422 20. 3
21. A 22. C 23. D 24. D
Practice Questions
1. B 2. A 3. B 4. A 5. C
6. C 7. B 8. B 9. C 10. C
11. B 12. D 13. B 14. B 15. C
16. C 17. B 18. B 19. B 20. A
21. A
Assignment Questions
1. 0.67 2. 33.03
(a) 194 μA / V 2 , (b)
VDS min  VGS  Vt  0.32 V
3. 13.8 4.
(c) VGS  1.22 V
5. 2.3 fF/μm2 ;127 μA/V 2 ;0.40 V;0.40 V 6. 2 kΩ
7. 3 V; 9 mA 8. 8 mA; +1 V
W 1 2
i  kn'  Vt v  2 v  ,
L 
9. 1 W 2
for v  Vt ; i  kn' V ,
2 L t
for v  Vt

Note : For detailed solutions, scan the QR code Given below,



54 Electronic Devices & Circuits

 5 MOS Capacitor
Basic MOS Capacitor Structure
The simple two terminal MOS structure is shown in below Gate
figure (a). It consists of 3 layers
Metal : This layer is a metal gate electrode. Also an highly Metal
doped Poly-Silicon layer can also be used as the metal layer. SiO2
 
The Poly-Silicon may be n or p doped.

Oxide : This layer is generally made up of Silicon dioxide and

is expected to work as an insulation layer between metal layer Semi conductor
and semi-conductor layer. Oxide layer is required to have high
quality of insulation. Bulk
Semiconductor : This layer is made up of semi-conductor Fig. (a) Basic structure of
material, generally Silicon. This semi-conductor portion is also MOS Capacitor
called Bulk or Substrate. It acts as another electrode of the
two terminal MOS structure.
 The semi-conductor can be of p-typed doped as well as n-type doped.
 The electrical equivalent circuit of use capacitor is shown below.

Gate Semi Body

Metal
Conductor

SiO2

Fig. (b) MOS Structure

1. ‘DC and low frequency Signal’ C versus VGS of MOS :
For p-type substrate in MOS Capacitor,
Accumulation mode : Accumulation occurs typically for negative voltages where the
negative charge on the gate attracts holes from the substrate to the oxide-semiconductor
interface.
Depletion mode : Depletion occurs for positive
voltages. The positive charge on the gate pushes
the mobile holes into the substrate. Therefore,
the semiconductor is depleted of mobile carriers
at the interface and a negative charge, due to the
ionized acceptor ions, is left in the space charge
region.
Inversion mode : In inversion, there exists a
negatively charged inversion layer at the oxide- Fig. Capacitance Vs VGS for NMOS at
semiconductor interface in addition to the low frequency
depletion-layer.

Electronic Devices & Circuits 55

2. AC signal behavior of MOS capacitor : (High frequency)

Fig. Capacitance Vs VGS for NMOS at high frequency

3. Energy band diagram of MOSFET :
(A) NMOS transistor (p-type substrate) :
Case 1 : VG  0 V

Case 2 : VG  0 (Moderate positive gate voltage)

or 0  VG  VThn

Case 3 : VG  VThn (i.e. high positive gate voltage)

Strong inversion layer is created

(B) PMOS transistor (n-type substrate)
Case 1 : VG  0 volt

Accumulation of electrons

56 Electronic Devices & Circuits

 Case 2 : VG  0 volt (i.e. moderate negative gate voltage) or VThp  VG  0

Case 3 : VG  V Thp (i.e. high negative gate voltage)

Strong inversion layer is created

4. Flat Band Voltage (VFB ) and Non-idealities in a MOS-CAP

The voltage which is applied at the gate terminal for getting flat energy band diagram at
Si -SiO2 interface, is known as flat - band voltage (VFB ) .
1. Non-idealities due to presents of fixed charge :
 If a fixed amount of POSITIVE charges are available at SiO2 , then amount of voltage that
has to be applied at Gate terminal to make flat energy band diagram at Si  SiO2
interface is called “Flat Band Voltage”.
Qox
 Mathematically, VFB   (Valid for p-type substrate)
Cox
2. Non-idealities when work function of metal and semiconductor are not equal :
Here ms  m  s , it is called Metal-SC work function difference
VFB  m  s  ms
E0
EC
EF M
EF

EV

Where, E0  vacuum energy level

3. Flat band voltage when both idealities 1 and 2 are present :
Qox
VFB  ms 
Cox
“Electron Affinity” is the energy needed by an e  in lowest level of conduction band ( Ec )
to escape out from the device and move to the vacuum.
4. Maximum width of Depletion Region/ Space Charge Region (NMOS) :
2  1 
Wd (max)     2 f 
q  NA 

Electronic Devices & Circuits 57

 NA
Here,  f  VT ln volt (NMOS) = Fermi potential = Bulk potential.
ni
Important Formulas
kT  N A 
1. Bulk potential or Fermi potential, B  ln
q  ni 
2. Gate voltage when surface voltage is equal to twice of bulk voltage,
2q si N A (2 B )
VG   (2 B )
Cox'
3. Inversion charge in Inversion Mode, Qinv  Cox' (VG  VT )

Therefore, Qinv  VG  VT
4. Gate voltage in Inversion Mode,
2q si N A (2 B )
VG  s  2 B
 VT   (2 B )
Cox'
where, VT is the ideal threshold voltage.
5. Gate voltage in Depletion Mode,
2q si N A B
VG   B [Depletion Mode (Intrinsic Semiconductor bulk)]
Cox'
2q si N A B
VG  s  2 B
   B  VT
Cox'

Q.1 The threshold voltage of an n-channel function is 4.1 eV and electron affinity
MOSFET can be increased by of Si is 4.0 eV, EC  EF  0.9 eV , where
[GATE 1994, IIT Kharagpur]
EC and E F are conduction band
(A) increasing the channel dopant
concentration. minimum and the Fermi energy levels
(B) reducing the channel dopant of Si, respectively. Oxide layer
14
concentration. permittivity  r  3.9, 0  8.85 10 F/cm
(C) reducing the gate-oxide thickness. . Oxide thickness tox  0.1 m and
(D) reducing the channel length. 19
Q.2 If fixed positive charges are present in electronic charge q  1.6 10 C. If the
the gate oxide of an n-channel measured flat band voltage of this
enhancement type MOSFET, it will lead capacitor is 1 V , then the magnitude
to of the fixed charge at the oxide-
[GATE 2014 Set-01, IIT Kharagpur] semiconductor interface, in (nC/cm2) is
(A) a decrease in the threshold voltage. ______. [GATE 2017, IIT Roorkee]
(B) channel length modulation. Q.4 A silicon n-channel MOSFET has a
(C) an increase in substrate leakage threshold voltage of 1 V and oxide
current. 8 2
thickness of 400×10 cm .
(D) an increase in accumulation 14
[  r (SiO2 )  3.9, 0  8.854 10 F/cm,
capacitance.
Q.3 A MOS capacitor is fabricated on p- q  1.6 1019 C ]
type Si (Silicon) where the metal work

58 Electronic Devices & Circuits

 The region under the gate is ion (A) holes.
implanted for threshold voltage (B) electrons.
tailoring. The dose and type of the (C) positively charged ions.
implant (assumed to be a sheet charge (D) negatively charged ions.
at the interface) required to shift the Q.8 The modified work function of an N
threshold voltage to – 1 V are channel MOSFET is – 0.85 V. If the
[GATE 1996, IISc Bangalore]
interface charge is 3 10 4 C/m3 and the
(A) 1.08 10 /cm , p-type
12 2
oxide capacitance is 300 F/m2 , the flat
(B) 1.08 10 /cm , n-type
12 2
band voltage is
(C) 5.4 1011 /cm2 , p-type (A) – 1.85 V (B) – 0.15 V
(C) + 0.15 V (D) + 1.85 V
(D) 5.4 1011 /cm2 , n-type
Q.5 The figure shows the band diagram of Common Data for
a Metal Oxide Semiconductor (MOS). Questions 9 to 11
The surface region of this MOS is in
[GATE 2016 Set-01, IISc Bangalore] The figure shows the high-frequency
capacitance voltage (C-V) characteristics of a
Metal/ SiO2 /silicon (MOS) capacitor having an
area of 110 4 cm2 . Assume that the
permittivities (0  r ) of silicon and SiO2 are
110 –12 F/cm and 3.5 1013F/cm respectively.
[GATE 2007, IIT Kanpur]

(A) inversion (B) accumulation

(C) depletion (D) flat band
Q.6 Consider the following statements S1
and S2. Q.9 The gate oxide thickness in the MOS
S1 : The threshold voltage (VTh ) of a capacitor is
MOS capacitor decreases with (A) 50 nm (B) 143 nm
increase in gate oxide thickness. (C) 350 nm (D) 1 μm
S2 : The threshold voltage (VTh ) of a Q.10 The maximum depletion layer width in
MOS capacitor decreases with silicon is
increase in substrate doping (A) 0.143 m (B) 0.857 m
concentration. (C) 1 m (D) 1.143 m
Which one of the following is correct? Q.11 Consider the following statements
[GATE 2004, IIT Delhi] about the C-V characteristics plot.
(A) S1 is FALSE and S2 is TRUE. S1 : The MOS Capacitor has an n-type
(B) Both S1 and S2 are TRUE. substrate.
(C) Both S1 and S2 are FALSE. S2 : If positive charges are introduced
(D) S1 is TRUE and S2 is FALSE. in the oxide, the C-V plot will shift to
Q.7 A MOS capacitor made using p-type the left.
substrate is in the accumulation mode. Then, which of the following is true ?
The dominant charge in the channel is [GATE 2007, IIT Kanpur]
due to the presence of (A) Both S1 and S2 are true.
[GATE 2005, IIT Bombay] (B) S1 is true and S2 is false.
Electronic Devices & Circuits 59
 (C) S1 is false and S2 is true. only insulator material X of thickness
(D) Both S1 and S2 are false. teq .
Q.12 A voltage VG is applied across a MOS If the capacitors are of equal
capacitor with metal gate and p-type capacitance, then the value of teq (in
silicon substrate at T  300 K . The nm) is _______.
inversion carrier density (in number of [GATE 2016 Set-03, IISc Bangalore]
carriers per unit area) for VG  0.8 V is
2 1011 cm2 , For VG  1.3 V , the
2
inversion carrier density is 4 10 cm .
11

What is the value of the inversion

carrier density for VG  1.8 V ?
[GATE 2016 Set-02, IISc Bangalore]
2 2
(A) 4.5 10 cm (B) 6.0 10 cm
11 11

2 2
(C) 7.2 10 cm (D) 8.4 10 cm
11 11

Q.13 An ideal MOS capacitor has boron

3
doping-concentration of 10 cm in the
15

substrate. When a gate voltage is

applied, a depletion region of width
0.5 m is formed with a surface
(channel) potential of 0.2 V . Given that
0  8.854 1014 F/cm and the relative
permittivities of silicon and silicon Q.15 The band diagram of the
dioxide are 12 and 4 respectively, the semiconductor region in an MOS
peak electric field (in V/m ) in the oxide capacitor is as follows :
region is_________.
[GATE 2014 Set-03, IIT Kharagpur] EC
Q.14 Figures 1 and 2 shows two MOS
capacitors of unit area. The capacitor in EF
figure 1 has insulator materials X (of EV
thickness t1  1 nm and dielectric
Oxide Substrate (semi-conductor)
constant 1  4 ) and Y (of thickness
The MOS capacitor is operating in
t2  3 nm and dielectric constant (A) Inversion (B) Flat band
2  20 ). The capacitor in figure 2 has (C) Depletion (D) Accumulation

Q.1 Consider C-V graph of a MOS capacitor C

shown below. The gate oxide thickness
of the MOS capacitor is. 7 pF
13
Given :  SiO2  3.5  10 F/cm and area
 1104 cm . 1 pF
V
0
(A) 50 nm (B) 143 nm
(C) 350 nm (D) 100 nm

60 Electronic Devices & Circuits

Q.2 Which of the following is the correct
plot of high frequency C-V
characteristics of a n-substrate EC
MOSCAP.
C Ei
0.3 eV
EF
0.3 eV
EV

(A) VG If tox  0.1 cm , then the value of

C minimum capacitance per unit area (in
nF/cm 2 ) is_______.(Rounded upto three
decimal places)
[Given :
T  300 k ,  Si  12 , 0  8.854 1014 F/cm
(B) VG , ox  40 , ni  1.5 1010 cm 3 ]
C Q.5 An ideal MOS capacitor (p-type
semiconductor) is shown in the figure.
The MOS capacitor is under strong
inversion with VG  2 V . The
corresponding inversion charge density
(C) VG (Qin ) is 2.2 C/cm2 . Assume oxide
C capacitance per unit area as
Cox  1.7 F/cm . For VG  4 V the value
2

of Qin is________ C/cm2 (rounded upto

one decimal place)
Oxide Semiconductor
VG Metal
(D)
Q.3 For a MOSFET with gate plate area VG
0.5 102 cm2 and oxide layer thickness
80 nm, the value of MOS capacitance
and its breath down voltage are Q.6 Consider the C-V plat of MOS capacitor
(assume  r ( SiO2 )  4 , shown below
C (in pF)
0  8.854 1014 F/cm and dielectric
strength of SiO2 firm is 5 106 V/cm ) 10

(A) 0.22 F and 40 V

(B) 0.22 nF and 40 V 2

(C) 1.22 F and 40 V V

Vth
(D) 1.08 nF and 80 V
If ox  0.36 1012 F/cm ,
Q.4 A MOS capacitor is fabricated on p-
type Si. The energy band diagram is  Si  1.04 1012 F/cm and thickness of
shown in the figure below. the oxide layer tox  1.8 m , then the
maximum value of the width of the
depletion region will be________.
Electronic Devices & Circuits 61
 (A) 1.02 m (B) 5.06 m E (V/cm)

(C) 10.02 m (D) 20.8 m

Q.7 N-type semiconductor MOS capacitor 0 tox Wmax
operates in accumulation mode if X (cm)

(A) Applied voltage is greater than flat

band voltage
(C)
(B) The gate positively charged with E (V/cm)
respect to body
(C) Holes are accumulated under the
silicon dioxide layer
X (cm)
(D) The bands bend down and 0 tox Wmax
conduction band moves towards
fermi level
(D)
Q.8 Which diagram is/are correct for Q.9 MOS capacitor fabricated with metal
inversion in n-type semiconductor. with work function 4 eV and p-type Si
with electron affinity 3.8 eV. The
conduction band of Si is 0.8 eV above
the fermi energy. If  r (SiO2 )  3.9 ,

EC 0  8.854 1014 F/cm , measured flat

band voltage of MOS cap is 1V and
S EFn
 Fn magnitude of the charge at oxide
EFi
semiconductor inter face is 15.4 nC/cm2
EV , then oxide thickness (in nm)
(A) is________. (Rounded off to the nearest
integer)
Q.10 An ideal MOS capacitor with p-type
substrate has doping concentration of
EC N A  1.2 1015 cm 3 , oxide capacitance
Fn
S EFn Cox  2 109 F/cm2 ,  si  1.04 1012 F/cm .
EFi If the body terminal is grounded then
the gate voltage required to produce a
EV surface potential of 0.026 V at the
semiconductor oxide layer interface
(B) will be ________V. (rounded upto three
decimal places)

62 Electronic Devices & Circuits

 Classroom Questions
1. A 2. A 3. 6.903 4. A 5. A
6. C 7. A 8. 4.33 9. A 10. B
11. C 12. B 13. 2.4 14. 1.6 15. D
Assignment Questions
1. A 2. B 3. B 4. 12.194 5. 5.6
6. D 7. A, B, D 8. A, C 9. 90 10. 1.637

Note : For detailed solutions, scan the QR code Given below,



Electronic Devices & Circuits 63

 6 CMOS
Introduction :
CMOS Stands for “Complementary Metal Oxide Semiconductor”. It consists of PMOS and NMOS
FET. The input serves as the gate voltage for both transistors. When a high voltage ( ~ VDD ) is
given at input terminal of the inverter, the PMOS becomes an open circuit, and NMOS short circuit
so the output will be pulled down to VSS (0 volt).
Similarly when logic low voltage is applied at input of inverter then PMOS is short circuited and
NMOS is open circuited results output is high ( VDD ).

1. Transfer Characteristic of Practical CMOS Inverter

2. Power Dissipation in CMOS Inverter

(1) Static power :

Fig. (a) Fig. (b)

64 Electronic Devices & Circuits

 (a) Static power exists due to leakage current in stable state or steady state of CMOS
inverter.
(b) PD  static   V DD  I leakage where, I leakage  I leakage( NMOS)  I leakage(PMOS)
(c) Static power is the power consumed by the MOSFET during stable state i.e. it is the
power consumed by MOSFET during continuously ON at logic 1 and continuously OFF
at logic 0.
(2) Dynamic capacitive power :

Fig. (a) Fig. (b)

Fig. Charging of capacitor by PMOS

Fig. (c) Fig. (d)

Fig. Discharging of capacitor by using NMOS
(a) It is the power consumed by the MOSFET during its transition state i.e. power
consumed by the MOSFET during logic 1 to logic 0 or logic 0 to logic 1.
(b) It depends on charging and discharging of capacitive load.
(c) It is also referred as switching power dissipation.
(d) Energy stored in PMOS,
1
ED (PMOS)  CVDD
2

2
1
Energy stored in NMOS, ED (NMOS)  CVDD 2

2
Energy stored in CMOS, ED (CMOS)  ED ( NMOS)  ED (PMOS)  CVDD
2

Dynamic power dissipation of CMOS inverter,

ED (CMOS)
Pdynamic(CMOS) 
T
Pdynamic(CMOS)  f SW CVDD
2
where, f SW = Switching frequency.
f SW  f
Where,   Activity factor ( 0    1 ) and f  Operating frequency.
If  is not mentioned then we assume   1 .
Electronic Devices & Circuits 65
 (3) Dynamic short circuit power :
This power is due to flow of short circuit current from VDD to ground, when both
transistors are in saturation region.
Dynamic short circuit power is given by,
I maxVDD f
PD (short circuit)  (tr  t f ) where, tr  Rise time and t f  Fall time.
2
3. I D -Vin Curve of CMOS Inverter is Shown Velow
ID

C
I D(max)

Vin
0 VDD
2
At point C, (when both NMOS and PMOS are in saturation) the drain current I D is maximum
and therefore, in this case maximum power dissipation will occur in CMOS.
4. Input Threshold Voltage of CMOS Inverter is given by,
kn
VDD  VThp  VTh
kp n
Vin  VITh 
kn
1
kp
kn
If  1.0 and VThn  VThp [Symmetric CMOS inverter]
kp
V
Vin  VITh  DD
2
5. Mobility of Electron is Two (or Three) Times That of The Mobility of Hole
In order to make kn  k p ,
 nCox  W   p Cox  W 
    
2  L n 2  L p
W  W 
n     p  
 L n  L p
W  W 
2.6  p     p  
 L n  L p
W  W 
2.6     
 L n  L  p
Hence, Aspect ratio of PMOS  2.6  aspect ratio of NMOS
 Key Point
For proper designing of CMOS inverter the aspect ratio of PMOS must be 2.6 times of the
aspect ratio of NMOS
 Wp  W 
i.e.    2.6  n 
 Lp   Ln 

66 Electronic Devices & Circuits

6. Positive Logic & Negative Logic in CMOS
For  ve logic :
Source of NMOS  lowest potential  0 volt
Source of PMOS  highest potential  VDD volt
For ve logic :
Source of NMOS  lowest potential  VDD
Source of PMOS  highest potential  0 volt

7. Dynamic Power Dissipation in CMOS Circuit

2
ECMOS CVDD
PDynamic  
(Time Period) T
PDynamic   f C VDD
2

i.e., PDynamic  (Frequency of input signal)
This implies that there must be a limitation of applied input signal frequency otherwise
the power dissipation will increase and it may damage the CMOS device.

Q.1 The threshold voltage for each

transistor in the figure is 2 V. For this
circuit to work as an inverter, Vi must
take the values
[GATE 1998, IIT Delhi]

Which of the following is correct?

[GATE 2002, IISc Bangalore]
(A) Only Statement 1 is TRUE.
(B) Only Statement 2 is TRUE.
(C) Both the statements are TRUE.
(D) Both the statements are FALSE.
Q.3 In the CMOS inverter circuit shown, if
the transconductance parameters of
(A)  5 V and 0 V (B)  5 V and 5 V the NMOS and PMOS transistors are
W Wp
(C) 0 V and 3 V (D) 3 V and 5 V kn  k p  nCox n   p Cox  40 A/V 2
Ln Lp
Q.2 Consider the following statements in and their threshold voltages are
connection with the CMOS inverter in
the figure, where both the MOSFETs are
VThn  VThp  1V, the current I is
of enhancement type and both have a [GATE 2007, IIT Kanpur]
threshold voltage of 2 V.
Statement 1 : T1 conducts when
Vi  2 V .
Statement 2 : T1 is always in saturation
when V0  0 V .

Electronic Devices & Circuits 67

 (A) 0 A (B) 25 A Q.6 In the CMOS circuit shown below,
electron and hole mobilities are equal,
(C) 45 A (D) 90 A
and M 1 and M 2 are equally sized. The
Statement for Linked device M 1 is in the linear region if
Answer Q.4 & Q.5
[GATE 2012, IIT Delhi]

Consider the CMOS circuit shown below,

where the gate voltage VG of the n-MOSFET
is increased from zero, while the gate voltage
of the p-MOSFET is kept constant at 3 V.
Assume that, for both transistors, the
magnitude of the threshold voltage is 1 V and
the product of the transconductance
parameter and the (W/L) ratio i.e. the quantity
Cox (W /L) , is 1 mA/V2 .
[GATE 2009, IIT Roorkee]
(A) Vin  1.875 V
(B) 1.875 V  Vin  3.125 V
(C) Vin  3.125 V
(D) 0  Vin  5 V
Q.7 What is the voltage Vout in the following
circuit?
[GATE 2016 Set-02, IISc Bangalore]

Q.4 For small increase in VG beyond 1 V,

which of the following gives the correct
description of the region of operation
of each MOSFET?
(A) Both the MOSFETs are in saturation
region.
(B) Both the MOSFETs are in triode
region.
(C) n-MOSFET is in triode and
p-MOSFET is in saturation region. (A) 0 V
(D) n-MOSFET is in saturation and VTh of PMOS  VTh of NMOS
p-MOSFET is in triode region. (B)
2
Q.5 Estimate the output voltage (C) Switching threshold of inverter
V0 for VG  1.5 V .
(D) VDD
[Hint : Use the appropriate current-
Q.8 Transistor geometries in a CMOS
voltage equation for each MOSFET,
inverter have been adjusted to meet
based on the answer to previous
the requirement for worst case charge
question]
and discharge times for driving a load
1 1 capacitor C. This design is to be
(A) 4  V (B) 4  V
2 2 converted to that of a NOR circuit in the
same technology, so that its worst case
3 3 charge and discharge times while
(C) 4  V (D) 4  V
2 2 driving the same capacitor are similar.
68 Electronic Devices & Circuits
 The channel lengths of all transistors (A) Width of PMOS transistors should
are to be kept unchanged. Which one of be doubled, while width of NMOS
the following statement is correct? transistors should be halved.
[GATE 2016 Set-02, IISc Bangalore] (B) Width of PMOS transistors should
be doubled, while width of NMOS
transistors should not be changed.
(C) Width of PMOS transistors should
be halved, while width of NMOS
transistors should not be changed.
(D) Widths of PMOS transistors should
be unchanged, while width of NMOS
transistors should be halved.

Q.1 A CMOS inverter which has output Q.2 Consider and CMOS inverter
voltage V0 is equal to 2.7 V and has VD D
maximum source current of 16 A .
Given :
Vi V0
W
VDD  4 V , k p  kn  Cox  40 A/V ,
2

L
VTN  VTP  0.7 V , where VTN and VTP
are threshold voltage of PMOS and
Given : VDD  5V , VTN  VTP  1V ,
NMOS respectively.
VD D W
kn  nCox   100 A/V2 and
L
W
Vi V0 k p   pCox   50 A/V2
L
VDD
When Vi   2.5V . The static power
2
drawn by the CMOS inverter (in mW) is
The W/L ratio of the PMOS is _______.
_______. (rounded upto three decimal
(rounded upto three decimal places)
places)
Electronic Devices & Circuits 69
Q.3 A CMOS inverter is better than an I D (mA)

inverter using only one transistor and a

0.8
resistance for application in digital VGS  5 V
system because
0.6
(A) CMOS inverter provides faster
switching speed
0.4 VGS  4 V
(B) CMOS inverter does not power on
both “ON” and “OFF” states
0.2 VGS  3 V
(C) CMOS inverter does not consume
VGS  2 V
power during the switching event
0 0.5 1 1.5 2 2.5 3 3.5 4 5 6 VDS (V)
(D) CMOS inverter is linear circuit
Q.7 The threshold voltage of each
Q.4 Consider an inverter circuit as given in
transistor in figure (i), (ii), (iii) is
the figure below V01 is the output
VTN  0.4 V . The region of operation of
voltage of inverter 1 and Vi 2 is the input the transistor in each circuit is
voltage of inverter 2. Both the inverter 2.2 V

0.6 V

3V

  
have the following characteristics. 

2.2 V
1V
 

1V



VDD  5V , ViL  1.35V , ViH  1.15V , VoL  0.33V

1V


, VoH  3.84V Fig. (i) Fig. (ii) Fig. (iii)

Vo 1 Vi2 (i) (ii) (iii)
1 2
(A) Saturation Cutoff Cutoff
The inverter low and high noise margin Non-
(B) Cutoff Saturation
respectively are (in volt) saturation
(A) 1.02, 2.69 (B) 2.69, 1.02 Non-
(C) Saturation Cutoff
(C) 2.5, 2.5 (D) 1, 4 saturation
Q.5 The current in an NMOS transistor is (D) Cutoff Saturation Cutoff
0.5 mA when VGS  VTN  0.6V and Q.8 The threshold voltage of each
transistor in Figure (i), (ii), (iii) is
1.0 mA when VGS  VTN  1.0V , Keeping
VTP  0.4 V , the region of operation of
VDS constant. The device is operating in
the transistor in each circuit.
the non-saturated region. Where   
2.2 V 2V 2V

1 W  
kn  n cox . The VDS applied is (in 

2.2 V
 
2 L 1V

1V


volt) and k n in (mA/ v2 ) respectively are

(A) 0.8, 0.23 (B) 0.4, 1.56 Fig. (i) Fig. (ii) Fig. (iii)
(C) 0.2, 2.8 (D) 0.1, 6.1 (i) (ii) (iii)
Q.6 The transistor characteristics Non-
(A) Cutoff Saturation
I D versus VDS for an NMOS device are saturation
Non-
shown in Figure below. For VGS  3.5V (B) Cutoff Saturation
saturation
the value of I D (in mA) is _________. Non-
(C) Saturation Cutoff
(Rounded upto three decimal places). saturation
(Assume NMOS operating in saturation (D) Saturation Saturation Cutoff
region) Given : k n (average) = 0.0640 Q.9 The process transconduction
1 W parameter Kn  ncox for an NMOS
mA/V 2 , where kn  n cox
2 L transistor with  n  600 cm 2 /V-s and for

70 Electronic Devices & Circuits

 0 When the transistor is biased in the
an oxide thickness tox of 25A is
saturation region with VGS  1.4V, the
_________ μA/V 2 . (Rounded upto two
drain current is I D  0.6 mA . Where
decimal place) [Given : ox  3.9 0 ]
Kn  ncox . The channel width (in μm ) is
Q.10 An NMOS device has parameters
(A) 22.2 (B) 44.4
VTN  0.8V, L  0.8 m, and
(C) 23 (D) 11.1
K n  120 A/V 2 .

Classroom Questions
1. A 2. A 3. C 4. D 5. D
6. A 7. C 8. B
Assignment Questions
1. 0.473 2. 0.562 3. A, B 4. A 5. B
6. 0.256 7. C 8. A 9. 828.36 10. A

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Electronic Devices & Circuits 71

 7 Special Purpose Diodes
Introduction
Now we are at the last stage of this subject which is named as special purpose diodes. From the
name itself it is clear that these diodes are designed for a particular operations, here we are
going to learn about Zener Diode, LEDs, Solar cell, Photodiodes.
1. Zener Diode
The operation of a Zener diode is like a normal diode in forward biased mode. That means a large
majority current flows through the device when the forward potential is applied to it. However,
a Zener shows variation from a normal diode in the aspect of its doping concentration. Zener
diode is highly doped thus its depletion width is very thin. Due to this, more current flows through
a Zener diode as compared to a normal junction diode.
It specifically acts in the breakdown region in the reverse biased condition. A Zener diode
shows two breakdown approach, Zener breakdown, and avalanche breakdown.
(i) Avalanche Breakdown (R.B) :
 High Reverse Bias voltage is required.
 Here impact ionization means collision mechanism.
(ii) Zener Breakdown (R.B) :
 Concentration is 1 in 105 in Zener Diode.
 Both sides are heavily doped.
 Here, zener breakdown occurs “due to rupture of covalent bond” due to large electric
field. This process is known as “field Ionization”.[Tunnelling]
(iii) Punch through (R.B) :

2  1 
 W   V0  VR 
q  ND 
1 1 1 1 1
If N A  N D then,   
N ND N A N ND
 Here, VR does not decide the magnitude of current.
 Widely used in Industries as “Punch through” devices.
2. Solar Cell (R.B)
Solar cell (also known as a photovoltaic cell or PV cell) is defined as an
electrical device that converts light energy into electrical energy through the
photovoltaic effect. A solar cell is basically a p-n junction diode. Solar cells
are a form of photoelectric cell, defined as a device whose electrical
characteristics-such as current, voltage, or resistance-vary when exposed to
light.
Magnitude of reverse photocurrent, I ph is directly proportional to the intensity of light.

72 Electronic Devices & Circuits

 V0
VT
Total current I  I 0 (e  1)  I ph
 Key Point
ve sign is with I ph because I ph is flowing from n to p
Parameters of solar cell :

(a) Percentage rise of minority 

 Pn0  P    Pn0  100%
Pn 0
Where, P  Excess generated carriers.

(b) Efficiency  
 maxmium power delivered by solar cell 
 Incident power per unit area from sun 

 Key Point
The maximum area of rectangle that can be drawn gives the maximum power of solar cell.

Area of Rect1 Vm I m
(c) Fill factor ( FF )  
Area of Rect2 Voc I sc
Maximum power delivered by solar cell
Also,  
Input power from radiation of sun light/Area×Area of solar panel
Pmax V I FF Voc  I sc

 m m 
Pin Pin Pin
A
A
(d) Calculation of open circuited voltage (Voc )
Voc
VT
I  I 0e  I ph (Intensity of light)
Voc

0  I 0e VT  ( I ph )(Intensity of light)

Voc
VT
I ph  I 0 e
 I ph 
Voc  VT ln  
 I0 
 Key Point
Solar cell operates in 4th quadrant of V-I characteristics.
3. Photodiode (Reverse Bias)
Photodiode is a PN-junction diode that consumes light energy to produce an electric current.
They are also called a photo-detector, a light detector, and a photo-sensor. Photodiodes are

Electronic Devices & Circuits 73

designed to work in reverse bias condition. Typical photodiode materials are Silicon, Germanium
and Indium gallium arsenide.
 In photodiode, we apply reverse biasing of the diode. So, it works in 3rd quadrant.
 Difference between solar cell and photodiode
Solar cell Photodiode
(1) Area is large (1) Area is less
(2) Working in 4th quadrant (2) Working in 3rd quadrant
(3) No external voltage is applied (3) R.B. external voltage is applied

II Quadrant I Quadrant

V V

III Quadrant IV Quadrant

I
I ph (Photo current) I ph
 Responsivity   [A/watts]
Power Incident Light Pin
I ph
i.e., R
Power
N (Number of charge carriers generated)
 Quantum efficiency,    QE 
n (Number of incident photons)
(QE )q
 R
h
4. LED (Operated in Forward Bias) :
 Light emitting diode is two lead semiconductor light source.
 The LED is a special type of diode and they have similar electrical characteristics to a
pn junction diode
 Hence it allows flow of current in Forward Bias (FB) and block the current in Reverse
Bias (RB).
 It is a specially doped diode and made up of a special type of semiconductors (like GaAs,
GaAsP).
 When it is forward bias light emits.
 LED symbol

 Working principle of LED :

The working principle of light emitting diode is based on the quantum theory of
electrolaminesence
 The quantum theory says that When the electrons comes down from higher energy level
to the lower energy level then the energy emits in the form of photon.
74 Electronic Devices & Circuits
  The photon energy is equal to
the energy gap between these
two energy levels.
hc
 EG 

where, h  Planck’s constant
(6.63 10 34 Js) , C  Speed of
light (3 10 m/s)
8

  Wavelength of light (in μm) .

1.24
 EG  eV Fig. Working principle of LED
(m)
The Main Difference Between a Diode & a LED Includes The Following
Diode LED
The semiconductor device like a diode The LED is one type of diode, used to
conducts simply in one direction. generate light.
The designing of the diode can be done The LED is designed with the Gallium
with a semiconductor material & the Phosphide (GaP) and Gallium Arsenide
flow of electrons in this material can (GaAs) whose electrons can generate
give their energy in the heat form. light while transmitting the energy.
The diode changes the AC into the DC. The LED changes the voltage into light.
It has a high reverse breakdown voltage. It has a low-reverse breakdown
voltage.
The on-state voltage of the diode is 0.7 The on-state voltage of LED
V for silicon whereas, for germanium, it approximately ranges from 1.2 to 2.0 V.
is 0.3 V.
The diode is used in voltage rectifiers, The applications of LED are traffic
clipping, clamping and voltage signals, automotive headlamps, in
multipliers. medical devices, camera flashes, etc.
There are different types of light-emitting diodes present and some of them are mention below:
 Gallium Arsenide (GaAs) - Infra-red
 Gallium Arsenide Phosphide (GaAsP) - Red to infra-red, orange
 Aluminium Gallium Arsenide Phosphide (AlGaAsP) - High - Brightness red, orange-red,
orange, and yellow.
 Gallium Phosphide (GaP) - Red, yellow and green.
 Aluminium Gallium Phosphide (AlGaP) - Green.
 Gallium Nitride (GaN) - Green, emerald green.
 Gallium Indium Nitride (GalnN) - Near-ultraviolet, bluish-green and blue.
 Silicon Carbide (SiC) - Blue as a substrate.
 Zinc Selenide (ZnSe) - Blue.
 Aluminium Gallium Nitride (AlGaN) - Ultraviolet.

Electronic Devices & Circuits 75

Q.1 Direct band gap semiconductors
[GATE 1987, IIT Bombay]
(A) exhibit short carrier life time and
they are used for fabricating BJT's.
(B) exhibit long carrier life time and
they are used for fabricating BJT's.
(C) exhibit short carrier life time and
they are used for fabricating lasers.
(D) exhibit long carrier life time and The maximum efficiency (in %) of the
they are used for fabricating lasers. device is _____.
Q.2 A particular green LED emits light of [GATE 2016 Set-03, IISc Bangalore]
0
wavelength 5490 A . The energy Q.5 For a particular intensity of incident
bandgap of the semiconductor material light on a silicon p-n junction solar cell,
used is (Planck's constant  6.626 1034 the photo current density ( J L ) is
J-s) 2.5 mA/cm2 and the open circuit
[GATE 1995, IIT Kanpur] voltage ( VOC ) is 0.451 V , consider
(A) 2.26 eV (B) 1.98 eV
thermal voltage ( VT ) to be 25 mV. If the
(C) 1.17 eV (D) 0.74 eV
intensity of the incident light is
Q.3 Red (R), Green (G) and Blue (B) Light increased by 20 times, assuming that
Emitting Diodes (LEDs) were fabricated the temperature remains unchanged,
using p-n junctions of three different
VOC (in volts) will be ______.
inorganic semiconductors having
different band-gaps. The built-in [GATE 2017 Set-02, IIR Roorkee]
voltages of red, green and blue diodes Q.6
2
A solar cell of area 1.0 cm , operating
are VR , VG and VB , respectively. Assume at 1.0 sun intensity, has a short circuit
donor and acceptor doping to be the current of 20 mA and an open circuit
same ( N A and N D , respectively) in the voltage of 0.65 V. Assuming room
p and n sides of all the three diodes. temperature operation and thermal
equivalent voltage of 26 mV, the open
Which one of the following
circuit voltage (in volts, correct to two
relationships about the built-in
decimal places) at 0.2 sun intensity is
voltages is TRUE?
______. [GATE 2018, IIT Guwahati]
[GATE 2018, IIT Guwahati] Q.7 When the optical power incident on a
(A) VR  VG  VB (B) VR  VG  VB photodiode is 10 W and the
responsivity is 0.8 A/W, the
(C) VR  VG  VB (D) VR  VG  VB
photocurrent generated (in A ) is
Q.4 The figure shows the I-V _________.
characteristics of a solar cell [GATE 2014, IIT Kharagpur]
illuminated uniformly with solar light of Q.8 Choose proper substitutes for X and Y
2
power 100 mW/cm . The solar cell has to make the following statement
2
an area of 3 cm and a fill factor of 0.7. correct. Tunnel diode and Avalanche
photo diode are operated in X bias and
Y bias respectively.
[GATE 2003, IIT Madras]
(A) X : reverse, Y : reverse
(B) X : reverse, Y : forward

76 Electronic Devices & Circuits

 (C) X : forward, Y : reverse (A) Applied voltage
(D) X : forward, Y : forward (B) Current injected
Q.9 The light emitting diode (LED) emits (C) Temperature
light of particular colour because (D) Level of doping
(A) It is fabricated from a fluorescent Q.13 Statement (I) : Photodiodes are not
material used in relay circuits.
(B) Transition between energy levels of
Statement (II) : The current needed to
the carrier takes place while
activate photodiodes is very low even
crossing the pn junction
at high light intensities.
(C) Heat generated in the diode is
(A) Both Statement (I) and Statement
converted in to light
(II) are individually true and
(D) The band gap of the semiconductor
Statement (II) is the correct
material used in the fabrication of
explanation of statement (I)
the diode is equal to the energy hv
(B) Both Statement (I) and Statement
of the light photon
(II) are individually true but
Q.10 An LED made using GaAs emits
Statement (II) is not the correct
radiation in
explanation of Statement (I)
(A) Visible region
(B) Ultraviolet region (C) Statement (I) is true but Statement
(C) Infrared region (II) is false.
(D) Microwave frequency region (D) Statement (I) is false but Statement
Q.11 Consider the following statements : (II) is true
1. The efficiency of a light emitting Q.14 In a photoconductive cell the
diode (LED) decreases with the resistance of the semiconductor
injected current. material varies with intensity of
2. The efficiency of a LED increases incident light.
with a decreases in temperature. (A) directly (B) inversely
3. The light emitted is concentrated (C) exponentially (D) loganithmically
near the junction because most of Q.15 Photoconductivity is a characteristic of
the carriers are within a diffusion semiconductors. When light falls on
length of the junction. certain semiconductors, it
4. Light is emitted in a LED when (A) sets free electrons from some of
electrons move from the valence the atoms, increasing the
band to the conduction band. conductivity.
Which of these statements are correct? (B) ejects electrons into space
(A) 1, 2, 3 and 4 (B) 1 and 2 only (C) establishes a potential difference
(C) 3 and 4 only (D) 2 and 3 only creating a source of EMF
Q.12 The efficiency of an LED for generating (D) produces heat raising the
light is directly proportional to the temperature.

Q.1 Colour of light of LED depends on Q.3 In a photodiode, light is focused to fall
(A) Its forward bias voltage on
(B) Its reverse bias voltage (A) only at the junction
(C) Forward current magnitude (B) n region only
(C) only p and n regions but not at
(D) Semiconductor material
junction
Q.2 The maximum wave length of photons
(D) p and n regions including junction
that can be detected by a photo diode
made of a semiconductor of band gap Q.4 The photovoltaic cell is placed 0.7 m
2eV is ________ nm. away from a lamp having an intensity
of 180 candela. The window area
Electronic Devices & Circuits 77
 through which the light from the lamp (A) both the current and junction
is made incident upon the cell is 1680 voltage is positive (1st quadrant or
mm2. The luminous flux incident upon 2nd quadrant)
the cell is __________ lumens. (B) both the current and junction
Q.5 A solar cell has a dark resistance of voltage is negative (3rd quadrant)
200 k and a resistance of 10 k in a (C) current is positive but junction
day time. If time constant of the cell is voltage is negative (2nd quadrant)
100msec. then the resistance of the (D) current is negative but junction
cell after 30 msec of application of a voltage is positive (4th quadrant)
light beam is ____________ (in k ). Q.8 In the circuit shown below, the
Q.6 A pin photo detector has an active area diode(LED) has cut-in voltage of 1 V &
of 15 mm2 and responsivity is 0.4 AAV. some non-zero internal resistance. If
It is illuminated by a light of intensity the current through the LED is 5 mA,
1.5 mW/cm2. The value of the  of the then power in mW dissipated in the
transistor is ________ LED is ________.
[assume VBE = 0.7 V and VCE = 2 V] 700 
20 V
2 k
6V
C

Q.9 Which of the following material is used

B
in light-emitting diodes?
E (A) Gallium arsenide sulphate
(B) Gallium arsenide phosphide
Q.7 Find the correct statement for the I-V (C) Gallium chromate phosphide
curve of a solar cell (D) Gallkum phosphide sulphate

Assignment 1 when the light intensity is doubled?

Show that the change in emitted What are the values when the intensity
wavelength  with T from an LED is is halved?
approximately given by Assignment 3
d hc  dEg  A photoconductor with dimensions
 2  L  6 mm, W  2 mm, and D  1 mm is
dT Eg  dT 
placed under uniform illumination. The
Where Eg is the band gap. Consider a absorption of light increases the
dEg current by 2.83 mA. A voltage of 10 V is
GaAs LED with Eg of 1.42 eV and  applied across the device. As the
dT
radiation is suddenly cut off, the
 4.5 104 eVK 1. What is the change in current falls, initially at the rate of
the emitted wavelength if the
0
23.6 A s 1. The electron mobility is
temperature change is 10 C?
3600 cm 2 V 1s 1.
Assignment 2
(a) Find the equilibrium density of
A solar cell at room temperature is
2
electron-hole pairs generated under
under an illumination of 500 Wm and radiation.
has a short circuit current, I SC , of 150 (b) The minority-carrier lifetime.
mA and an open circuit voltage, VOC , of (c) The excess density of electrons and
0.53 V. What are the short circuit holes remaining 1 ms after the
current and the open circuit voltage radiation is turned off.
78 Electronic Devices & Circuits
 Classroom Questions
1. C 2. A 3. B 4. 21 5. 0.525
6. 0.608 7. 8 8. C 9. D 10. C
11. C 12. B 13. D 14. B 15. A
Practice Questions
1. D 2. 620 3. D 4. 0.617 5. 59.244
6. 100 7. D 8. 12.5 9. B

Assignment Questions
For double intensity :
I SC"  75 mA, VOC"  0.48 V
1.   2.77 nm 2.
For half intensity :
I SC'  300 mA, VOC'  0.55 V
(a) 1.47  1013 cm3
3. (b) 3.44  109 cm3
(c) 119.6 sec

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Electronic Devices & Circuits 79