Faculty of Information and

Engineering Technology
Dr. Tallal Elshabrawy
Dr. Wassim Alexan

Bar Code

Digital Logic Design (ELCT 201)

Spring 2021
Midterm Exam
May 26th 2021
Please read carefully before proceeding.
1. The duration of this exam is 2 hours
2. Calculators are permitted for this exam.
3. Write your solutions in the space provided. If you need more space, write on the
back of sheet containing the problem.
4. Attempt as much of the problems as you can within the time limits. The more you
solve the higher your score is expected to be.
5. This exam booklet contains 16 pages, including this one.

6. Two extra sheets have been added at the end of the exam.

7. Good Luck!

Problem 1 2 3 4 5 Total
Number
Possible Marks 20 20 10 15 15 80
Final Marks

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Problem 1:

Choose The Correct Answer

(You have to use the table below for the solutions by circling only ONE correct
answer)

Q1 A B C D Q8 A B C D
Q2 A B C D Q9 A B C D
Q3 A B C D Q10 A B C D
Q4 A B C D Q11 A B C D
Q5 A B C D Q12 A B C D
Q6 A B C D Q13 A B C D
Q7 A B C D Q14 A B C D

1) In a 3-variable K-map, how many adjacent cells would result in a

term with a single literal?
A. 2
B. 4
C. 8
D. 16

2) A tri-state buffer has 3 states: logic 0, logic 1 and a third state that is
called high impedance, which
A. Behaves like a closed circuit
B. Behaves like a buffer
C. Behaves like an inverter
D. Behaves like an open circuit

3) Given a binary multiplier that takes as input two binary numbers, one
of them is 3-bits and the other is 4-bits long. How many bits are
needed to fully represent the output?
A. 4 bits
B. 5 bits
C. 6 bits
D. 7 bits

4) Why is an N-bit binary ripple carry adder extremely slow?

A. Because it is implemented with half adders
B. Because it is implemented with full adders
C. Because each stage must wait for the next one to get the carry
from it
D. Because each stage must wait for the previous one to get the
carry from it

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5) How many full adders are required to build a 7-bit ripple carry adder?
A. 7
B. 27
C. 26
D. 8
6) Which of the following expressions depicts the output C1?

A. C1= C0P0+G0
B. C1= C0P1+G1
C. C1= G0P1+C0
D. C1= G0P0+G0

7) In a 6-variable K-map, how many cells need to have a 1 so that the

simplified expression is equal to 1?
A. 6
B. 8
C. 32
D. 64

8) Which of the following combinational logic circuits can be used to

introduce redundancy at the transmission side of a communication
system?
A. A parity checker
B. A parity generator
C. A multiplexer
D. A magnitude comparator

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9) THE XOR Function could be implemented using how many transistors
assuming basic logic gates?
A. 5
B. 22
C. 20
D. 21

10) For an Odd Parity Checker?

A. It can detect all patterns with odd number of errors
B. It can detect single errors only
C. It can detect single and double errors
D. It can detect all patterns with even number of errors

11) A 4 × 16 decoder could be constructed from

A. Two 3 × 8 decoders without need for any gates
B. Four 2 × 4 decoders without need for any gates
C. Five 2 × 4 decoders without need for any gates
D. Four 2 × 4 decoders with the addition of only one basic gate

12) In an 8 × 3 priority encoder, if inputs (𝐷0 , 𝐷1 , 𝐷2 , 𝐷3 , 𝐷4 , 𝐷5 , 𝐷6 , 𝐷7 ) = (1,

0,1,0,0,0,1,0), the encoder output (𝐴0 , 𝐴1 , 𝐴2 ) would be (Note that
subscript 0 is always the least significant bit)
A. (0,1,0)
B. (1,1,0)
C. (0,1,1)
D. (0,0,1)

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13) The following circuit implements the function F(x,y,z) =

A. (𝛴(1,4))(𝛴(4,6))
B. Π(0,2,3,5,7)
C. Σ(0,2,3,5,7)
D. Π(1,4,6)

14) The following circuit implements the function F(x,y,z) =

A. 𝛴(1,2,6,7)
B. 𝛴(0,2,6,7)
C. 𝛴(0,1,2,3)
D. 𝛴(0,2,4,5)

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Problem 2:

Simplify the function H(A,B,C,D) using K-Maps. Then implement the logic diagram
of the simplified Boolean expression using NAND gates.
𝐻=𝐹⊕𝐺
𝐺(𝐴, 𝐵, 𝐶, 𝐷) = Π𝑀(0,1,2,3,6,7,8,9,12,14,15)

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Problem 3:

One of the schemes that could be used in communication for error correction is a
repetition code. Let’s assume a 1/3 repetition code that works as follows:
− At the transmitter side, if we want to send binary 0, we repeat it three times
and send (0,0,0).
− At the transmitter side, if we want to send binary 1, we repeat it three times
and send (1,1,1).
− At the receiver side, three bits are received that may be different from what
was transmitted due to errors.
− The receiver applies a majority vote to determine whether binary 0 or 1
have been transmitted (i.e., the receiver declares binary 0 if the number of
ones in the received three coded bits is less than or equal to 1 and declares
binary 1 otherwise)
Construct a combinatorial logic circuit that implements the receiver side and
implement using basic logic gates.

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Problem 4:

Given that a, b are two 2-bit binary numbers (𝑎0 , 𝑎1 ), (𝑏0 , 𝑏1 ) with subscript 0
corresponding to the least significant bit. Design a circuit that implements the
mathematical function 𝑓 = 𝑎 × 𝑏 + 1 using two half adders, one full adder and four
AND gates.

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Problem 5:

Assume you are given a comparator block as shown below with four inputs and
compares two 2-bit numbers (𝐴0 , 𝐴1 ) and (𝐵0 , 𝐵1 ) with subscripts 0 corresponding to
least significant bits. The comparator has three outputs that behave as follows:
𝐹0 = 1 if 𝐴 > 𝐵, 𝐹1 = 1 if 𝐴 < 𝐵 and 𝐹2 = 1 if 𝐴 = 𝐵

Comparator

You are required to design a combinatorial circuit that computes the function |A-B|
where || is the absolute value operator. Your design should be composed of full
adders and xor gates only in addition to the comparator.

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Extra Sheet (1)

15
Extra Sheet (2)

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