UNIT 3

ANALOG AND DIGITAL ELECTRONICS

SEMICONDUCTORS
Semiconductors are the materials having conductivity in between conductors and
insulators.
Features of Semiconductor
1. Semiconductors have resistivity between that of conductors and insulators.
2. Semiconductors have negative temperature coefficient of resistance
(Resistance decreases with increase in temperature).
3. Semiconductors are crystalline in nature.
4. Conductivity of semiconductors can be considerably increased by adding
impurities to it.

Intrinsic Semiconductors
Semiconductors in its pure form is called Intrinsic semiconductor. At absolute
zero temperature intrinsic semiconductor behaves as insulator. However, at room
temperature the electrons present in the outermost orbit absorb thermal energy. When
the outermost orbit electrons get enough energy then they will break bonding with
the nucleus of atom and jumps in to conduction band. The electrons present in
conduction band are not attached to the nucleus of an atom so they are free to move.
When the valence electron moves from valence band to the conduction band a
vacancy is created in the valence band where electron left. Such vacancy is called
hole.

In semiconductors, current is caused by both electrons in conduction band and

holes in valence band. Current that is caused by electron motion is called electron
current and current that is caused by hole motion is called hole current. Electron
is a negative charge carrier whereas hole is a positive charge carrier.
Let’s take an example, as shown in figure above. There are three atoms atom A, atom
B and atom C. At room temperature valence electron in an atom A gains enough
energy and jumps in to conduction band as show in fig (1). When it jumps in to
conduction band a hole (vacancy) is created in the valence band at atom A as shown
in fig (2). Then the neighboring electron from atom B moves to atom A to fill the
hole at atom A. This creates a hole at atom B as shown in fig (3). Similarly
neighboring electron from atom C moves to atom B to fill the hole at atom B. This
creates a hole at atom C as shown in fig (4). Likewise, electrons move from left side
to right side and holes moves from right to left side.

The process of conduction in intrinsic semiconductor is shown in below fig.

In the fig., an intrinsic semiconductor is connected to a battery.

Here, positive terminal of battery is connected to one side and negative terminal of
the battery is connected to other side. As we know, like charges repel each other and
opposite charges attract each other. In the similar way, negative charge carriers
(electrons) are attracted towards the positive terminal of battery and positive charge
carriers (holes) attracted towards the negative terminal of battery.

Electrons will experience a attractive force from the positive terminal, so they
move towards the positive terminal of the battery by carrying the electric current.
Similarly holes will experience a attractive force from the negative terminal, so they
moves towards the negative terminal of the battery by carrying the electric current.
Thus, in a semiconductor electric current is carried by both electrons and holes. In
intrinsic semiconductor the number of free electrons in conduction band is equal to
the number of holes in valence band. The current caused by electrons and holes is
equal in magnitude. The total current in intrinsic semiconductor is the sum of hole
and electron current.

Total current = Electron current + Hole current

I = Ihole+ Ielectron

The electric current that flows from positive terminal of battery to the negative
terminal of battery is called conventional current. The conventional current direction
is in the same direction of flow of holes but opposite to the direction of flow of free
electrons.

Extrinsic Semiconductors
Extrinsic semiconductors are semiconductors that are doped with specific
impurities. The impurity modifies the electrical properties of the semiconductor and
makes it more suitable for electronic devices such as diodes and transistors. The
process of adding impurities deliberately is termed as doping and the atoms that are
used as an impurity are termed as dopants. The impurity modifies the electrical
properties of the semiconductor and makes it more suitable for electronic devices
such as diodes and transistors. The dopant added to the material is chosen such that
the original lattice of the pure semiconductor is not distorted. Also, the dopants
occupy only a few of the sites in the crystal of the original semiconductor, and it is
necessary that the size of the dopant is nearly equal to the size of the semiconductor
atoms.

While doping tetravalent atoms such as Si or Ge, two types of dopants are used,
and they are:
  Pentavalent atoms: Atoms with valency 5; such as Arsenic (As),
Phosphorous (Pi), Antimony (Sb), etc.
 Trivalent atoms: Atoms with valency 3; such as Indium (In), Aluminium
(Al), Boron (B), etc.
The reason behind using these dopants is to have similar-sized atoms as the
pure semiconductor. Both Silicon and Germanium atoms belong to the fourth group
in the periodic table. Hence, the choice of dopants from the third and fifth group is
more viable. This ensures that the size of the atoms is not very different from the
fourth group. Therefore, the trivalent and pentavalent choices. These dopants give
rise to two types of semiconductors as follows:

 n-type semiconductors
 p-type semiconductors

n-type Semiconductors
When a tetravalent atom such as Si or Ge is doped with a pentavalent atom, it
occupies the position of an atom in the crystal lattice of the Si atom. The four of the
electrons of the pentavalent atom bond with the four neighboring silicon atoms, and
the fifth one remains weakly bound to the parent atom. As a result, the ionization
energy required to set the fifth electron free is very low, and the electrons become
free to move in the lattice of the semiconductor. Such semiconductors are termed as
n-type semiconductors.
p-type Semiconductors
When a tetravalent atom such as Si or Ge is doped with a trivalent impurity
such as Al, B, In, etc., the dopant atom has one less electron than the surrounding
atoms of Si or Ge. Thus, the fourth atom of the tetravalent atom is free, and a hole
or vacancy is generated in the trivalent atom. In such materials, the holes are the
charge carriers, and such semiconductors are termed p-type semiconductors.
 PN Junction Diode
A PN-junction diode is formed when a p-type semiconductor is fused to an n-type
semiconductor creating a potential barrier voltage across the diode junction. The PN
junction thus formed will be as shown in figure below.

The holes from the p-side diffuse to the n-side, and the electrons from the n-
side diffuse to the p-side. These give rise to a diffusion current across the junction.
These electrons combine with the holes and become neutral at the junction. Also,
when an electron diffuses from the n-side to the p-side, an ionized donor is left
behind on the n-side, which is immobile. As the process goes on, a layer of positive
charge is developed on the n-side of the junction. Similarly, when a hole goes from
the p-side to the n-side, an ionized acceptor is left behind on the p-side, resulting in
the formation of a layer of negative charges in the p-side of the junction. This region
of positive charge and negative charge on either side of the junction is termed as the
depletion region. The term depletion because the region is depleted of holes and
electrons. An electric field is set up from positive space charges to negative space
charge which will prevent any further diffusion of holes and electrons into the region.
There develops a potential difference across the depletion layer due to the electric
field which is called as barrier potential.

The barrier potential of a PN junction depends upon several factors including

the type of semiconductor material, the amount of doping and temperature. The
typical barrier potential for silicon is 0.7V and for germanium 0.3 V.

Symbolic representation of a PN junction diode is given in the figure below.

Forward Biased PN Junction Diode

 When the p-type semiconductor is connected to the battery’s positive
terminal and the n-type semiconductor to the negative terminal, then the P-N
junction is said to be forward-biased. When the P-N junction is forward biased, the
VD will “pressure” electrons in the n-type material and holes in the p-type material
to recombine with the ions near the boundary and reduce the width of the depletion
region. When the applied voltage is high, the resistance of the depletion zone
becomes insignificant. At 0.6 V, the resistance of the depletion area in silicon
becomes absolutely insignificant, allowing a flood of electrons can pass through the
junction, resulting in an exponential rise in current as shown in the forward-bias
region of the characteristics. The forward characteristics of PN junction diode is
shown figure below.

The point at which sudden increase in current takes place in the static I-V
characteristics curve is called as the “knee” point.

Reverse Biased PN Junction Diode

 When a diode is connected with a positive voltage applied to the N-type
material and a negative voltage applied to the P-type material, the diode is said to be
reverse biased. The positive voltage applied to the N-type material attracts electrons
towards the positive electrode and away from the junction, while the holes in the P-
type end are also attracted away from the junction towards the negative electrode.
The net result is that the depletion layer grows wider due to a lack of electrons and
holes and presents a high impedance path, almost an insulator and a high potential
barrier is created across the junction thus preventing current from flowing through
the semiconductor material.
The reverse characteristics of a PN junction diode is shown in figure below.

As the reverse voltage is increased, reverse current reaches a saturation value until
reverse break down takes place. when the applied voltage in the reverse direction
exceeds a limit (called breakdown voltage), the diode starts conducting in the reverse
direction as well. This stage is called the breakdown in the diode.
The following two types of breakdowns take place in a PN-junction semiconductor
diode −
 Zener Breakdown
 Avalanche Breakdown
Zener Breakdown
The breakdown of PN junction in a semiconductor diode which occurs due to the
flow of free electrons across the junction is called Zener breakdown. The Zener
breakdown mainly occurs in the heavy doped diodes that have a thin depletion
region.
When a high electric field is applied across the PN junction in reverse direction, the
charge carriers start flowing across the junction. As a result of it, a heavy current
flow in the reverse direction through the diode. The Zener breakdown is temporary
breakdown of the PN junction in the diode, which does not destroy the diode.
Therefore, once the reverse voltage is removed, the PN junction regains its original
state.
The value of reverse voltage at which the Zener breakdown in the PN junction diode
takes place is called the Zener voltage. The Zener breakdown takes place in highly
doped PN junction diodes.
Avalanche Breakdown
The type of PN junction breakdown in which the applied electric field in the reverse
direction across the diode increases the velocity of charge carriers and these charge
carriers create a large number of hole-electron pairs by colliding with the atoms of
the semiconductor materials is called the avalanche breakdown.
In case avalanche breakdown, the production of hole-electron pairs is continuous
which causes an avalanche of free charge carries. The flow of free charge carriers
across the junction results a high reverse current in the diode which permanently
destroys the PN junction.
The applied reverse voltage at which the avalanche breakdown occurs is called
avalanche breakdown voltage. The avalanche breakdown mainly occurs in such PN
junction diodes that have thick depletion region. The avalanche breakdown in the
diode is permanent, i.e. it cannot regain its original state.
 APPLICATIONS OF PN JUNCTION DIODE
HALF-WAVE RECTIFIER

PN junction diode can be used to convert an AC signal (egs. Sinusoidal) into

a DC signal. The above process is called rectification and the circuit is called a
rectifier. There are two types namely half wave rectifier and full wave rectifier. If
one half cycle of the signal is passed and the other half cycle is blocked, the process
is called a half wave rectification and the circuit is called a half wave rectifier. A
half wave rectifier circuit is shown in the diagram below.

During the interval t = 0 → T/2 in the figure, the polarity of the applied voltage
vi is such as to forward bias the diode and turn on the diode so that output volage
will be same as input voltage. The circuit equivalence during this period and the
output wave form are shown in the figure below.
For the period t = T/2 → T, the polarity of the input vi is such that diode will be
reverse biased. The equivalent circuit and output are shown in figure below.

The result is the absence of a path for charge to flow and for the period T/2 →T. The
input vi and the output vo were sketched together in the figure below, for comparison
purposes.

The process of removing one-half the input signal to establish a dc level is

aptly called half-wave rectification.
.
Full Wave Rectifier (Bridge Network)
The dc level obtained from a sinusoidal input can be improved by using a
process called full-wave rectification. The most familiar network for
performing such a function appears in figure below with its four diodes in a
bridge configuration.
During the period t = 0 to T/2 the polarity of the input is as shown in figure
below.

D2 and D3 will be conducting and D1 and D4 will be in the “off” state

during the above period.

Since the diodes are ideal the load voltage is vo = vi, as shown in the same
figure.

For the negative region of the input the conducting diodes are D1 and D4,
resulting in the configuration of figure below.

The important result is that the polarity across the load resistor R is the same,
establishing a second positive pulse. Over one full cycle the input and output
voltages will appear as shown below.
Full Wave Rectifier (Center-Tapped Transformer)

A second popular full-wave rectifier appears in the figure above with only two
diodes but requiring a center-tapped (CT) transformer to establish the input
signal across each section of the secondary of the transformer. During the
positive portion of vi applied to the primary of the transformer, the network
will appear as shown in Fig. below.

D1 assumes the short-circuit equivalent and D2 the open-circuit equivalent,

as determined by the secondary voltages and the resulting current directions.
The output voltage appears as shown in the figure above. During the negative
portion of the input the network appears as shown below, reversing the roles
of the diodes but maintaining the same polarity for the voltage across the load
resistor R.
 Zener Diode
Diode designed with heavily doped P region and N region with narrow depletion
layer is called as Zener diode. Symbolic representation of Zener diode is shown in
figure below .

The location of the Zener region can be controlled by varying the doping levels. An
increase in doping, producing an increase in the number of added impurities, will
decrease the Zener potential. Zener diodes are available having Zener potentials of
1.8 to 200 V with power ratings from 0.25 to 50 W. Because of its higher temperature
and current capability, silicon is usually preferred in the manufacture of Zener
diodes.
Application (Voltage Regulator)

Zener Diodes can be used to produce a stabilized voltage output with low
ripple under varying load current conditions. By passing a small current through the
diode from a voltage source, via a suitable current limiting resistor (RS), the zener
diode will conduct sufficient current to maintain a voltage drop of Vout.
 Resistor, RS is connected in series with the zener diode to limit the current
flow through the diode with the voltage source, VS being connected across the
combination. The stabilized output voltage Vout is taken from across the zener diode.
The zener diode is connected with its cathode terminal connected to the positive of
the DC supply so that it is reverse biased and will be operating in its breakdown
condition. Resistor RS is selected so to limit the maximum current flowing in the
circuit.
With no load connected to the circuit, the load current will be zero, ( IL = 0 ),
and all the circuit current passes through the zener diode which in turn dissipates its
maximum power. Also, a small value of the series resistor RS will result in a greater
diode current when the load resistance RL is connected and large as this will increase
the power dissipation requirement of the diode so care must be taken when selecting
the appropriate value of series resistance so that the zener’s maximum power rating
is not exceeded under this no-load or high-impedance condition.
The load is connected in parallel with the zener diode, so the voltage
across RL is always the same as the zener voltage, ( VR = VZ ). There is a minimum
zener current for which the stabilization of the voltage is effective and the zener
current must stay above this value operating under load within its breakdown region
at all times. The upper limit of current is of course dependent upon the power rating
of the device. The supply voltage VS must be greater than VZ. The zener voltage
regulator consists of a current limiting resistor RS connected in series with the input
voltage VS with the Zener diode connected in parallel with the load RL in this reverse
biased condition. The stabilized output voltage is always selected to be the same as
the breakdown voltage VZ of the diode.
BIPOLAR JUNCTION TRANSISTORS
TRANSISTOR CONSTRUCTION
The transistor is a three-layer semiconductor device consisting of either two
n- and one p-type layers of material or two p- and one n-type layers of material. The
former is called an npn transistor, while the latter is called a pnp transistor. Both are
shown in the figure below with the proper dc biasing.

The dc biasing is necessary to establish the proper region of operation for ac

amplification. The emitter layer is heavily doped, the base lightly doped, and the
collector only lightly doped. The outer layers have widths much greater than the
sandwiched p- or n-type material. For the transistors shown in figure the ratio of the
total width to that of the center layer is 0.150/0.001 = 150:1. The doping of the
sandwiched layer is also considerably less than that of the outer layers (typically,
10:1 or less). This lower doping level decreases the conductivity (increases the
resistance) of this material by limiting the number of “free” carriers.
For the biasing shown in figure the terminals have been indicated by the
capital letters E for emitter, C for collector, and B for base. The term bipolar reflects
the fact that holes and electrons participate in the injection process into the
oppositely polarized material. If only one carrier is employed (electron or hole), it is
considered a unipolar device.

TRANSISTOR OPERATION

In figure below, the pnp transistor has been redrawn without the base-to-
collector bias.
 The depletion region has been reduced in width due to the applied bias,
resulting in a heavy flow of majority carriers from the p- to the n-type material.
Now, remove the base-to-emitter bias of the pnp transistor as shown below.

The flow of majority carriers is zero, resulting in only a minority-carrier flow,

as indicated in the figure. In the figure below both biasing potentials have been
applied to a pnp transistor, with the resulting majority- and minority-carrier flow
indicated. Note in the figure, the widths of the depletion regions, indicating clearly
which junction is forward-biased and which is reverse-biased.

As indicated in the figure, a large number of majority carriers will diffuse

across the forward-biased p-n junction into the n-type material. The question then is
whether these carriers will contribute directly to the base current IB or pass directly
into the p-type material. Since the sandwiched n-type material is very thin and has a
low conductivity, a very small number of these carriers will take this path of high
resistance to the base terminal. The magnitude of the base current is typically on the
order of microamperes as compared to milliamperes for the emitter and collector
currents. The larger number of these majority carriers will diffuse across the reverse-
biased junction into the p-type material connected to the collector terminal as
indicated in figure. The reason for the relative ease with which the majority carriers
can cross the reverse-biased junction is easily understood if we consider that for the
reverse-biased diode the injected majority carriers will appear as minority carriers in
the n-type material. In other words, there has been an injection of minority carriers
into the n-type base region material. Combining this with the fact that all the minority
carriers in the depletion region will cross the reverse-biased junction of a diode
accounts for the flow indicated in figure.
Applying Kirchhoff’s current law to the transistor of figure,
we get, 𝑰𝑬 = 𝑰𝑪 + 𝑰𝑩
The collector current, however, is comprised of two components—the
majority and minority carriers as indicated in figure. The minority-current
component is called the leakage current and is given the symbol ICO (IC current with
emitter terminal Open). The collector current, therefore, is determined in total by Eq.
𝑰𝑪 = 𝑰𝑪𝑴𝒂𝒋𝒐𝒓𝒊𝒕𝒚 + 𝑰𝑪𝑶𝑴𝒊𝒏𝒐𝒓𝒊𝒕𝒚
For general-purpose transistors, IC is measured in milliamperes, while ICO is
measured in microamperes or nanoamperes.

BJT CONFIGURATIONS

COMMON BASE CONFIGURATION

The notation and symbols used for the common-base configuration with pnp and
npn transistors are shown in the figure below.
 The common-base terminology is derived from the fact that the base is
common to both the input and output sides of the configuration. In addition, the base
is usually the terminal closest to, or at, ground potential. All the current directions
appearing in the figure are the actual directions as defined by the choice of
conventional flow. Note that in each case IE = IC + IB. Note also that the applied
biasing (voltage sources) are such as to establish current in the direction indicated
for each branch.
To fully describe the behavior of a three-terminal device such as the common
base amplifiers of the figure requires two sets of characteristics—one for the driving
point or input parameters and the other for the output side. The input set for the
common-base amplifier will relate an input current (IE) to an input voltage (VBE) for
various levels of output voltage (VCB) as shown in the figure below.
 The input characteristics reveal that for fixed values of collector voltage (VCB),
as the base-to-emitter voltage increases, the emitter current increases in a manner
that closely resembles the diode characteristics. In fact, increasing levels of VCB have
such a small effect on the characteristics.

The output set will relate an output current (IC) to an output voltage (VCB) for
various levels of input current (IE) as shown in figure below. The output or collector
set of characteristics has three basic regions of interest, as indicated in figure: the
active, cutoff, and saturation regions. The active region is the region normally
employed for linear (undistorted) amplifiers.

At the lower end of the active region the emitter current (IE) is zero, the
collector current is simply that due to the reverse saturation current ICO, as indicated
in figure. The current ICO is so small (microamperes) in magnitude compared to the
vertical scale of IC (milliamperes) that it appears on virtually the same horizontal
line as IC = 0.

As the emitter current increases above zero, the collector current increases to
a magnitude essentially equal to that of the emitter current as determined by the basic
transistor-current relations. Note also the almost negligible effect of VCB on the
collector current for the active region. The curves clearly indicate that a first
approximation to the relationship between I E and IC in the active region is given by
𝐼𝐶 ≅ 𝐼𝐸
As inferred by its name, the cutoff region is defined as that region where the
collector current is 0 A, as revealed on output characteristics.
 The saturation region is defined as that region of the characteristics to the left
of VCB = 0 V. The horizontal scale in this region was expanded to clearly show the
dramatic change in characteristics in this region. Note the exponential increase in
collector current as the voltage VCB increases toward 0 V.
With the transistor in the “on” or active state, the voltage from base to emitter
will be 0.7 V at any level of emitter current as controlled by the external network. In
fact, at the first encounter of any transistor configuration in the dc mode, one can
now immediately specify that the voltage from base to emitter is 0.7 V, if the device
is in the active region.

Alpha (∝)
In the dc mode the levels of IC and IE due to the majority carriers are related by a
quantity called alpha and defined by the following equation:
𝑰𝑪
∝𝒅𝒄 =
𝑰𝑬
where IC and IE are the levels of current at the point of operation. Even though the
output characteristics would suggest that 𝛼 = 1 for practical devices, the level of
alpha typically extends from 0.90 to 0.998, with most approaching the high end of
the range. Since alpha is defined solely for the majority carriers,
𝑰𝑪 = 𝑰𝑪𝑴𝒂𝒋𝒐𝒓𝒊𝒕𝒚 + 𝑰𝑪𝑶𝑴𝒊𝒏𝒐𝒓𝒊𝒕𝒚 becomes 𝑰𝑪 = 𝜶𝑰𝑬 + 𝑰𝑪𝑩𝑶

For the output characteristics, when IE = 0 mA, IC is therefore equal to ICBO, but as
mentioned earlier, the level of ICBO is usually so small that it is virtually undetectable
on the graph of output characteristics. In other words, when IE = 0 mA on the output
characteristics, IC also appears to be 0 mA for the range of VCB values.

COMMON-EMITTER CONFIGURATION

This is the most commonly used transistor configuration. Common emitter

configuration for pnp and npn transistors are shown in figure below.
 It is called the common-emitter configuration since the emitter is common or
reference to both the input and output terminals. Two sets of characteristics are again
necessary to describe fully the behavior of the common-emitter configuration: one
for the input or base-emitter circuit and one for the output or collector-emitter circuit.
Even though the transistor configuration has changed, the current relations
developed earlier for the common-base configuration are still applicable. That is,
𝐼𝐸 = 𝐼𝐶 + 𝐼𝐵 and 𝐼𝐶 = 𝛼𝐼𝐸
The output characteristics are a plot of the output current (IC) versus output
voltage (VCE) for a range of values of input current (IB). The input characteristics are
a plot of the input current (IB) versus the input voltage (VBE) for a range of values of
output voltage (VCE). Both the characteristics are shown in figure below.
 The magnitude of IB is in microamperes, compared to milliamperes of IC.
Consider also that the curves of IB are not as horizontal as those obtained for IE in
the common-base configuration, indicating that the collector-to-emitter voltage will
influence the magnitude of the collector current.
The active region for the common-emitter configuration is that portion of the
upper-right quadrant that has the greatest linearity, that is, that region in which the
curves for IB are nearly straight and equally spaced. In the figure (a) this region exists
to the right of the vertical dashed line at VCEsat and above the curve for IB equal to
zero. The region to the left of VCEsat is called the saturation region. The active region
of the common-emitter configuration can be employed for voltage, current, or power
amplification.
The cutoff region for the common-emitter configuration is the region below
IB=0.

Beta (𝜷)
In the dc mode the levels of IC and IB are related by a quantity called beta and
𝑰
defined by the following equation 𝜷𝒅𝒄 = 𝑪 , where IC and IB are determined at a
𝑰𝑩
particular operating point on the characteristics. For practical devices the level
typically ranges from about 50 to over 400, with most in the midrange.
COMMON-COLLECTOR CONFIGURATION
The common-collector configuration, shown in figure below with the proper
current directions and voltage notation.
 The common-collector configuration is used primarily for impedance-
matching purposes since it has a high input impedance and low output impedance,
opposite to that of the common-base and common-emitter configurations.

Input characteristics are the relationship between the input current and input
voltage keeping output voltage constant. Here input current is I B and input voltage
VBC and output voltage is VEC. The characteristics is shown in the figure below.
 Output characteristics are the relationship between the output current and
output voltage keeping input current constant. Here output current is I E and output
voltage is VEC and the input current is IB.

Common collector configuration has high input impedance and low output
impedance. It has low voltage gain, high current gain and the power gain is medium.
This configuration is mostly used for impedance matching, that is high impedance
source is used to drive low impedance load.
 OPERATIONAL AMPLIFIERS (Op-amp)
An operational amplifier, or op-amp, is a very high gain differential amplifier with
high input impedance and low output impedance. Symbol of an operational amplifier
is shown in figure below.

Figure 31
Single-ended input operation results when the input signal is connected to one input
with the other input connected to ground. In Fig. 32a, the input is applied to the plus
input (with minus input at ground), which results in an output having the same
polarity as the applied input signal. Figure 32b shows an input signal applied to the
minus input, the output then being opposite in phase to the applied signal.

Figure 32
In addition to using only one input, it is possible to apply signals at each input—this
being a double-ended operation. Figure 33a shows an input, Vd, applied between the
two input terminals, with the resulting amplified output in phase with that applied
between the plus and minus inputs. Figure 33b shows the same action resulting when
two separate signals are applied to the inputs, the difference signal being Vi1 - Vi2.
The output will be the amplified difference in signals Vi1 - Vi2.
 Figure 33
PRACTICAL OP-AMP CIRCUITS
The op-amp can be connected in a large number of circuits to provide various
operating characteristics. In this section, we cover a few of the most common of
these circuit connections.
Inverting Amplifier
The most widely used constant-gain amplifier circuit is the inverting amplifier, as
shown in Fig.34. The output is obtained by multiplying the input by a fixed or
constant gain, set by the input resistor (R1) and feedback resistor (Rf ).

Figure 34
The terminals (-) and (+) are virtually at the same potential. Apply KCL at the
terminal (-). Since the terminal (+) is grounded, the terminal (-) is also grounded
virtually.
𝑉1 −0 0−𝑉𝑂 𝑅𝑓
= . Therefore, 𝑉𝑂 = − 𝑉1
𝑅𝑖 𝑅𝑓 𝑅𝑖
𝑅𝑓
𝑉𝑂 = 𝐴𝑉 𝑉1 where 𝐴𝑉 = −
𝑅𝑖
Noninverting Amplifier
The connection of Fig. 35a shows an op-amp circuit that works as a noninverting
amplifier or constant-gain multiplier. It should be noted that the inverting amplifier
connection is more widely used because it has better frequency stability. To
determine the voltage gain of the circuit, we can use the equivalent representation
shown in Fig. 35b. Note that the voltage across R1 is V1 since Vi ≈ 0 V. This must be
equal to the output voltage, through a voltage divider of R1 and Rf, so that

Figure 35
𝑉 𝑅
Applying voltage division rule, 𝑂 1 = 𝑉1
𝑅1 +𝑅𝑓
𝑅𝑓 𝑅𝑓
Therefore, 𝑉𝑂 = 𝑉1 (1 + )=𝐴𝑉 𝑉1 where 𝐴𝑉 = 1 +
𝑅1 𝑅1

DIGITAL ELECTRONICS

Types of Number Systems

There are various types of number systems in mathematics. The four most common
number system types are:

1. Decimal number system (Base- 10)

2. Binary number system (Base- 2)
3. Octal number system (Base-8)
4. Hexadecimal number system (Base- 16)

Decimal Number System

The decimal system consists of 10 symbols (single-digit numbers) 0, 1, 2, 3,
4, 5, 6, 7, 8 and 9. The number 9 is followed by 10, which is followed by 11, then
12, and so on. The number on the left is incremented by 1 each time the digit to the
right goes beyond 9. For example, 20 follows 19, 30 follows 29, 100 follows 99, and
1000 follows 999. The positional values of decimal numbers to the left of decimal
point are 100, 101, 102, 103 etc. and to the right of decimal point are 10-1, 10-2, 10-3
etc.
Egs. The decimal number 1457.32=(1x103)+(4x102)+(5x101)+(7x100)+
(3x10-1)+(2x10-2) .

Octal Number System

Octal number system uses 8 symbols (0,1,2,3,4,5,6,7) to represent numbers. Octal

number system will be as follows: ,1,2,3,4,5,6,7,10,11,12,13,14,15,16,17,20,21, etc.
75,76,77,100,101,102,…. Etc. 775,776,777,1000,1001,1002 etc. The positional
values of octal numbers to the left of octal point are 80, 81, 82, 83 etc. and to the right
of decimal point are 8-1, 8-2, 8-3 etc. Octal numbers can be converted to equivalent
decimal number by multiplying each digit with its positional values and add
them all.

Egs.1 (153.21)8 =(1x82)+(5x81)+(3x80)+(2x8-1)+

(1x8-2)=(1x64)+(5x8)+(3x1)+(0.25)+(0.015625)=(107.265625)10

Egs.2

2158 = 2 × 82 + 1 × 81 + 5 × 80

= 2 × 64 + 1 × 8 + 5 × 1

= 128 + 8 + 5

= 14110

Conversion from Decimal number to Octal number

Divide the part of the number to the left of decimal point repeatedly by 8 and
remove the remainder. Read the remainders from bottom to top. To find the
fractional part, repeatedly multiply with 8 and remove the part to the left of decimal
point. Read the removed part from top to bottom.
Example 1: Convert (127)10 to Octal.

Solution: Divide 127 by 8

127 ÷ 8= 15(Quotient) and (7) Remainder

Divide 15 by 8 again.

15 ÷ 8 = 1(Quotient) and (7) Remainder

Divide 1 by 8, we get;

1 ÷ 8 = 0(Quotient) and (1) Remainder

Since the quotient is zero now, no more division can be done. So by taking the
remainders in reverse order, we get the equivalent octal number.

Hence, (127)10 = (177)8

Example 2

(0.542)10= ?

0.542 x 8=4.336, Remove 4

0.336 x 8=2.688 Remove 2

0.688 x 8=5.504 Remove 5 and continue the same way

Read from top to bottom (0.425…)8

(0.542)10= (0.425…)8

Binary Number System

Binary number system uses 2 symbols namely 0 and 1 to represent numbers.

Binary number system will be as follows: 0,1,10,11,100,101,110,111,1000 etc. The
positional values of binary numbers to the left of octal point are 20, 21, 22, 23 etc. and
to the right of decimal point are 2-1, 2-2, 2-3 etc. Binary numbers can be converted
to equivalent decimal number by multiplying each digit with its positional
values and add them all.
Egs. (1001.01)2=?

(1001.01)2=(1 x 23)+(0 x 22)+ (0 x 21)+(1 x 20)+(0 x 2-1)+(1 x2-2)=

8+1+0.0+0.25=(9.25)10

Conversion from Decimal number to Binary number

Divide the part of the number to the left of decimal point repeatedly by 2 and
remove the remainder. Read the remainders from bottom to top. To find the
fractional part, repeatedly multiply with 2 and remove the part to the left of decimal
point. Read the removed part from top to bottom.
Example
(23.25)10=?
23/2=11, Remainder 1

11/2=5, Remainder 1

5/2=2, Remainder 1

2/2=1, Remainder 0

1/2=0, Remainder 1

Read from bottom to top : 10111

To find the fractional part, repeatedly multiply with 2 and remove the part to the
left of decimal point.
0.25 x 2=0.5 Remove 0
0,5 x 2=1.0 Remove 1
Read from top to bottom as : .01
Therefore (23.25)10=(10111.01)2

HEXADECIMAL NUMBER SYSTEM

Hexa-decimal number system uses 16 symbols (0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F) to

represent numbers. Hexadecimal number system will be as follows:
0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,10,11,12,…..1F,20,21,……FE,FF,100,……etc. The
positional values of hexadecimal numbers to the left of point are 160, 161, 162, 163
etc. and to the right of decimal point are 16-1, 16-2, 16-3 etc. Hexadecimal numbers
can be converted to equivalent decimal number by multiplying each digit with
its positional values and add them all.

Egs. 3B16=?

3B16 = 3×161+11×160 = 48+11 = 5910

Conversion from Decimal number to Hexadecimal number

Divide the part of the number to the left of decimal point repeatedly by 16 and
remove the remainder. Read the remainders from bottom to top. To find the
fractional part, repeatedly multiply with 16 and remove the part to the left of decimal
point. Read the removed part from top to bottom.

Egs. (732.36)10= ?

732/16=45 Remainder= 12 or C
45/16=2 Remainder = 13 or D
2/16 =0 Remainder =2
Reading from bottom to top : 2DC
0.36 x 16=5.76 Remove 5
0.76 x 16 = 12.16 Remove 12 which is equal to C in hexadecimal system.
0.16 x 16= 2.56 Remove 2
0.56 x 16 =8.96 Remove 8
0.96 x 16 = 15.36 Remove 15 which is equal to F in hexadecimal system
It continues indefinitely.
Read as 5C28F…..
(732.36)10=(2DC.5C28F)16

Binary To Octal and Hexadecimal Number

Binary number can be directly converted to Octal and Hexadecimal numbers.
To covert to Octal number, binary numbers may be grouped into a group of 3 bits
and each group is converted into a single Octal digit by multiplying each bit by its
position value within the group and add all these product within the group.
(101100100111.101)2=(101)(100)(100)(111).(101)=(5447.5)8

To covert to Hexadecimal number, binary numbers may be grouped into a

group of 4 bits and each group is converted into a single Hexadecimal digit by
multiplying each bit by its position value within the group and add all these product
within the group. (101100100111.1011)2=(1011) (0010) (0111) .(1010) =(B27B.A)16

LOGIC GATES
Logic gates are the basic building blocks used in digital circuits. Various logic gates
are discussed below.

AND Gate

Symbolic representation of AND gate is shown below.

A and B are the logical inputs and Y is the logical output. Inputs and output can take
any one of the possible values 0 or 1. These 0 and 1 may represent the possible
logical states like True or False, Yes or No etc. A can take the value 0 or 1. Similarly
B can take the values 0 or 1.
Output of AND gate, Y is defined as: Y=A AND B or Y=A.B
Dot represents the AND operation. In the case of AND gate Y will take the value 1
only when both the inputs A and B are 1. Otherwise, Y will take the value 0. Truth
table of AND gate is given below.

Truth Table
Input1 (A) Input 2 (B) Output Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

Three Input AND gates

AND gates with three inputs are also available. Its symbolic representation and truth
table are given below.
 Truth Table
Input1 (A) Input 2 (B) Input 3 (C) Output
Y=A.B.C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Output can be expressed as Y=A.B.C

OR Gate

Symbolic representation of OR gate is shown below.

Output of OR gate, Y is defined as: Y=A OR B or Y=A+B

‘+’ represents the OR operation. In the case of OR gate Y will take the value 1 if any
one of the inputs is 1. Otherwise, Y will take the value 0. Truth table of OR gate is
given below.
 Truth Table
Input1 (A) Input 2 (B) Output Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1

Three Input OR gates

AND gates with three inputs are also available. Its symbolic representation and truth
table are given below.

Truth Table
Input1 (A) Input 2 (B) Input 3 (C) Output
Y=A.B.C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Output can be expressed as Y=A+B+C

NOT Gate
Symbolic representation of OR gate is shown below.
It is a single input, single output gate. This gate inverts the input. If the
input is 0, output will be 1. Similarly, if the input is 1, output will be 0.
If the the input is the logical variable A, output Y can be represented as
𝑌 = 𝐴̅ . Truth table is given below.
Truth Table
Input A Output 𝒀 = 𝑨 ̅
0 1
1 0

NAND Gate

Symbolic representation of NAND gate is shown below. It is equivalent to an AND

gate followed by a NOT gate.

Equivalent circuit is shown below.

When both the inputs are 1, output will be zero. Otherwise, output will be 1. Truth
table is given below.
 Truth Table
Input1 (A) Input 2 (B) Output 𝒀 = ̅̅̅̅̅
𝑨. 𝑩
0 0 1
0 1 1
1 0 1
1 1 0
̅̅̅̅̅
Output can be expressed as 𝒀 = 𝑨. 𝑩
NOR Gate

Symbolic representation of NOR gate is shown below. It is equivalent to an OR gate

followed by a NOT gate.

Its equivalent circuit is shown below.

When both the inputs are 0, output will be 1. Otherwise, output will be 0. Truth table
is given below.

Truth Table
Input1 (A) Input 2 (B) Output 𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩
0 0 1
0 1 0
1 0 0
1 1 0

Output can be expressed as 𝒀 = ̅̅̅̅̅̅̅̅

𝑨+𝑩
Exclusive OR Gate
Symbolic representation of NOR gate is shown below.

Its output can be defined by the logical equation 𝑌 = 𝐴𝐵̅ + 𝐴̅𝐵

Its equivalent circuit is shown below.

Truth table of exclusive OR gate is shown below.

Truth Table
Input1 (A) Input 2 (B) Output 𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩
0 0 0
0 1 1
1 0 1
1 1 0

Exclusive NOR Gate

Symbolic representation of NOR gate is shown below. It is equivalent to an exclusive
OR gate followed by a NOT gate.
Its equivalent diagram is given below.

Output Y can be expressed as 𝑌 = 𝐴. 𝐵 + 𝐴̅. 𝐵̅

Truth table of exclusive NOR gate is shown below.

Truth Table

Input1 (A) Input 2 (B) Output 𝒀 = ̅̅̅̅̅̅̅̅

𝑨+𝑩
0 0 1
0 1 0
1 0 0
1 1 1
Logical variables used in the above logical gate circuits are called Boolean variables.
An expression relating Boolean variables is called a Boolean expression. Operators
relating these variables are AND ( . ), OR ( + ) and NOT operator.

Examples of Boolean expressions

Y=A+A𝐵̅

X=AB+C+A𝐶̅

Y=A𝐵̅ 𝐶 + 𝐴𝐵 + 𝐵𝐶
̅̅̅̅

Laws Boolean Algebra

1. Annulment Law – A term AND´ed with a “0” equals 0 or OR´ed with a “1” will

equal 1.

A.0=0

A+1=1

2. Identity Law – A term OR´ed with a “0” or AND´ed with a “1” will always

equal that term

A+0=A

A.1=A

3. Idempotent Law – An input that is AND´ed or OR´ed with itself is equal to that

input

a) A+A=A

Proof

If A=0, 0+0=0

If A=1, 1+1=1
 b) A.A=A

Proof

If A=0, 0.0=0

If A=1, 1.1=1

4.. Complement Law – A term AND´ed with its complement equals “0” and a term

OR´ed with its complement equals “1”.

a). A.𝐴̅ =0

If A=0, 0.1=0

If A=1, 1.0=0

b). A+𝐴̅ =1

If A=0, 0+1=1

If A=1, 1+0=1

5. Commutative Law – The order of application of two separate terms is not

important.

a). A.B=B.A

b). A+B=B+A

6. Double Negation Law – A term that is inverted twice is equal to the original

term.

𝐴̅ = 𝐴

7.. de Morgan´s Theorem – There are two “de Morgan´s” rules or theorems.

a). ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 = 𝐴̅. 𝐵̅

b). ̅̅̅̅̅
𝐴. 𝐵 = 𝐴̅ + 𝐵̅
 8. Distributive Law – This law permits the multiplying or factoring out of an

expression.

a). A(B+C)=A.B+A.C

b). A+(B.C)=(A+B).(A+C)

9. Absorption Law– This law enables a reduction in a complicated expression to

a simpler one by absorbing like terms.

a). A+(A.B)=A

b) A.(A+B)=A

10. Associative Law – This law allows the removal of brackets from an expression

and regrouping of the variables.

a).. A+(B+C)=(A+B)+C=A+B+C

b). A(B.C)=(A.B)C=A.B.C

1. Simplify F(A,B,C)=A′B+BC′+BC+AB′C′

Solution

A′B+BC′+BC+AB′C′= A′B+BC′+ BC′+BC+ BC′+AB′C′

A′B+BC′+BC+AB′C′= A′B+B(C+ C′)+ BC′+AB′C′

= A′B+B+ BC′+AB′C′ = A′B+B+ C′(B+ AB′)

But B+ AB′=(B+A).(B+ B′)=′(B+A).1=B+A

Therefore, A′B+B+ C′(B+ AB′)= A′B+B+ C′(B+ A)= (A′+ 1)B+ C′ B + C′ A

=B+ C′ B + C′ A=B(1+ C′)+ C′ A=B+ C′ A

2. Minimize the following Boolean expression using Boolean

 identities − F(A,B,C)=(A+B)(A+C)

Solution

(A+B)(A+C)=AA+AC+BA+BC=A+AC+AB+BC=A(1+C)+AB+BC

=A+ AB+BC=A(1+B)+BC=A+BC

3. Simplify the given Boolean expression: x’y’z +yz+ xz

Solution

x’y’z +yz+ xz=z( x’y’+y+ x)=z(y x’+y y’+x)=z(y x’+1+x)=z

4..Reduce the Boolean expression: A = XY + X(Y+Z) + Y(Y+Z)

Solution

XY + X(Y+Z) + Y(Y+Z)=XY+XY+XZ+YY+YZ=XY+XZ+Y+YZ

= XY+XZ+Y(1+Z) = XY+XZ+Y=Y+ XY+XZ=Y(1+X)+ XZ=Y+XZ

Implementation of Boolean Expression

1.. Realize Y=(A+B)(A+C)

2. Realize 𝐹 = 𝐴𝐵 + 𝐴𝐵̅
3. Realize 𝐹 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶 ′ + 𝐴′ 𝐵𝐶 ′

4. Realize 𝑭 = (𝑨 + 𝑩 + 𝑪) ∗ (𝑨′ + 𝑩′ + 𝑪) ∗ (𝑨 + 𝑩" + 𝑪)