Question Bank
Subject Name: VLSI TESTING
Part-A
Question
Unit -I
1. Define VLSI test process.
2. What is Automatic Test Equipment (ATE)?
3. List objectives of testing.
4. Define test economics.
5. What is product quality?
6. A lot has 10,000 chips, 9200 pass. Calculate yield.
7. If defect rate is 5% in 4000 chips, find defective chips.
8. Define cost of quality.
9. Explain relationship between yield and profit.
10. Define fault modelling.
11. What is yield?
12. Define defect density.
13. List types of fault models.
14. What is reliability in testing?
15. What is DPM (Defects per Million)?
16. Compare defect and fault.
17. Testing cost is ₹25 per chip for 8000 chips. Calculate total testing cost.
18. Evaluate importance of ATE in modern VLSI.
Unit -II
1. Define logic simulation.
2. What is fault simulation?
3. Define controllability.
4. Define observability.
5. What is combinational circuit testing?
6. A circuit has 5 inputs. Find exhaustive test vectors.
7. A circuit has 12 nodes. Calculate stuck-at faults.
8. Fault simulation detects 180/200 faults. Find coverage.
9. Analyze limitations of sequential testing.
10. Evaluate effectiveness of random testing.
11. What is sequential circuit testing?
12. Define fault coverage.
13. Define test vector.
14. List types of fault simulation.
15. What is ATPG?
16. 40 vectors require 3 cycles each. Calculate total cycles.
17. Compare logic and fault simulation.
18. Define SCOAP measures.
19. Suggest methods to improve testability.
20. Analyze impact of low observability.
Unit-III
1. Define memory testing.
2. What is March test?
3. Define IDDQ testing.
4. What is delay fault?
5. A memory has 2048 cells. How many write operations are required for full write test?
6. If propagation delay increases from 5ns to 8ns, calculate delay variation.
7. Define coupling fault in memory.
8. Explain importance of analog test bus.
9. Analyze need for mixed-signal testing.
10. Define mixed-signal testing.
11. What is DSP-based testing?
12. Define parametric fault.
13. What is stuck-open fault in memory?
14. Calculate number of address lines required for 4096 memory cells.
15. What is transition fault?
16. Compare stuck-at and delay fault.
17. Evaluate advantages of DSP-based testing.
18. Analyze impact of delay faults in high-speed circuits.
Unit-IV
1. Define Built-In Self-Test (BIST).
2. What is scan chain?
3. Define boundary scan.
4. What is JTAG?
5. A scan chain has 200 flip-flops. How many clock cycles are needed to shift one vector?
6. If 50 test vectors are applied to 150-bit scan chain, calculate total shift cycles.
7. Define memory BIST.
8. Suggest improvements in SoC test architecture.
9. Analyze core-based testing challenges.
10. Define fault dictionary.
11. What is diagnostic tree?
12. Define wrapper design in SoC.
13. What is random logic BIST?
14. What is test wrapper?
15. Compare BIST and external testing.
16. Explain role of analog test bus.
17. Analyze advantages of scan design.
18. Evaluate boundary scan test standard importance.
Unit-V
1. Define in-circuit testing (ICT).
2. What is unpowered short circuit test?
3. Define powered in-circuit test.
4. What is optical inspection?
5. If board has 150 nodes and 3% shorts, calculate number of shorted nodes.
6. A test fixture checks 200 boards/hour. How many boards in 5 hours?
7. Define bed-of-nails tester.
8. Evaluate advantages of X-ray inspection.
9. Define X-ray inspection.
10. What is functional block testing?
11. Define boundary scan in PCB.
12. What is analog ICT?
13. What is isolation test?
14. Compare optical and X-ray inspection.
15. Define mixed-signal ICT.
16. Explain importance of functional testing.
17. Evaluate role of ICT in quality assurance.
Part-B
Unit-I
1. Explain complete VLSI testing flow including ATE.
2. A batch of 20,000 chips has 3% defects. Testing detects 95%. Calculate remaining defective
chips and analyze impact.
3. Compare various fault models and justify selection.
a. Analyze relationship between testing and reliability.
b. Evaluate economic impact of improved fault coverage.
4. Discuss fault modelling techniques in detail.
5. A company produces 5000 chips/month with 90% yield. Calculate good chips and analyze
profit impact.
a. Discuss test economics and cost trade-offs.
b. Compare stuck-at and bridging fault models.
6. Evaluate strategies to reduce testing cost while maintaining quality.
Unit-II
1. Explain complete combinational circuit test generation.
2. A circuit has 8 inputs and 20 faults. Random testing detects 75%. Calculate undetected faults
and analyze efficiency.
3. Evaluate fault simulation algorithms.
4. Evaluate testability measures for improving circuit reliability.
5. Explain sequential circuit testing methods.
6. Analyze controllability and observability improvement methods.
7. Develop ATPG algorithm for digital circuits.
8. Explain logic and fault simulation with algorithms and applications.
Unit-III
1. Explain complete memory testing techniques with fault coverage analysis.
2. Develop DSP-based test architecture for mixed-signal IC.
3. Analyze IDDQ testing limitations in nanometer technologies.
4. Discuss delay testing and transition fault detection methods.
5. Evaluate model-based analog test techniques.
6. Design a testing strategy for mixed-signal IC.
Unit-IV
1. Describe boundary scan test standard.
2. Evaluate DFT techniques in SoC testing.
3. Discuss fault dictionary and diagnostic tree.
4. Explain complete BIST architecture with diagram.
5. Compare random logic BIST and memory BIST.
6. Evaluate advanced diagnostic methodology for fault isolation.
Unit-V
1. Explain complete in-circuit testing methodology.
2. Compare ICT and functional testing.
3. Evaluate different board-level testing strategies.
4. Discuss optical and X-ray inspection in detail.
5. Analyze functional block design of ICT equipment.
6. Design ICT strategy for mixed-signal PCB.