Module: 6.

Digital System Design Implementation

SYLLABUS:
Serial Binary Adder, Simple Sequence Detector, Traffic Light Control System, Vending Machine
Controller, ALU Design.

Serial Binary Adder

A Serial Binary Adder is a binary adder circuit that is used to add binary numbers in serial
form. In the serial adder, the two binary numbers to be added serially are stored in shift
registers A and B. The logic circuit diagram of the serial binary adder is shown in the figure
below

The function of different elements of the serial adder:

Full Adder: A full adder is a digital combinational logic circuit that adds three binary digits
and produces two output bits, i.e., the sum bit and the carry bit.
Shift Register: A group of flip-flops that can store several bits of data is called a register. The
content of the register can be moved or shifted either serially or parallelly such registers are
called shift registers. In a serial binary adder, two shift registers are used, where one is for
storing the augend bit, and the other is for storing the added bit of the binary number.
D Flip-Flop: In a serial adder, the D flip-flop is used to store the carry output bit. The output
of this D flip-flop is used as the carry input in the next stage of addition
Operation: In the serial binary adder circuit, the binary digits (bits) are added one pair at a
time using a full-adder circuit. The carry generated from the full adder is transferred to a D
flip-flop. Thus, the output of this D flip-flop is then used as the carry input for the next pair of
significant bits. The sum bit S is transferred to a third shift register.

Simple Sequence Detector

A sequence detector is a sequential digital circuit that can be used to detect whether a given
sequence of bits has been received or not. The sequence detector produces an output ‘1’,
whenever it detects the desired input sequence and ‘0’ for other cases. There are two types of
sequence detectors:
 1. Sequence Detector with non-overlapping input sequence
2. Sequence Detector with over-lapping input sequence.
Step-by-Step Design Procedure:
1. Draw the state diagram of the sequence detector based on the required sequence.
2. Construct the State Table from the State Diagram of the sequence detector
3. State Minimization & State Assignment.
4. Determine the number of flip-flops needed by using the relation 2 n ≥ number of states.
Where ‘n’ is no. of flip-flops.
5. Construct the Transition table of the sequence detector.
6. Find flip-flop input expressions and the output expression of the sequence detector.
7. Draw the Logic Diagram of the sequence detector.
Example: Design a non-overlapping 101 Mealy sequence detector using D flipflops.
Step 1: Design the State Diagram of the Sequence Detector 101.

Step 2: Construct the State Table from the State Diagram

Present Next State Output

State X=0 X=1 X=0 X=1
A A B 0 0
B C B 0 0
C A A 0 1

Step 3: State Minimization & State Assignment for the states in the state table
The state table does not have equivalent states, so there is no possibility for state
minimization.
A = 00; B = 01; and C = 10; Reconstruction State Table after State Assessment
Present Next State Output
State X=0 X=1 X=0 X=1
00 00 01 0 0
01 10 01 0 0
 10 00 00 0 1
Step 4: Determine no. of Flip-flops required by using the relation 2 n≥ No. of states.
Where ‘n’ is no. of flipflops.
22 ≥ 3; No. of flipflops = 2 (A & B)
Step 5: Construct the Transition Table of the Sequence Detector.

Present State Present Input Next State Flip-flop inputs Output

QA QB X QA+1 QB+1 DA DB Z
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 0 0 0 0 1
1 1 0 d d d d d
1 1 1 d d d d d

Step 6: Find flip-flop input expressions and the output expression of the sequence
detector.
DA (QA, QB, X) = ∑m (2) + ∑d (6, 7); DB (QA, QB, X) = ∑m (1, 3) + ∑d (6, 7);
Z (QA, QB, X) = ∑m (5) + ∑d (6, 7)

Step 7: Draw the Logic Diagram of the Sequence Detector

Traffic Light Control System
A Traffic Light Control System is an example of a Finite State Machine (FSM) used in
digital system design. It controls vehicle movement at road intersections using sequential
logic. A Mealy-type Finite State Machine (FSM) for a traffic light controller produces
outputs that depend on the current state and the input (for example, a timer signal or
vehicle sensor). The system can be designed with D flip-flops.
Inputs and Outputs
Input X: Timer: X = 0; Continue current light phase; X = 1: Change to next phase.
Output Z: the output Z = 1 when three consecutive states input X = 1, (i.e. once the cycle
completes.)
States of the Controller
There are four states: S0 = Main road Green, Side road Red
S1 = Main road Yellow, Side road Red
S2 = Main road Red, Side road Green
S3 = Main road Red, Side road Yellow
State Diagram

State Assignment
S0 = 00; S1 = 01; S2 = 10; S3 = 11
State Table

Present
Next State
State Present
(NS) Output (Z)
(PS) Input (X)
QA+1QB+1
QAQB
00 0 00 0
00 1 01 0
 01 0 01 0
01 1 10 0
10 0 10 0
10 1 11 0
11 0 11 0
11 1 00 1

Excitation Table of the Traffic Light Controller

Present Flip-flops
Next State
State Present inputs Output
(NS)
(PS) Input (X) DADB (Z)
QA+1QB+1
QAQB
00 0 00 00 0
00 1 01 01 0
01 0 01 01 0
01 1 10 10 0
10 0 10 10 0
10 1 11 11 0
11 0 11 11 0
11 1 00 00 1

Find Flipflop Input Expressions

Logic Diagram
Vending Machine Controller
Design a vending machine that dispenses multiple products depending on the selection
and amount inserted.
Assumptions:
The machine sells two products: Product A – ₹10; Product B – ₹15
Coins accepted: ₹5 coin; ₹10 coin
The controller dispenses the product once enough amount is inserted, and returns change if
necessary. This controller is implemented using a Mealy Finite State Machine, where outputs
depend on the present state and input.
Inputs and outputs
Inputs
X1 = Rs. 5 coin inserted; X2 = Rs. 10 coin inserted;
S: Product Selection 0 = Product A; 1 = Product B
Outputs
DA: Dispense Product A; DB: Dispense Product B

States of the Machine

States represent the amount accumulated

State Amount Encoding

S0 Rs. 0 00
S5 Rs. 5 01
S10 Rs. 10 10
State Transition Table

Present State Input Coin Selectio Next State Output

n
S0 ₹5 --- S5 ---
S0 ₹10 A S0 DA
S0 ₹10 B S10 ---
 S5 ₹5 A S0 DA
S5 ₹5 B S10 ---
S5 ₹10 A S0 DA+C
S5 ₹10 B S0 DB
S10 ₹5 B S0 DB
S10 ₹10 B S0 DB+C
State Diagram

ALU Design
An Arithmetic Logic Unit (ALU) is a multi-operational, combinational digital logic circuit.
It can perform a set of basic arithmetic operations and a set of logic operations. The ALU has
several selection lines to select a particular operation. The block diagram of a 4-bit ALU is
shown in the figure below.

The inputs A and B are two 4-bit numbers, F is the 4-bit output of the ALU. The Mode-select
input S2 distinguishes between arithmetic and logic operations. The Function-select inputs S1
and S0 specify the particular arithmetic or logic operation to be generated. The input carry
Cin in the least significant position of an ALU is quite often used as a fourth selection
variable that can double the number of arithmetic operations.
The design of a typical ALU will be carried out in three stages.
1. Design of the Arithmetic Section
2. Design of Logic Section
3. The arithmetic section will be modified so that it can perform both arithmetic and logic
operations.
Design of an Arithmetic Circuit
The basic component of the arithmetic section of an ALU is a parallel adder. A parallel adder
is constructed with several full-adder circuits connected in cascade. By controlling the data
inputs to the parallel adder, it is possible to obtain different types of arithmetic operations.
The input carry Cin goes to the full-adder circuit in the least significant bit position. The
output carry Cout comes from the full-adder circuit in the most significant bit position. Input
A was directly applied to one input of the full-adder, and the other input to the full-adder is B,
which is applied through the MUX circuit. Based on the input carry Cin and selection lines
S1 and S0 of the MUX, the circuit will decide the operation performed by the arithmetic
circuit.
The functional table of the arithmetic circuit is shown below.

Design of Logic Circuit

The logic microoperations manipulate the bits of the operands separately and treat each bit as
a binary variable. All logic operations can be obtained by means of AND, OR, and NOT
operations, it may be more convenient to employ a logic circuit with just these operations.
For three operations, we need two selection variables. But two selection lines can select
among four logic operations, so we also choose the XOR function for the logic circuit to be
designed.
The logic circuit and its function table are shown in the figure below. The diagram shows one
typical stage designated by subscript i. The circuit must be repeated n times for an n-bit logic
circuit. The four gates generate the four logic operations OR, XOR, AND, and NOT. The two
selection variables in the multiplexer select one of the gates for the output.

The logic circuit can be combined with the arithmetic circuit to produce an arithmetic logic
unit. Selection variables S1 and S0 can be made common to both selections, provided we use
a third selection variable, S2, to differentiate between the two. The output of the logic and
arithmetic circuits in each stage goes through a multiplexer with selection variable S2. When
S2 = 0, the arithmetic output is selected, but when S2 = 1, the logic output is selected.
Combining Logic and Arithmetic Circuits

The function table for the ALU is shown in below