Question 11
Latch: Level-sensitive memory el ement. Output follows inputs while
enable is active.
Flip-Flop: Edge-triggered memory element. Output changes only on
clock edge.
SR Flip-Flop
Truth Table
S R Qn+1 DESCRIPTION
0 0 Q HOLD
0 1 0 RESERT
1 0 1 SET
1 1 - INVALID
Characteristic Equation: 𝑄 + = 𝑆 + 𝑄 ⋅ 𝑅‾
Excitation Table:
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
QUESTION 12
S-R Flip-Flop
This is the simplest flip-flop circuit. It has a set input (S) and a reset
input (R). When in this circuit when S is set as active, the output Q
would be high and the Q' will be low. If R is set to active, then the
output Q is low and the Q' is high. Once the outputs are established,
the results of the circuit are maintained until S or R get changed, or the
power is turned off.
Characteristics
Q(t+1)=S+R′Q(t)
S R Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
Characteristics Equation :Q(t+1)=S+R′Q(t)
J-K Flip-Flop
Because of the invalid state corresponding to S=R=1 in the SR flip-
flop, there is a need of another flip-flop. The JK flip-flop operates with
only positive or negative clock transitions. The operation of the JK flip-
flop is similar to the SR flip-flop. When the input J and K are different
then the output Q takes the value of J at the next clock edge. When J
and K both are low then NO change occurs at the output. If both J and
K are high, then at the clock edge, the output will toggle from one state
to the other
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Characteristics Equation
Q(t+1)=jkQ(t)′+K′Q(t)
D Flip-Flop
In a D flip-flop, the output can only be changed at positive or negative
clock transitions, and when the inputs changed at other times, the
output will remain unaffected. The D flip-flops are generally used for
shift-registers and counters. The change in output state of D flip-flop
depends upon the active transition of clock. The output (Q) is same as
input and changes only at active transition of clock
Characteristics Equation
Q(t+1)=D
T Flip-Flop
A T flip-flop (Toggle Flip-flop) is a simplified version of JK flip-flop. The
T flop is obtained by connecting the J and K inputs together. The flip-
flop has one input terminal and clock input. These flip-flops are said
to be T flip-flops because of their ability to toggle the input state.
Toggle flip-flops are mostly used in counters.
Characteristics Equation
Q(t+1)=T′Q(t)+TQ(t)′=T⊕Q(t)
QUESTION 14
Encoder
An encoder is a digital circuit that converts a set of binary inputs into
unique binary code
truth table
INPUT OUTPUT
I3 I2 I1 I0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
Decoder is a combinational logic circuit that converts coded n-bit
binary inputs into 2n-bit outputs.
Truth table
INPUT OUTPUT
A B 0 1 2 3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Multiplexer is a combination that has many data inputs and a single
output, depending on control or select inputs
Truth table
SO I0 I1 Y
0 0 X 0
0 1 X 1
1 X 0 0
1 X 1 1
demultiplexer is digital information [Link] takes input from the
source and also converts the data to transmit towards various sources
Truth table
input Outputs
S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 0
0 1 0 1 1 0
1 0 0 0 0 0
1 1 1 0 0 0
NAME: REAGAN SHAWA
STUDENT NUMBER: 2022101514
COURSE NAME: COMPUTER ARCHITECTURE
COURSE CODE: BOCS 2020
MODE OF STUDY: DISTANCE LEARNING
ASSIGNMENT NUMBER: TEST 1
LECTURE NAME:MR BWALYA B
EMAIL ADDRESS: [Link]@[Link]
PHONE NUMBER: 0978754671
QUESTION 1 (a)
[Link] language is important in Computer Science because it
provides direct control over the hardware. It allows programmers to
access CPU registers, memory addresses, and machine instructions,
making it essential for writing device drivers, embedded systems, and
operating system kernels. It also helps students understand the
relationship between high-level languages and machine code, thereby
strengthening knowledge of computer architecture.
[Link] language should be avoided for general application
development because it is complex, error‑prone, and
time‑consuming. It is architecture‑dependent, lacks portability, and is
difficult to maintain compared to high‑level languages such as C,
Java, or Python. For large‑scale applications, high‑level languages are
preferred due to faster development, readability, and built‑in libraries.
QUESTION 1(b)
section .data
num1 db 5 ; first number
num2 db 7 ; second number
result db 0 ; storage for result
section .text
global _start
start:
mov al, [num1] ; load num1 into AL
add al, [num2] ; add num2 to AL
mov [result], al ; store result in memory
mov eax, 60 ; syscall: exit
xor edi, edi ; status 0
syscall
QUESTION 2
Direct Memory Access (DMA): DMA is a technique that allows data
transfer directly between I/O devices and main memory without
continuous CPU involvement. It reduces CPU overhead and increases
system efficiency. For example, data can be transferred from disk to
RAM using a DMA controller while the CPU executes other
instructions.
Interrupts: Interrupts are signals sent to the CPU to indicate that an
event requires immediate attention. They may be hardware interrupts
(e.g., keyboard input, timer) or software interrupts (e.g., system calls).
Interrupts enable asynchronous event handling and multitasking.
Crucial Role: DMA and interrupts work together to improve
performance. DMA handles bulk data transfer in the background,
while interrupts notify the CPU when the transfer is complete. This
combination ensures efficient I/O operations, reduced CPU load, and
faster device communication. For example, in networking, DMA
transfers packets into memory and interrupts signal the CPU to
process them.
QUESTION 3
Memory Types and Mapping Procedures
1. Cache Memory: Small, high‑speed memory located close to the
CPU, Stores frequently accessed instructions/data to reduce average
access time.
• Mapping procedures: Direct Mapping: Each block maps to one
cache line.
• Associative Mapping: Any block can be placed in any line.
• Set‑Associative Mapping: A block maps to a set of lines.
2. Virtual Memory: Technique that gives programs the illusion of large
continuous memory using disk storage.
• Implemented through paging or segmentation.
• Allows execution of programs larger than physical RAM.
3. Auxiliary Memory: Non‑volatile storage such as hard disks, SSDs,
and [Link] for permanent data storage, slower than RAM.
4. Associative Memory (Content‑Addressable Memory):• Memory
accessed by content rather than [Link] in cache lookups and
Translation Lookaside Buffers (TLBs).
• Compares input tags with stored tags simultaneously.