SCHOOL OF ELECTRICAL ENGINEERING
BAEEE201- Digital Electronics
Module 3 – Sequential logic circuit
By,
[Link]
Associate Professor /SELECT
Logic circuit
• Combinational logic circuit
• Outputs at any instant of time are entirely dependent
upon the inputs present at that time.
• Sequential logic circuit
• Combinational logic circuit with memory
elements
• Memory elements are connected to form a
feedback path.
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Block diagram of sequential logic diagram
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• Types of sequential logic circuits
• Asynchronous sequential circuit
• Depends on the order in which its input signal
change and can be affected at any instant of time
• Synchronous sequential circuit
• Defined from the knowledge of its signals at
discrete instants of time
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Synchronous clocked sequential circuit
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S R Latch with NOR gates
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SR Latch with NAND gates
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SR Latch with control input
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D Latch
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Q1. If the S ‘ and R ‘ waveforms shown in Figure a are applied to the
inputs of the latch shown in Figure b. determine the waveform that
will be observed on the Q output. Assume that Q is initially LOW.
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• Q2. Determine the Q output waveform if the inputs shown in
Figure (a) are applied to a gated S-R latch that is initially
RESET.
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Level and edge triggering
• Level triggering
• The output state is allowed to change according to
inputs(s) when active level is maintained at the enable
input.
• Positive level triggering
• Negative level triggering
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Negative level triggered SR latch
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• Edge triggering
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Clocked SR Flip-flop
• Positive edge triggered SR flip flop
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• Negative edge triggered SR flip flop
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Clocked D Flip-flop
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Negative edge triggered D flip-flop
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Clocked JK Flip-flop
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Clocked T flip flop
• T flip flop is also known as Toggle –Flip flop.
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Asynchronous or Direct inputs
• SR,D,JK,T – the inputs are called synchronous inputs - data on
these inputs are transferred to the FF output only on the
triggering edge of the CP.
• FF available as IC package, has special inputs for setting and
clearing the FF.
• Preset or Direct Set
• Clear or Direct reset
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• Q3. Determine the Q output waveform if the inputs shown in
Figure (a) are applied to a gated D latch, which is initially RESET.
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• Q 4. Determine the Q and Q’ output waveforms of the flip-flop in
Figure (a) for the D and CLK inputs in Figure (a1). Assume that the
positive edge-triggered flip-flop is initially RESET.
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Q5. For the positive edge-triggered D flip-flop with preset and
clear inputs in Figure ,determine the Q output for the inputs shown in
the timing diagram in part (a) if Q is initially LOW.
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IC74HC112
The 74HC112 dual J-K flip-flop has two identical flip-flops that
are negative edge-triggered and have active-LOW synchronous preset and clear
inputs. The logic symbols are shown in Figure.
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Flip flop excitation tables
• Excitation table lists the required inputs for a given change of
state.
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J K Flip flop – excitation table
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Thank You !
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