國立清華大學 電機工程學系碩博士班
106 學年度第一學期
EE-6250 超大型積體電路測試 VLSI Testing
期末考 Jan. 11, 2018 (總分 100 分)
(Closed-Book Examination)
參考解答
1. (10%) Answer the following questions.
(a) Define the aliasing condition introduced by test response compaction? (5%)
An aliasing condition occurs when a faulty response vector is compacted into a fault-free vector.
(b) Give one reason why fault diagnosis is important for ICs that fail the manufacturing test. (5%)
to identify the defects, so as to improve the yield, or to identify defect-prone layout pattern to guide the
DFM rules. (Any of the above answers will be considered correct).
2. (15%) Answer the following questions related to LFSR.
(a) There are two basic requirements to produce (2n-1) pseudo random patterns using a LFSR. One of them is to
choose a LFSR with a primitive (or irreducible) polynomial. Name the other requirement. (5%)
Use non-zero SEED
(b) Consider the design of a LFSR generating a maximum-length sequence of random patterns. The
characteristic polynomial of such a LFSR shown below is represented as p(x) = x4+ x1+ 1, where x
corresponds to a delay element in the circuit structure, meaning the "delay of one clock cycle". (Note: D1,
D2, D3, D4 in the figure denotes 4 flip-flops). Try to generalize it and show the out-tap structure for a 5-
stage maximum-length LFSR with a characteristic polynomial as p(x)=x5+x2+ 1. (Hint: This is an LFSR with
a recursive formula as z = D5(z)+D2(z). (5%)
(c) Convert the out-tap structure into its in-tap version. (Hint: signal flow analysis will help). (5%)
+
z D1 D2 D3 D4 D5
D(z) D2(z) D3(z) D4(z) D5(z)
(a) out-tap structure for p(x)=x5+x2+ 1
z D1 D2 D3 + D4 D5
(b) in-tap structure for p(x)=x5+x2+ 1
3. (15%) Answer the following questions related to IEEE-1149.1.
(a) There is a TAP controller that regulates the boundary test procedure. During a boundary test session, which
IEEE-1149.1 input signal is used as the input of the finite state machine of this TAP controller? (5%)
TMS
(b) There are two basic registers required by the IEEE-1149.1 standard. One is “boundary scan register”. What
is the other? (5%)
1-bit bypass register
(c) A Boundary Scan Cell in IEEE-1149.1 standard is controlled by three important control signals, namely
1
ClockDR, ShiftDR, and UpdateDR. Which one controls the output flip-flop of each boundary scan cell? (5%)
UpdateDR
4. (15%) Answer the following questions related to test compression.
(a) Golomb code is an improved zero-run-length code for test compression. Find the original test sub-pattern
represented by a Golomb code of "11011", assuming that there are two tail bits. (Hint: For example "1001"
denotes the 2nd pattern in group A2 with the prefix of '10', which corresponds an original sub-pattern of
"000001".) (5%)
-> "11011" is the Golomb code the 4th pattern in group A3, which is "000000000001" ('1' trailing 11 '0s')
(b) There are three major types of test compression, including code-based compression and linear compression.
What is the other type? (Simply give the name.) (5%)
Broadcasting scan
(c) In the following linear decompression structure, represent Z6 in terms of {X1, X2,…, X10}. Note the {X1, X2,
X3, X4} are the seeds of the shift register before the input test pattern bits {X5, X6, X7, X8, X9, X10} are applied.
(5%).
Z6 = X1 ⊕ X4
5. (15%) Answer the following questions related to the Pulse-Vanishing Test (PV-Test).
(a) A short pulse is used as the test stimuli and applied to an interconnect under test by the PV-Test. Explain
what condition is used as the fault detection criterion at the receiver end of the interconnect? (5%)
There is a delay fault associated with the interconnect if there is no pulse signal at the receiver end (or
the pulse vanishes when it travels throguh the interconnect).
(b) PV-Test is a delay test scheme that checks if the propagation delay across an interconnect exceeds a delay
threshold. When we want to set a more tolerant threshold (i.e., a larger delay budget), then how should we do?
Increase the pulse-width of the test pulse (since it is related to the delay threshold).
(c) Give the logic diagram of the Boundary-Cell-Compatible Capture Cell (attached to the termination end of the
interconnect under test) for the PV-test. (Hint: your logic circuit will contain 4 MUXes and 2 Flip-Flops.
Mark clearly the input pin where the termination end of the interconnect under test should be connected to.)
Check out the lecture notes on ch10-17.
6. (15%) Answer the following questions about VOT-based oscillation test.
(a) Show the transistor schematic of a VOT (Variable Output Threshold) inverter. (5%) Check out the
lecture notes on ch10-29.
(b) Construct a ring oscillator for 2 interconnects under test, consisting of the following elements: {2 tri-state
inverters used as the interconnect drivers, 2 VOT inverters, 2 MUXes, and 1 NAND gate). Note that this
ring oscillator should be able to support the VOT-based oscillation test for bridging faults as discussed in
class. (5%) Check out the lecture notes on ch10-36.
(c) If the oscillation period is denoted as TREF when the 2 VOT inverters are both in the normal mode, and
denoted as TST1 when the VOT inverter of the 1st interconnect is switched to the Schmitt-Trigger mode.
2
Then, what formula (in terms of TREF and TST1) is positively correlated to the delay across the 1st
interconnect. (5%) (TST1 - TREF)
7. (15%) Consider the diagnosis of a combinational failing chip with five outputs. Under a particular test vector v,
the output response is (1,1,1,0,0) for the circuit model, and (0,0,1,0,1) for the failing chip under diagnosis.
(a) What is the number of mismatched outputs under this test vector? 3
(b) An internal signal f is being checked for a fault location candidate by the inject-and-evaluate paradigm.
If the value of signal f is ‘1’ when test vector v is applied to the circuit. What operation should be done
before the event-driven simulation is performed? (5%) flip the value at signal f to ‘0’
(c) If the output response after the inject-and-evaluate process is (0,0,1,0,1), then is test vector v a curable
vector of signal f? (5%) YES