國立清華大學 電機工程學系碩博士班

104 學年度第一學期
EE-6250 超大型積體電路測試 VLSI Testing
期末考 Jan. 13, 2016 (總分 100 分)
(Closed-Book Examination)
REFERENCE ANSWERS
1. (20%) Answer the following questions.
(a) There are two basic requirements to produce (2n-1) pseudo random patterns using an n-stage LFSR. One of
them is to choose a LFSR with a primitive (or irreducible) polynomial. Name the other requirement. (5%)
-> Start the LSFR in a seed that is NOT all-zero.
(b) The reliability of a semiconductor device is often characterized by a "bathtub curve", with the entire
lifetime divided into three stages, including "infant mortality stage", "normal lifetime stage", and a third
stage. Give a name for the third stage and explain what it means briefly. (5%)
-> Wear-out stage, in which the failure rate increases over time gradually.
(c) There is a TAP controller that regulates the boundary test procedure. During a boundary test session, which
IEEE-1149.1 input signal is used as the input of the finite state machine of this TAP controller. (5%)
-> TMS (standing for Test Mode Select)

(d) Golomb code is an improved zero-run-length code for test compression. Find the original test sub-pattern
represented by a Golomb code of "1011", assuming that there are two tail bits. (Hint: For example "1001"
denotes the 2nd pattern in group A2 with the prefix of '10', which corresponds an original sub-pattern of
"000001".) (5%)
-> "1011" is the Golomb code for "00000001"

2. (10%) Consider the design of an LFSR generating a maximum-length sequence of random patterns. The
characteristic polynomial of such a LFSR shown below is represented as p(x) = x4+ x1+ 1, where x corresponds
to a delay element in the circuit structure, meaning the "delay of one clock cycle". (Note: D1, D2, D3, D4 in the
figure denotes 4 flip-flops). (5%)
(a) Try to generalize it and show the out-tap structure for a 5-stage maximum-length LFSR with a
characteristic polynomial as p(x)=x5+x2+ 1. (Hint: This is an LFSR with a recursive formula as z = D5(z)+D2(z).)
(b) Convert the out-tap structure into its in-tap version. (Hint: signal flow analysis will help). (5%)

z D1 D2 D3 D4 D5
D(z) D2(z) D3(z) D4(z) D5(z)
(a) out-tap structure for p(x)=x5+x2+ 1

z D1 D2 D3 + D4 D5

(b) in-tap structure for p(x)=x5+x2+ 1

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3. (10%) Consider a test pattern split into 5 sub-patterns (one for each of 5 scan chains): {Chain1=(101XX),
Chain2=(XX10X), Chain3=(XXX0X), Chain4=(0X0X1), Chain5=(XX01X)}.
(a) Draw a compatibility graph to describe the compatibility relations among these five sub-patterns. (5%)
(b) If the broadcasting scan test is applied, then we can use only two common sub-patterns to fill out all 5 scan
chains for this particular test pattern. If one of the common sub-pattern is (1010X), what is the other? (5%)
-> (0X011)

Chain 1 Chain 4

Chain 2 Chain 3 Chain 5

(a) Compatibility Graph

(b) 2nd common sub-pattern for Chain 4 and Chain 5 is (0X011)

4. (10%) Draw the circuit structure of a Boundary Scan Cell (BSC) defined in IEEE Std. 1149.1, using two flip-
flops and two multiplexers. Label clearly the following input signals {IN, SI, Test_Mode, ClockDR, ShiftDR,
UpdateDR} and output signals {SO, OUT}, where signals SI stands for scan-input, and SO stands for scan-
output.

5. (10%) Consider the Huffman encoding for a set of test patterns containing 5 symbols {A=0001, B=0010,
C=0100, D=1000, E=1111} with their occurrence frequencies shown in the table below.
(a) Construct a binary tree for the Hoffman encoding, with the accumulated number of occurrences labeled in
each node. (5%)
(b) Before the Hoffman encoding, the original number of bits to represent this set of test patterns is
(10+20+30+40+100)* 4 = 800. What is the total number of bits after the Hoffman encoding? (5%) -> 390

SOUT
IN 0
MUX OUT
1
0
MUX
1 1D Q 1D Q

QA QB Test_Mode
SIN ShiftDR
ClockDR UpdateDR

2
 200
Reference 0
ANSWER 100
0
60 1
0
1
30
1
0 1
10 20 30 40 100
4 bits 4 bits 3 bits 2 bits 1 bits
A B C D E

Total number of bits (after Hoffman Encoding)

6. (10%) Answer the following questions about pulse-vanishing test for an interconnect.
(a) Draw a primitive launch cell using only 1 D-type flip-flop, 1 multiplexer, and 1 inverter. The input
signals include {IN, S, Test_Mode, TP}, where IN denotes the functional input, S denotes a signal which
resets the flip-flop to '0' before the test when asserted, Test_Mode determines if the circuit is in the
functional mode or in the test mode, and TP denotes a two-pulse signal coming in from a remote
controller. The output signal is {OUT} which is connected to the input of the interconnect driver. (5%)
(b) In this test method, what should we do if we want to relax the test threshold? For example, if we want to
catch a delay fault making an interconnect delay larger than 10ns, instead of 1ns as discussed in class,
then what should we do?). Simply describe the general principle briefly. (5%)
-> Use a pulse signal with a larger pulse width (e.g., one with a pulse-width of 10ns).
Test_Mode

IN 0
OUT
D Q 1
FF
R

S
TP
(a) Launch cell

7. (15%) Consider the transition fault testing in a scan test environment. It requires a 2-pattern test,
namely (v1, v2). The entire test application is executed in three stages: (1) scan-in v1, (2) launch-v2-and-
capture-the-response, (3) scan-out response vector.
(a) There are two types of test application (for launching v2), popularly known as LoS and LoC. Show
the complete names of these two acronyms. (5%)
-> LoS for "Launch-off-Shifting", LoC for "Launch-off-Capture"
(b) If using LoS, then there is a special timing constraint for scan clock signal (TCK) and scan enable
signal (SE) during the stage of "launch-v2-and-capture". Draw the waveforms of these two signals
to illustrate the above timing constraint. (5%)
(c) If LoS is used, and v1: (y1, y2, y3) = (1, 0, 0), where y1, y2, and y3 are three PPI’s (Pseudo-Primary
Inputs). Let SI (Scan-Input) is stable at ‘0’, derive v2, assuming that the scan chain order is SI
y1y2y3SO. (5%)
-> v2: (y1, y2, y3) = (0, 1, 0)
Shift Window Launch Window Shift Window

V1 V2
S1 C1
TCK … …

d
SE

Answer(b): signal SE falls between the two rising edges of TCK

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8. (15%) Answer the following questions about transition-time monitoring schemes discussed in class for
interconnects.
(a) Explain what "non-intrusive monitoring" means briefly. (5%)
-> The monitor can work even when the IC is operating with its designated functional task.
(b) Draw a logic circuit, namely "TT2PW" in the class, that can convert the transition-time at an observation
point into a pulse signal, while the pulse-width is sensitively correlated to the transition time being
observed. Use 1 Schmitt-Trigger inverter, 1 normal inverter, and 1 XOR gate. (5%)
(c) How can you modify the circuit so that it responds only to the fall-time of the signal at an observation
point while ignoring the rise-time. Show the modified circuit. (5%).

Schmitt-Trigger

(b) TT2PW stage

Schmitt-Trigger

(c) Fall-Time to PW Converter