國立清華大學 電機工程學系碩博士班
105 學年度第一學期
EE-6250 超大型積體電路測試 VLSI Testing
期末考 Jan. 12, 2017 (總分 100 分)
(Closed-Book Examination)
REFERENCE ANSWERS
1. (10%) Answer the following questions.
(a) The reliability of a semiconductor device is often characterized by a "bathtub curve", with the entire
lifetime divided into three stages, including "infant mortality stage", "normal lifetime stage", and a third
stage. Give a name for the third stage and explain what it means briefly. (5%)
-> Wear-out stage, in which the failure rate increases over time gradually.
(b) Golomb code is an improved zero-run-length code for test compression. Find the original test sub-pattern
represented by a Golomb code of "1011", assuming that there are two tail bits. (Hint: For example "1001"
denotes the 2nd pattern in group A2 with the prefix of '10', which corresponds an original sub-pattern of
"000001".) (5%)
-> "1011" is the Golomb code for "00000001"
2. (10%) Consider the Huffman encoding for a set of test patterns containing 5 symbols {A=0001, B=0010,
C=0100, D=1000, E=1111} with their numbers of occurrences in a set of test patterns as shown in the table
below.
(a) Construct a binary tree for the Hoffman encoding, with the accumulated number of occurrences labeled in
each node. (5%)
(b) Before the Hoffman encoding, the original number of bits to represent this set of test patterns is
(20+120+100+10+30)* 4 = 1120. What is the total number of bits after the Hoffman encoding? (5%) ->
530
280
Reference 0
ANSWER 160
0
60 1
0
1
30
1
0 1
10 20 30 100 120
4 bits 4 bits 3 bits 2 bits 1 bits
D A E C B
Total number of bits (after Hoffman Encoding)
= 4*10 + 4*20 + 3*30 + 2*100 + 1*120 = 530
3. (10%) Answer the following questions about pulse-vanishing test (PV-test) for an interconnect.
(a) What is the test stimulus in PV-test? What symptom at the termination end of an interconnect is used as
1
an indicator of the presence of a delay fault somewhere along the interconnect under test? (5%) A
pulse signal (with a short pulse-width). There is delay fault when the pulse vanishes.
(b) Design a basic capture cell, consisting of only 1 flip-flop, attached to the termination end of an
interconnect. What initial condition is required before a test session for this capture cell? (5%) Check
out the textbook.
4. (10%) Answer the following questions about Time-to-Digital Converter Design.
(a) Design a basic coarse pulse-shrinking cell that consists of only 1 delay element and an AND gate. (5%)
(b) Design a basic fine pulse-shrinking cell that consists of only 2 inverters and one Flip-Flop. Note that this cell
shrinks the pulse-width of an incoming pulse signal slightly (e.g., 5ps). (5%)
Check out the lecture notes.
5. (15%) Answer the following questions.
(a) There are 5 basic input/output signals used in IEEE Std. 1149.1. What are them? (5%) {TCK, TRST,
TMS, TDI, TDO}
(b) A Boundary Scan Cell (BSC) in IEEE Std. 1149.1 is controlled by three important control signals, namely
ClockDR, ShiftDR, and UpdateDR. Show the structure of a boundary scan cell consisting of 2 Flip-Flops and
2 MUXes. Label clearly the following input signals {IN, SI, Test_Mode, ClockDR, ShiftDR, UpdateDR} and
output signals {SO, OUT}, where signals SI stands for scan-input, and SO stands for scan-output. (5%)
(c) For a BSC at a chip's output pin, which signal will determine the timing of launching a data bit into the
interconnect this output pin drives? (5%) UpdateDR
6. (15%) Consider a test pattern split into 5 sub-patterns (one for each of the 5 scan chains): {Chain1=(101XX),
Chain2=(XX10X), Chain3=(XXX0X), Chain4=(0X0X1), Chain5=(XX01X)}.
(a) Draw a compatibility graph to describe the compatibility relations among these five sub-patterns. (5%)
(b) If the broadcasting scan test is applied, then we can use only two common sub-patterns to fill out all 5 scan
chains for this particular test pattern. If one of the common sub-pattern is (1010X), what is the other? (5%)
-> (0X011)
(c) We often need to do output compaction of the responses scanned out of the 5 scan chains before they are
stored back into the ATE. Output compaction is often lossy with the aliasing problem. What is aliasing? Define it
clearly. (5%)
-> Aliasing means a faulty response vector is compacted to a signature the same as the fault-free signature. Or a
detected fault in a test environment WITHOUT output compaction becomes undetected due to the insertion of
the output compaction scheme.
Chain 1 Chain 4
Chain 2 Chain 3 Chain 5
(a) Compatibility Graph
(b) 2nd common sub-pattern for Chain 4 and Chain 5 is (0X011)
2
7. (15%) Answer the following questions about VOT-based oscillation test.
Show the transistor schematic of a VOT (Variable Output Threshold) inverter. (5%) Check out the
lecture notes.
Construct a ring oscillator consists of the following elements - {2 interconnects under testing, 3 normal
inverters with 2 of them used as the interconnect drivers, and 2 VOT inverters) so that this ring oscillator
can support the VOT-based oscillation test.(5%) Check out the lecture notes.
(a) If the oscillation period is denoted as TREF when the 2 VOT inverters are both in the normal mode, and
denoted as TST1 when the VOT inverter of the 1st interconnect is switched to the Schmitt-Trigger mode.
Then, what formula (in terms of TREF and TST1) is positively correlated to the delay across the 1st
interconnect. (5%) (TST1 - TREF)
8. (15%) Answer the following questions about transition-time monitoring schemes discussed in class for
interconnects.
(a) Explain what "non-intrusive monitoring" means briefly. (5%)
-> The monitor can work even when the IC is operated with its designated function.
(b) Draw a logic circuit, namely "TT2PW" in the class, that can convert the transition-time at an observation
point into a pulse signal, while the pulse-width is sensitively correlated to the transition time being
observed. Use 1 Schmitt-Trigger inverter, 1 normal inverter, and 1 XOR gate. (5%)
(c) How can you modify the circuit so that it responds only to the fall-time of the signal at an observation
point while ignoring the rise-time. Show the modified circuit. (5%).
Schmitt-Trigger
(b) TT2PW stage
Schmitt-Trigger
(c) Fall-Time to PW Converter