National Tsing Hua University, Taiwan
EE-6250 超大型積體電路測試 (VLSI Testing)
(Closed-Book) Midterm Exam., Fall Semester, 2020 (Nov. 18, 2020)
(總分 105 分，超過 100 分以 100 分計算)
1. (20%) Answer the following questions.
(a) What do the variables Y and T represent in the following popularly used estimation formula for
defect level: DL = 1 – Y(1-T) (5%) -> Y is manufacturing yield, while T is the test fault coverage
(b) What does IDDQ stand for? Give one fault type in addition to the “transistor-stuck-ON fault” that
could be tested by IDDQ test? (5%) IDDQ means the quiescent current at a VDD pin. Bridging
faults.
(c) Assume that the detection probability of a stuck-at fault by one test vector is p, then what is the
detection probability by applying n such test vectors (from a statistical point of view like
STAFAN). (Hint: calculate the probability that all n test vectors fail to detect a fault first). (5%)
1 – (1-p)n
(d) Consider an OR gate with three inputs denoted as {x1, x2, x3} and output f. Compute Boolean
difference df/dx3 as a Boolean expression in terms of {x1, x2}. (5%) x1’x2’
2. (20%) Answer the following questions.
(a) Consider a two-input NAND-gate, Z = (AB)'. If CC0(A), CC1(A), CC0(B), CC1(B) are 3, 6, 10, and
1, respectively, by SCOAP (Sandia Controllability and Observability Analysis Program). If
observability of Z, denoted as CO(Z), is 5, then, what is CO(A). (5%) (5+1)+1 = 7
(b) There are two major improvement techniques of FAN algorithm over PODEM for combinational test
pattern generation. One is using the head-lines as the pseudo-PIs for value assignment. Name the
second? (5%) Multiple backtrace
(c) For a two-input NOR gate, C = (A+B)', is it true that C-stuck-at-1 fault dominates A stuck-at-0 fault?
(5%) Yes, C-sa-1 dominates A-sa-0
(d) Consider a NOR gate g=(a+b+c)’ during the deductive fault simulation with the fault-free values
{a=0, b=0, c=1}. Assume that the fault lists at {a, b, c} are {Fa, Fb, Fc}, respectively. Derive Fc as a
formula in terms of {Fa, Fb, Fc} as we did in the lecture notes.
3. (10%) Shown below are the flow-chart of a for-loop in C language and one of its possible Extended
Finite State Machine (EFSM). Complete the EFSM by specifying the missing transitions, i.e., T1 and T2.
Note that we assume that the loop index i is realized in the EFSM by register Ri, and the result is stored in
register Rsum, and this EFSM starts its computation when an input signal start goes HIGH.
EFSM model
sum=0; if( ! start ); Transition 1
for(i=1; i<=10; i++){ if( start )
{Ri=1; Rsum=0}
sum = sum + 1;
S0 S1
}
Transition 2
4. (10%) Answer the following questions about the testing of a circuit in Fig. (a), as shown below.
(a) Consider stuck-at-0 fault, derive the test pattern in terms of primary inputs {A, B, C, E}. (A, B,
C, E) = (0, 0, 1, 1).
(b) Consider a stuck-ON fault occurring to the pMOS controlled by input signal B, as shown in Fig. (b).
Derive the test pattern in terms of primary inputs {A, B, C}, so that the IDDQ test can be effective.
(A, B, C) = (0, 1, 1). (Hint: a VDD-to-Ground direct path needs to be established in order to
facilitate the IDDQ test).
1
VDD
A
B = (A + BC)’ A
Stuck-ON
C B C
F B
A
E C
GND
(a) Circuit Under Test
(b) Stuck-ON fault
5. (15%) Consider the technique of critical-path tracing for fault simulation based on the simulation
results in response to an input vector (a,b,c,d)=(1,0,1,0) as shown below.
(a) Draw the circuit on your answer sheet and mark every sensitive input of each gate with a dot like in
the lecture notes. As shown below.
(b) Derive the critical lines. Note that the critical-path tracing traverses the circuit from the outputs
towards the inputs and stops whenever a stem is encountered. (5%) {g, h, e, b1, d}
(c) Derive the set of faults that can be detected based on the information derived in (b). Follow the
branch notations as shown in the figure. The faults on primary inputs should also be considered. (5%)
{g/1, h/1, e/1, b1/1, d/1}
Sensitive Inputs
6. (15%) Consider the sequence of operations in a 5-valued D-algorithm for ATPG for d2-stuck-at-0 fault
in a circuit shown below.
(a) In order to activate the fault and propagate the fault effect to the primary output signal z, what signal
value assignments at {d, h} are needed? (5%) {d=1, h=1}
(b) Based on global learning, what can be implied at signals {e} at this moment? Note that this kind of
global implication usually could speed up the ATPG process. e=1
(c) Derive the final 3-valued test pattern in terms of primary inputs {a, b, c, d}, and using ‘X’ denote a
don’t-care bit. (a,b,c,d)=(X,0,0,1)
a f
b e e1 h
c e2
d d1 g
z
d2
7. (15%) To detect a signal f slow-to-rise transition fault, a two-pattern test <v1, v2> is required.
(a) State what requirement needs to be satisfied for vector v1 in the first time-frame. (5%) -> v1 needs to
cause signal f to logic '0' (or excite signal a stuck-at-1 fault)
(b) In the second time frame, the requirement of v2 is equivalent to the detection of a single-stuck-at
fault. Name the stuck-at fault. (5%) -> v2 needs to be able to detect signal f stuck-at-0 fault in the 2nd
time frame.
2
(c) Suppose that v1={(y1, y2, y3)=(1, 1, 0)} and v2 ={(y1, y2, y3)=(1, 1, 0)} are two vectors satisfying all
the above two requirements. Signals {y1, y2, y3} are PPI signals in the scan chain in the order of (SI
→y3→y2→y1→SO). Can we apply <v1, v2> under the Launch-off-Shifting (LOS) scheme? Why?
(5%) -> NO, v1 cannot become v2 after one cycle of scan shifting operation.