SCHOOL OF ELECTRICAL ENGINEERING

Laboratory Manual
IAEEE101 - Basic Electrical and Electronics Engineering

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Reg. No. : …………………………………………………………
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VIT – A Place to learn; A Chance to grow

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 VISION AND MISSION STATEMENTS

Vision of the Institute:

Transforming life through excellence in education and research.

Mission of the Institute:

❖ World class Education: Excellence in education, grounded in ethics and
critical thinking, for improvement of life.
❖ Cutting edge Research: An innovation ecosystem to extend knowledge
and solve critical problems.
❖ Impactful People: Happy, accountable, caring, and effective workforce
and students.
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international industries & universities for productivity and economic
development.
❖ Service to Society: Service to the region and world through knowledge
and compassion.

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 SCHOOL OF ELECTRICAL ENGINEERING

Course Name : Basic Electrical and Electronics Engineering

Course Code : IAEEE101

Register Number : _____________________________

Certified that this is a bonafide work done by _________________________ of

Winter (2025-2026) semester [Link]. ______________ submitted for the

practical examination held on _________ at Vellore Institute of Technology,

Vellore – 632 014.

Date: Faculty In – charge

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 List of Experiments
Simulation Experiments
Sl. No Date Name of the Experiment Faculty sign
with date

Verification of Kirchhoff’s law

Verification of Thevenin’s theorem

Verification of maximum power transfer theorem

Sinusoidal steady state response of series RLC circuit

Design of full adder digital circuit

Hardware Experiments

Faculty sign
Sl. No Date Name of the Experiment
with date

Verification of Superposition theorem

Design of half adder circuit using logic gates

Characteristics of PN Junction diode

Design of regulated power supply using Zener diode

Design of Darlington amplifier using BJT

Challenging experiment

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 Expt. No.:
Verification of Kirchhoff’s Law
Date:

Aim:
To simulate the given electric circuit and obtain the various voltages and currents and validate the obtained
results by mesh and nodal analysis.

Software /Tool required:

ORCAD / Capture CIS → Analog Library – R
Source Library – VDC
Ground (GND) – 0 (zero)
Simulation Settings: Analysis Type – Bias point

Apparatus Required:
Sl. No. Part Specification Quantity
1. Resistor (R/Analog) 330 Ω, 270 Ω, 390 Ω, 1 each
220 Ω, 180Ω
2. DC voltage source (VDC/Source) - 2
3. Wires - As needed
4. Ground (0/CAPSYM) - 1

Theory:
Kirchhoff’s voltage law (KVL) states that that in a closed circuit, the algebraic sum of all source voltages
must be equal to the algebraic sum of all the voltage drops. Systematic application of KVL along with
the element V-I relationships yields mesh analysis which is applicable to planar circuits. Mesh analysis
involves finding the loop currents based on KVL equations. From the loop currents, the individual branch
currents and hence the branch voltages can be found.
Kirchhoff’s current law (KCL) states that at any node (junction) in a circuit the algebraic sum of currents
entering and leaving a node at any instant of time must be equal to zero. Systematic application of KCL
along with the element V-I relationships yields nodal analysis which is applicable to any type of circuit.
Nodal analysis involves in finding the node voltages based on KCL equations. From the node voltages,
the branch voltages and hence the branch currents can be found.

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Circuit Diagram:
330 270 390

10V
12V
220 180

Procedure:
1) Open OrCAD Tool and create new project.
2) Draw the circuit using the elements: R analog, VDC source, connecting wire and a ground
potential.
3) Enter the values in R and VDC.
4) Go to PSpice and create a new simulation profile.
5) In the simulation settings dialogue box, chose analysis type as Bias Point, enter APPLY and
OK.
6) Now click Run PSpice.
7) Enable bias voltage display and bias current display.
8) Compare the values to the manually calculated values and write the result.

Manual Calculation (Use mesh current analysis and solve the equations with Cramer’s method):

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Manual Calculation (Use node voltage analysis):

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Photograph of simulation circuit done in the lab along with its results:

Inferences:

Result:
Manual Calculations Practical output
V1
V2
I1
I2
I3

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 Expt. No.:
Verification of Thevenin’s Theorem
Date:

Aim:
To simulate the given electric circuit and verify the Thevenin’s theorem by computing load current and
voltage of a given DC circuit.

Software /Tool required:

ORCAD / Capture CIS → Analog Library – R
Source Library – VDC, IDC
Ground (GND) – 0 (zero)
Simulation Settings: Analysis Type – Bias point

Apparatus Required:
Sl. No. Part Specification Quantity
1. Resistor (R/Analog) 330 Ω, 270 Ω, 390 Ω, 1 each
220 Ω, 180Ω
2. DC voltage source (VDC/Source) - 1
3. DC current source (IDC/Source) 1
4. Wires - As needed
5. Ground (0/CAPSYM) - 1

Theory:
Thevenin’s theorem states that a linear, active, resistive network which contains one or more voltage
or current sources can be replaced by a single voltage source and a series resistance. The voltage is
called the Thevenin’s equivalent voltage, VTH and series resistance is called the Thevenin’s equivalent
resistance, RTH.

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Circuit Diagram:

Consider RL=10 
Procedure:
1) Open OrCAD Tool and create new project.
2) Draw the circuit using the elements: R analog, VDC source, IDC source connecting wire
and a ground potential.
3) Enter the values in R, IDC and VDC.
4) To find VTH:
a. Remove the load resistor (RL) and keep the terminals open.
b. Analyze the circuit to find the voltage across open terminals of the load resistance (open
circuit voltage).
c. The voltage across open terminals of the load resistance is called Thevenin’s voltage.

5) To find RTH:
a. Make all the independent sources dead. Replace all the independent voltage sources with
short circuit and all the independent current sources with the open circuit.
b. Remove the load resistor (RL) and find the equivalent circuit resistance by looking from the
open terminals of the load resistance.
c. The computed resistance is called Thevenin’s resistance, RTH

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 6) To find IL:
a. Draw the Thevenin’s equivalent circuit with Thevenin’s voltage connected in series with the
Thevenin’s resistance
b. Connect the load resistance in series with the Thevenin’s resistance
c. Compute the current flowing through the load resistance

7) Steps for execution 4,5,6:

a. Go to PSpice and create a new simulation profile.
b. In the simulation settings dialogue box, chose analysis type as Bias Point, enter APPLY
and OK.
c. Now click Run PSpice.
d. Enable bias voltage display and bias current display.
e. Compare the values to the manually calculated values and write the result.

Manual Calculation (For the above circuit calculate VTH, RTH and IL):

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Photograph of simulation circuit done in the lab along with its results:

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Inferences:

Result:
Manual Calculations Practical output
VTH
ITH
IL

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 Expt. No.:
Verification of Maximum Power Transfer
Date:
Theorem

Aim:
To simulate the given electric circuit and verify the Maximum Power Transfer Theorem.

Software /Tool required:

ORCAD / Capture CIS → Analog Library – R
Source Library – VDC, IDC
Ground (GND) – 0 (zero)
Simulation Settings: Analysis Type – DC Sweep

Apparatus Required:
Sl. No. Part Specification Quantity
1. Resistor (R/Analog) 6 Ω, 3 Ω, 12 Ω, 2 Ω 1 each
2. DC voltage source (VDC/Source) - 1
3. DC current source (IDC/Source) 1
4. Wires - As needed
5. Ground (0/CAPSYM) - 1

Theory:
Maximum power is developed in a load when the load resistance equals the Thevenin resistance of the
source to which it is connected. All linearly constructed sources can be reduced to their Thevenin
equivalent.
In DC circuits, the load can be represented by a resistance RL. The source develops a voltage VL across
the load and enables current IL to flow into it. The power delivered to the load resistance (R L) depends
on the value of RL. Maximum current IL occurs when RL = 0 (shorted terminals). The maximum voltage
VL occurs when RL = ∞ (open circuited terminals). Yet load power PL = 0 for both cases. PL is maximum
when RL equals the Thevenin equivalent resistance of the source, i.e. when RL = RTH.

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Circuit Diagram:

Procedure:
1) Open OrCAD Tool and create new project.
2) Draw the Thevenin’s equivalent circuit (VTh and RTh) using the tools: R analog, VDC source, IDC
source, connecting wire and a ground potential.
3) Enter the values in R, IDC and VDC.
4) After drawing the circuit, go to Part and chose PARAM/SPECIAL.
5) Place it beside the circuit and double click on PARAMETER.
6) In the schematic tab, click on pivot and then click on new property.
7) Now enter name as Rvar and value as 1. Enter APPLY and OK.
8) Go to PSpice and create a new simulation profile.
9) In the simulation settings dialogue box, chose analysis type as DC Sweep, chose sweep variable as
global parameter, enter parameter name as Rvar. Under sweep type, enter start value =1, end value = 20
and increment = 0.2. Enter APPLY and OK.
10) Chose power dissipation marker and put it on Rvar.
11) Now click Run PSpice.
12) A different window will open up with a graph containing peak value, RTh (x coordinate) and Pmax
(y coordinate).
13) Compare the values to the manually calculated values and write the result.

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Manual Calculation:
Find VTH

Find RTH

Find power across RL

Photograph of simulation circuit done in the lab:

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Photograph of output graph obtained using PSPICE:

Inferences:

Result:
Manual Calculations Practical output
VTh
RTh
Pmax

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 Expt. No.: Sinusoidal Steady State Response of Series
Date: RLC Circuit

Aim:
To find the resonance frequency of a series RLC circuit using OrCAD tool.

Software /Tool required:

ORCAD / Capture CIS → Analog Library – R, L & C
Source Library – VAC, Ground (GND) – 0 (zero)
Simulation Settings: Analysis Type – AC Sweep

Circuit Diagram:

Theory:
For an RLC circuit, 𝑍 = √𝑅 2 + (𝑋𝐿 − 𝑋𝐶 )2
When XL=XC; Z is minimum.
I=VZ is maximum
The frequency found when XL=XC is called resonance frequency.
1
Formulae: 𝑓 = 2𝜋√𝐿𝐶

Model Graph:

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Procedure:
1) Open OrCAD Tool and create new project.
2) Draw the circuits using the tools: R analog, L analog, C analog, VAC/source, connecting wire and
a ground potential.
3) Enter the values in R, L, C and V.
4) Go to PSpice and create a new simulation profile.
5) In the simulation settings dialogue box, chose analysis type as AC Sweep. Under AC sweep type,
enter start frequency=0.1, end frequency=100000 and points/decade=100. Now enter APPLY and
OK.
6) Take the current marker and place at the point between wire and the inductor.
7) Now click Run PSpice
8) A different window with a bell-shaped curve opens up with its peak giving us the resonance
frequency (x coordinate) and resonance current (y coordinate).
9) Compare the values to the manually calculated values and write the result.

Manual Calculations:

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Photograph of simulation circuit done in the lab:

Photograph of output graph obtained using PSPICE:

Inferences:

Result:

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 Expt. No.:
Design of Full Adder Digital Circuit
Date:

Aim:
To design full adder digital circuit and verify its truth table.

Software / Tools Required:

ORCAD / PSpice simulator – AND GATE: 7408
OR GATE: 7432
XOR GATE: 7486
Simulation Settings: Time domain (Transient)

Circuit diagram and truth table:

Practical Circuit:

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Theory:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs
(X, Y and Carry In) and two outputs (Sum and Carry Out). A full adder is useful to add three bits at a
time but a half adder cannot do so. In full adder, sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.
Sum = A xor B xor C
Carry = A.B +C (A xor B)

Procedure:
1. Open OrCAD and create a new project.
2. Draw the circuits using the parts given in apparatus required, digclock/source and the connecting
wires.
3. In digclock 1, Enter: offtime = ontime =4 ms; In digclock 2, Enter: offtime = ontime = 2ms; In
digclock 3: offtime = ontime = 1 ms.
4. Create a new simulation profile in PSpice. In simulation settings: chose analysis type as time
domain(transient) and set run to time = 8ms.
5. Click apply and ok.
6. Now take the voltage probe and put it at the input and output end of the circuit.
7. Click run. Note down the graph and verify the truth table.

Photograph of simulation circuit done in the lab:

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Photograph of output graph obtained using PSPICE:

Inferences:

Result:

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 Expt. No.:
Date: Verification of Superposition Theorem

Aim:
To conduct an experiment to verify Superposition theorem.

Apparatus Required:
Sl. No. Part Specification Quantity
1. Resistors 1kΩ, 220 Ω, 330 Ω Each1
2. Voltmeter 0-30V 2
3. Ammeter 0-50mA 3
4. RPS DC 0-30 V dual 1

Theory:
Superposition theorem states that in a linear bilateral network containing more than one source, the
current flowing through the branch is equal to the algebraic sum of all the currents flowing through that
branch when sources are considered one at a time and replacing other sources by their respective internal
resistances.

Circuit Diagram:

Circuit 1

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 Circuit 2 Circuit 3

Procedure:
1. Connect the circuit as per the diagram.
2. Set a voltage value of 5V and 10V using 𝑅𝑃𝑆1 and 𝑅𝑃𝑆2 and note down the ammeter reading.
3. Set the voltage as 5V using 𝑅𝑃𝑆1 alone and disconnect 10V source 𝑅𝑃𝑆2 and short circuit the
terminals as shown in Fig. (ii) and note the ammeter reading (say 𝐼1)
4. Repeat the same procedure with 𝑅𝑃𝑆2 (10V) and note down the ammeter reading (say 𝐼2).

5. Verify superposition theorem. 𝐼 = 𝐼1 + 𝐼2

Precautions:
1. Voltage control knob of RPS should be kept at minimum position initially.
2. Power supply should be turned off while connecting circuits.
3. Make sure that mode select of Voltmeter/Ammeter is on Ammeter (A) side while
measuring current.

Manual Calculation:

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Photograph of simulation circuit done in the lab along with its results:

Observations:

Voltage Source (RPS)

Ammeter Reading
V1 V2
Circuit (1) 𝐼=

Circuit (2) 𝐼1 =

Circuit (3) 𝐼2 =

I(Observed) = 𝐼1 + I2

Inferences:

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Result:

Ammeter Reading (mA) Current calculated (mA)

Circuit (1) 𝐼 =

Circuit (2) 𝐼1 =

Circuit (3) 𝐼2 =

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 Expt. No.: Design of Half Adder Circuit using Logic
Date: Gates

Aim:
To design and verify a half adder circuit using logic gates.

Apparatus/Tool required:

S. No. Name of the apparatus Range / Type Quantity

1 IC 7486 - 1 No.
2 IC 7408 - 1 No.
3 LED - 2 Nos.
4 RPS 0 – 15 V 1 No.
5 Resistor 330 Ω 2 Nos.
6 Breadboard - 1 No.
7 Wires - Few

Theory:
Half adder circuit is a two-bit adder which is also known as modulo 2 adder.
The expression for logic sum, S of half adder is: 𝑆 = 𝐴𝐵̅ + 𝐴̅𝐵 = 𝐴 ⊕ 𝐵
The logic expression for carry, C = A.B

Circuit diagram and truth table:

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Practical circuit diagram:
U1A
1 330 LED
7486 3
2

A
U2A
1 330 LED
7408 3
2
B
0
Procedure:
1. Connect the circuit as shown in figure
2. Apply voltages to inputs A and B as represented in the truth table and verify the truth table

Truth Table:
A B S=AB C=A.B

0 0

0 1

1 0

1 1

Photograph of the practical circuit done in the lab:

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Inferences:

Result:

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 Expt. No.:
Characteristics of PN Junction Diode
Date:

Aim:
To plot the volt-ampere characteristics of a P-N Junction diode.

Apparatus/Tool required:
Sl. No. Components Name Range Quantity
1 Resister 1kΩ, 470Ω 1 No.
2 PN Junction Diode D1N4007 1 No.
3 RPS 0-32 V (DC) 1 No.
4 Ammeter (0-50) mA, Each 1 No.
(0-500) µA
5 Voltmeter (0-1)V, (0-10)V Each 1 No.
6 Connecting Wires - Few
7 Bread Board - 1 No.

Identification of Terminals:

Circuit Diagram:
Forward Bias:
(0-50)mA

-
1k
A +
(0-32)V
V (0-1)V

D1N4007 -

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Reverse Bias:
(0-500)uA

470
A
(0-32)V
V (0-10)V
D1N4007

Model Graph:
V-I Characteristics:

Observations:
Forward Bias:

S. No. VF (Volts) IF (mA)

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Reverse Bias:

S. No. VR (Volts) IR (A)

VI Characteristics (Draw the graph as per the readings obtained):

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Photograph of the practical circuit done in the lab:

Inferences:

Result:

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 Expt. No.:
Design of regulated power supply using
Date: Zener diode

Aim:
To design a regulated power supply using Zener diode and analyze its performance.

Apparatus/Tool required:

S. No. Name of the apparatus Range / Type Quantity

1 Zener diode - 1 No.
2 RPS 0 – 30 V 1 No.
3 Voltmeter 0 – 30 V 2 No.
4 Resistor 330 Ω 1 No.
5 Resistor 1 kΩ 1 No.
6 Breadboard - 1 No.
7 Wires - Few

Theory:
Zener diodes are generally used in the reverse bias mode. This voltage across the diode (Zener Voltage,
Vz) remains nearly constant even with large changes in current through the diode caused by variations
in the supply voltage or load. This ability to control itself can be used to great effect to regulate or
stabilize a voltage source against supply or load variations. The Zener diode maintains a constant
output voltage until the diode current falls below the minimum Iz value in the reverse breakdown
region, which means the supply voltage, VS, must be much greater than Vz for a successful breakdown
operation.
When no load resistance, RL, is connected to the circuit, no load current (IL = 0), is drawn and
all the circuit current passes through the Zener diode which dissipates its maximum power. So, a
suitable current limiting resistor, (RS) is always used in series to limit the Zener current to less than its
maximum rating under this "no-load" condition.
As shown in the circuit diagram, a more stable reference voltage can be produced by connecting
a simple Zener regulator circuit across the output of the rectifier. The breakdown condition of the Zener
can be confirmed by calculating the Thevenin voltage, VTH, facing the diode is given as:
𝑅𝐿
𝑉𝑇𝐻 = 𝑉
𝑅𝑆 + 𝑅𝐿 𝑆
This is the voltage that exists when the Zener is disconnected from the circuit. Thus, VTH has
to be greater than the Zener voltage to facilitate breakdown. Now, under this breakdown condition,
irrespective of the load resistance value, the current through the current limiting resistor, IS, is given
by,
𝑉𝑆 − 𝑉𝑍
𝐼𝑆 =
𝑅𝑆
The output voltage across the load resistor, VL, is ideally equal to the Zener voltage and the
load current, IL, can be calculated using Ohm’s law:
𝑉
𝑉𝑆 = 𝑉𝑍 and 𝐼𝐿 = 𝑅𝐿
𝐿

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Thus, the Zener current, IZ is, 𝐼𝑍 = 𝐼𝑆 − 𝐼𝐿 .

Note that you have constructed a basic power supply, its quality depends on its load and line regulation
characteristics as defined below:

Load Regulation: It indicates how much the load voltage varies when the load current changes.
Quantitatively, it is defined as:
𝑉 −𝑉
Load regulation = 𝑁𝐿𝑉 𝐹𝐿 x 100%
𝐹𝐿
where VNL = load voltage with no load current (IL = 0) and VFL = load voltage with full load current.
The smaller the regulation, the better is the power supply.

Line Regulation: It indicates how much the load voltage varies when the input line voltage changes.
Quantitatively, it is defined as:
𝑉 −𝑉
Line regulation = 𝐻𝐿𝑉 𝐻𝐿 x 100%
𝐿𝐿

where VHL = load voltage with high input line voltage, and VLL = load voltage with low input line
voltage. As with load regulation, the smaller the regulation, the better is the power supply.

Circuit Diagram:
330

0-15V 0-15V

Zener Diode
1k
V

Procedure:
Line Regulation:
1. Connect the circuit as shown in the diagram
2. Keep the load resistance constant at a particular value
3. Vary the input voltage and note down the variation in the output voltage

Load Regulation:
1. Connect the circuit as shown in the diagram
2. Keep the input voltage constant at a particular value
3. Vary the load resistance and note down the variation in the output voltage

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Observations:
Table (i) Line Regulation: Load Resistor = _________Ω

Input DC Voltage Output DC Voltage (VL)

Sl. No
(Vi) in Volts in Volts
1

Table (ii) Load Regulation: Input DC voltage = _________V

Load Resistance in Output DC Voltage (VL) in

Sl. No
ohms Volts
1

Photograph of the practical circuit done in the lab:

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Inferences:

Result:

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 Expt. No.:
Design of Darlington amplifier using
Date: BJT

Aim:
To design a circuit to vary the intensity of the lamp using Darlington pair of BJT.

Apparatus Required:
S. No. Name of the apparatus Range / Type Quantity
1 BJT BC547 2 Nos.
2 RPS 0 – 30 V 1 No.
3 Diode 1N4007 1 No.
4 Potentiometer 1 kΩ 1 No.
5 Resistors 330 Ω 3 No.
6 LED - 3 No.
7 Breadboard - 1 No.
8 Wires - Few

Theory:
A Darlington pair is two transistors that act as a single transistor but with a much higher current gain.
This mean that a tiny amount of current from a sensor, micro-controller or similar can be used to drive a
larger load. An example circuit is shown below:

The Darlington Pair can be made from two transistors as shown or Darlington Pair transistors are
available where the two transistors are contained within the same package. Transistors have a
characteristic called current gain. This is referred to as its hFE. The amount of current that can pass
through the load in the circuit above when the transistor is turned ON is:
Load current = input current x transistor gain (hFE)

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The current gain varies for different transistors and can be looked up in the data sheet for the device. For a
normal transistor this would typically be about 100. This would mean that the current available to
drive the load would be 100 times larger than the input to the transistor. In some applications the amount
of input current available to switch ON a transistor is very low. This may mean that a single transistor
may not be able to pass sufficient current required by the load. As stated earlier this equals the input
current x the gain of the transistor (hFE). If it is not possible to increase the input current then the gain
of the transistor will need to be increased. This can be achieved by using a Darlington Pair.

A Darlington Pair acts as one transistor but with a current gain that equals:
Total current gain (hFE total) = current gain of transistor 1 (hFE t1) x current gain of transistor 2 (hFE
t2)
For example, if you had two transistors with a current gain (hFE) = 100: (hFE total) = 100 x 100
(hFE total) = 10,000

You can see that this gives a vastly increased current gain when compared to a single transistor.
Therefore, this will allow a very low input current to switch a much bigger load current.
Normally to turn ON a transistor the base input voltage of the transistor will need to be greater than 0.7V.
As two transistors are used in a Darlington Pair this value is doubled. Therefore, the base voltage will
need to be greater than 0.7V x 2 = 1.4V.
It is also worth noting that the voltage drops across collector and emitter pins of the Darlington Pair when
the turn ON will be around 0.9V. Therefore, if the supply voltage is 5V (as above) the voltage across the
load will be will be around 4.1V (5V – 0.9V).

Circuit Diagram:

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Procedure:
1. Connect the elements of circuit in the breadboard as given in the circuit diagram.
2. Connect the circuit to the Regulated Power Supply, turn it ON and set the voltage value to 5V.
3. Now vary the voltage using the variable resistor.
4. Observe the intensity variation in the LED bank.

Photograph of work done in the lab along with its results:

Inferences:

Result:

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 ***

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 Program Outcomes
PO1: Engineering Knowledge: Apply knowledge of mathematics, natural science,
computing, engineering fundamentals and an engineering specialization as specified in
WK1 to WK4 respectively to develop to the solution of complex engineering problems.
PO2: Problem Analysis: Identify, formulate, review research literature and analyze
complex engineering problems reaching substantiated conclusions with consideration for
sustainable development. (WK1 to WK4)
PO3: Design/Development of Solutions: Design creative solutions for complex
engineering problems and design/develop systems/components/processes to meet identified
needs with consideration for the public health and safety, whole-life cost, net zero carbon,
culture, society and environment as required. (WK5)
PO4: Conduct Investigations of Complex Problems: Conduct investigations of complex
engineering problems using research-based knowledge including design of experiments,
modelling, analysis & interpretation of data to provide valid conclusions. (WK8).
PO5: Engineering Tool Usage: Create, select and apply appropriate techniques, resources
and modern engineering & IT tools, including prediction and modelling recognizing their
limitations to solve complex engineering problems. (WK2 and WK6)
PO6: The Engineer and The World: Analyze and evaluate societal and environmental
aspects while solving complex engineering problems for its impact on sustainability with
reference to economy, health, safety, legal framework, culture and environment. (WK1,
WK5, and WK7).
PO7: Ethics: Apply ethical principles and commit to professional ethics, human values,
diversity and inclusion; adhere to national & international laws. (WK9)
PO8: Individual and Collaborative Team work: Function effectively as an individual,
and as a member or leader in diverse/multi-disciplinary teams.
PO9: Communication: Communicate effectively and inclusively within the engineering
community and society at large, such as being able to comprehend and write effective
reports and design documentation, make effective presentations considering cultural,
language, and learning differences
PO10: Project Management and Finance: Apply knowledge and understanding of
engineering management principles and economic decision-making and apply these to one’s
own work, as a member and leader in a team, and to manage projects and in multidisciplinary
environments.
PO11: Life-Long Learning: Recognize the need for, and have the preparation and ability
for i) independent and life-long learning ii) adaptability to new and emerging technologies
and iii) critical thinking in the broadest context of technological change. (WK8)

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