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Verilog Code

The document provides various implementations of basic logic gates using different modeling techniques in Verilog, including AND, OR, NAND, NOR, EX-OR, and NOT gates. It demonstrates structural, data flow, and behavioral modeling approaches for these gates. Each module defines inputs and outputs, along with the logic operations performed.

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ayush.sharma
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3 views3 pages

Verilog Code

The document provides various implementations of basic logic gates using different modeling techniques in Verilog, including AND, OR, NAND, NOR, EX-OR, and NOT gates. It demonstrates structural, data flow, and behavioral modeling approaches for these gates. Each module defines inputs and outputs, along with the logic operations performed.

Uploaded by

ayush.sharma
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

//AND gate using Structural modeling

module and_gate_s(a,b,y);
input a,b;
output y;
and(y,a,b);
endmodule

//AND gate using data flow modeling


module and_gate_d(a,b,y);
input a,b;
output y;
assign y = a & b;
endmodule

//AND gate using behavioural modeling


module AND_gate_b(a,b,y);
input a,b;
output y;
always @ (a,b)
y = a & b;
endmodule

//OR gate using data flow modeling


module or_gate_d(a,b,y);
input a,b;
output y;
assign y = a | b;
endmodule
//NAND gate using data flow modeling
module nand_gate_d(a,b,y);
input a,b;
output y;

assign y = ~(a & b);

endmodule

//NOR gate using data flow modeling


module nor_gate_d(a,b,y);
input a,b;
output y;

assign y = ~(a | b);

endmodule

//EX-OR gate using data flow modeling


module xor_gate_d(a,b,y);
input a,b;
output y;

assign y = a ^ b;

endmodule
module not_gate_s(a,y);
input a;
output y;

not(y,a);

endmodule

module not_gate_d(a,y);
input a;
output y;

assign y = ~a;

endmodule

module not_gate_b(a,y);
input a;
output reg y;

always @ (a)
y = ~a;

endmodule

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