SoCT Lecture Notes SoC Logic Design Recap
SYSTEM-ON-CHIP TECHNOLOGIES
SoC Logic Design Recap
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SoCT Lecture Notes SoC Logic Design Recap
Table of Contents
Simple Static CMOS Logic Gates............................................................................................... 22
DeMorgan Rule......................................................................................................................... 22
Generic Model of Static CMOS ................................................................................................. 22
Systematic Static CMOS Logic Design ...................................................................................... 22
Register Transfer Blocks: Arithmetic ........................................................................................ 23
Basic Register / Storage Element ............................................................................................. 23
CMOS Latch .............................................................................................................................. 23
CMOS Flip-flop.......................................................................................................................... 24
Flip-flop Timing ......................................................................................................................... 24
Metastability ............................................................................................................................ 24
Finite State Machines ............................................................................................................... 24
FSM example: Counter ............................................................................................................. 25
Practical Relevance of FSMs ..................................................................................................... 25
How are FSMs designed today? ............................................................................................... 25
FSM Logic Depth ....................................................................................................................... 25
Test Yourself: SoC Component Design ..................................................................................... 27
Test Yourself: Solutions ............................................................................................................ 29
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SoCT Lecture Notes SoC Logic Design Recap
SoC Component Design
Simple Static CMOS Logic Gates
Boolean equations can easily be converted into static CMOS circuits. To illustrate this, let us
start with a simple NAND function. To implement a 2 input NAND function, two nMOS tran-
sistors are connected in serial, complemented by two pMOS transistors in parallel. The out-
put is discharged only if both nMOS are turned on. In all other cases, one of the pMOS is
turned on and the output is charged to VDD. For a NOR function, we can use two nMOS in
parallel, complemented by two pMOS in serial. The output is charged to VDD only if both
pMOS are turned on. In all other cases, one of the nMOS is turned on and the output is dis-
charged to GND. Note that in the static state, there is no conducting path between V DD and
GND.
DeMorgan Rule
DeMorgan’s rule, one of the most important logic theorems for digital electronics, says that
any logical binary expression remains unchanged if we
• change all variables to their complements,
• change all AND operations to ORs,
• change all OR operations to ANDs, and
• take the complement of the entire expression.
As a consequence of DeMorgan’s rule, all logic functions can be expressed by combinations
of either NAND or NOR gates.
Generic Model of Static CMOS
In general, a generic model can be used to convert Boolean equations into static CMOS cir-
cuits. Each AND function generates serially connected nMOS transistors on a path from the
output to GND, complemented by parallel connected pMOS transistors on a path from the
output to VDD. Each OR function generates parallel nMOS, complemented by serial pMOS
transistors, respectively. Finally, the output is always inverted, due to the switching proper-
ties of MOS transistors.
Systematic Static CMOS Logic Design
Let us look at an example logic function: Z = AB + C
The first step in systematic design is to check the inverter function at the output. As our ex-
ample function is not inverted, we need to modify it, according to
Z = not (not (AB + C))
Then we start with the nMOS block, generating serial nMOS for AND (AB), parallel nMOS for
OR (C). Next, the pMOS block is added in the inverse way, parallel for AND (AB), serial for OR
(C). Finally, an extra inverter is added at the output.
In summary, the systematic static CMOS logic design consists of the following steps:
1. Check the inverter function at the output, insert an inverter if necessary.
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SoCT Lecture Notes SoC Logic Design Recap
2. Start with the nMOS block from output to GND, use serial nMOS transistors for AND,
parallel nMOS transistors for OR functions.
3. Continue with the pMOS block from the output to VDD, using the dual nMOS net-
work.
Today logic synthesis is used to generate CMOS logic from higher level design descriptions,
but the systematic design approach as illustrated here seems helpful for understanding the
principles of CMOS circuit design.
Register Transfer Blocks: Arithmetic
Numerous applications based on mathematical operations, like digital filters, or architectural
building blocks, like processor arithmetic logic units (ALUs), are designed using a set of regis-
ters to store logical values and a set of combinational circuits to implement logical intercon-
nections. Input values are stored in multi-bit registers, and then connected in combinatorial
logic circuitry. Intermediate results are stored in the next stage of registers, and then passed
on to the next stage of logic circuitry.
Combinatorial logic implementing Boolean equations was one example for logic circuitry.
Later we will have a look at some more examples, e.g. adders and multiplex-
ers/demultiplexers.
Basic Register / Storage Element
We have seen so far how electrical circuits can be built from transistor devices, logical gates
from circuits, register transfer blocks from gates, and all these together will form complex
systems. As storage elements, e.g. registers, are important building blocks on register trans-
fer level, we will have a more detailed look inside registers now.
The basic CMOS storage element consists of a loop of two inverters. Connected together,
they form a stable circuit, which can stick to either “1” or “0” at the corresponding nodes.
One inverter drives the input of the other. On the slide, the upper left hand chart shows the
closed loop logic circuit, the upper middle chart shows the same circuit with outputs Q and
notQ, the upper right hand chart shows the transistor level circuit.
Up to now, the circuit has just outputs, no inputs. It is impossible to externally drive a node
without generating a short-circuit path. In order to set a specific logic value, we need to
open the loop. This can be done by substituting the inverters with NAND gates, as shown in
the bottom chart. A control input x is used to determine the functionality of the NAND gate:
For x = 1, the NAND gate operates like an inverter, and the current logic value is stored in
the loop. For x = 0, the output of the NAND gate switches to “1”, thus setting this value into
the loop. In order to set both “0” and “1” values, we need an extra circuit to set the values
into both parts of the loop. The resulting circuit is called a latch.
CMOS Latch
The logic circuit, the circuit symbol, and the truth table of a Latch are shown on the slide.
The latch has two input signals (e, D) and two output signals (Q, notQ). The enable signal e
controls the latch: For e = 1, the value of D is written into the latch, Q = D. For e = 0, the
latch is locked on the current value of Q. Any change of the input D will not affect the output
Q in this state. The latch is called level-controlled, as the logic level of the control signal e
determines the behavior of the latch.
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SoCT Lecture Notes SoC Logic Design Recap
CMOS Flip-flop
In contrast to the level-controlled latch, a flip-flop is clock edge-controlled. A flip-flop is the
most important sequential element, used in almost all synchronous digital circuits, e.g. for
register banks, counter, shift registers.
A flip-flop consists of two serially connected latches, a Master and a Slave. A clock signal is
used to control the enable inputs of both latches. When the clock signal is “0”, i.e. e = 1 for
the first latch, the value of input D is set into the Master latch. At the same time, the Slave
latch is locked to the previous value of Q. When the clock signal switches to “1”, i.e. e = 0 for
the first latch, the Slave latch is set to the current value of the Master latch. Any further
change at the input D does not affect the Slave latch, as the Master latch is locked in this
state.
Overall, the flip-flop is set to the current value of the input D at the positive clock edge,
whereas for all other times, the output Q of the flip-flop is locked.
Flip-flop Timing
There are some timing restrictions for flip-flops, which are illustrated on the slide. For each
flip-flop, a set of three characteristic parameters is specified: The setup-time tsetup, the hold-
time thold, and the clock-to-output delay tc2q.
The first two parameters tsetup and thold impose restrictions on the input signal of the flip-
flop. The input signal D must be stable for the setup-time before clock edge and for the
hold-time after clock edge. This is required in order to guarantee correct setting of the flip-
flop at the clock edge and to avoid metastability.
The third parameter, tc2q, specifies the delay after the clock edge until the valid data will be
visible at the output.
Metastability
Violation of either setup-time or hold-time restrictions may result in undefined or oscillating
output signals of a flip-flop. If there occurs a change of input data D within the setup/hold
time window around the clock edge, the output Q may show undefined or oscillating signal
values.
The designer has to make sure to avoid such violations. This becomes more and more criti-
cal, as in todays and in future System-on-Chip designs, there is an increasing number of on-
chip clock domains and externally imposed clocks, which requires careful attention to con-
trol the setup/hold constraints at the clock domain boundaries. In such cases, it is recom-
mended to use double-registered inter-domain signal interfaces or FIFO buffers with sepa-
rate read and write clocks.
Finite State Machines
Finite State Machines (FSMs) are widely used to generate various forms of sequential con-
trollers or to implement reactive systems. Generally, FSMs consist of a register bank, input
logic, output logic, and a feedback loop. The input logic f(x,u) combines primary inputs x
with current-state vector u = [Q1 to Qn] to generate the next-state vector v = [D1 to Dn]. The
output logic g(x,u) combines primary inputs x with current-state vector u to generate the
output vector y. The clock signal switches the register bank from the current state to the
next state.
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SoCT Lecture Notes SoC Logic Design Recap
There exist different types of FSMs. The most general case is the Mealy-Machine, as shown
in the upper part of the slide. The other types are formed from subsets of the general case:
The Moore-Machine has no combinatorial logic path from the primary inputs x to the out-
puts y, so there is g(x,u) = g(u). The Medvedev-Machine has no output logic, i.e. y = g(x,u) =
g(u) = u. The No-input-logic Machine has no primary inputs x; the next state is generated
from the current state only, i.e. f(x,u) = f(u).
FSM example: Counter
A binary counter can easily be implemented using a Medvedev-type Finite State Machine as
shown on the slide. The input logic f(x,u) consists of a series of cascaded one-bit adders, with
Carry output of each stage connected to Carry input of the next stage. The Sum signals form
the next-state vector. The primary input x is a one-bit control signal connected to the Least
Significant Bit (LSB) adder. For x = 0, the counter will keep its value: S t+1 = St. For x = 1, the
counter will increment its value with each clock cycle: St+1 = St +1. The maximum clock fre-
quency of this counter is determined by the propagation delay of the carry signals through
the adder chain, as the Sum output of the Most Significant Bit (MSB) adder has to reach its
final value before the next clock edge, taking into account the setup-time restrictions of the
register flip-flop as well.
Practical Relevance of FSMs
In state-of-art synchronous digital design all sequential logic consists of communicating
FSMs, i.e. a sequence of combinatorial logic and registers. The maximum clock frequency is
limited by the propagation time through the combinatorial logic (ΣTlogic), the setup-time
(Tsetup) and the clock-to-output delay (Tc2q) of the registers.
Tclk > ΣTlogic + Tsetup + Tc2q
To facilitate easy connections between sequential logic blocks on a System-on-Chip, it is ad-
vised to stick to one design style and consequently use registers either at the input or the
output of the blocks.
How are FSMs designed today?
Each FSM illustrated as a set of state nodes and state transition graphs can be transformed
into an equivalent VHDL representation. Both FSM representations are behavioral descrip-
tions at the RTL level. The VHDL FSM representation can be automatically synthesized into a
structural representation consisting of combinatorial logic and state registers.
FSM Logic Depth
The question we now want to go after is: “How many levels of logic can one afford for the
FSM combinatorial logic block in a given case study of a 2.48 Gbps SDH framer?” The num-
ber of logic levels between two successive register stages in a FSM is also referred to as the
logic depth of the FSM.
The following timing condition must be fulfilled for sequential logic:
Tclk > ΣTlogic + Tsetup + Tc2q
Tsetup, Tc2q, the average delay per logic gate level tgate are obtained from the CMOS databook.
From previous synthesis and physical design runs we obtain an approximate value for the
additional wire delay between two gate level (twire). The data (and control) path clock period
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SoCT Lecture Notes SoC Logic Design Recap
is given by the SDH signal hierarchy level
(2.5 Gbps) and the data path width (16 bit). The total delay of the combinatorial logic levels
is: ΣTlogic = N x ( tgate + twire ). Resolving the equation for N reveals N < 28.52, or Nmax = 28
Questions:
a) Is this plenty or little levels to implement complex sequential or combinato-
rial functions?
b) Synthesis runs show that the actual maximum logic levels of all FSMs un-
der consideration is Nsynth = 14. This means we have a margin of a factor big-
ger than two in timing. Potentially, we could half the data path and double the
frequency of the FSMs. Would this be a good deal?
Answers:
a) By experience, 10 – 15 levels of logic between successive register stages
allow implementing already quite complex logic and sequential functions. 28
levels are by all measures plenty of levels.
b) Theoretically, one could consider doubling the frequency of the FSM as the
remaining margin is still a bit more than half a clock cycle (0.52 X 6.43 ns). On
the other hand, 3.3 ns total margin are already consumed when the wire delay
estimation was by as little as 2.5% too optimistic. Therefore, it is a considera-
ble risk to half the data path width w and double the clock frequency f p in this
example.
Practically speaking, a sequential depth N means that one has N levels of logic available to
implement the function modules between two register stages in the data path of the ATM
payload processor, and N levels of logic to implement the logic for the transition conditions
in the control path FSMs.
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