SoC Logic Design Recap
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Outline
• Combinatorial Logic
Transistor synthesis for combinatorial logic
• Sequential Logic
Registers, latches, flip-flops
Finite state machine design
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Combinatorial Logic
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Simple Static CMOS Logic Gates
VDD A A
NOR Z
B B Z
Z A NAND NOR
A Z A B Z
Z
B 1 0 0 1
B D
1 0 1 0
NAND 1 1 0 0
0 1 1 0
gnd
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All logic functions can
DeMorgan Rule be expressed with
NAND or NOR
NAND NOR
NOT
AND
OR
basic gate NOT AND OR NAND NOR
output expression A‘ AB A+B (AB)‘ (A+B)‘
NAND represent. (AA)‘ (AB)‘‘ (A‘B‘)‘ (AB)‘ (A‘B‘)‘‘
NOR represent. (A+A)‘ (A‘+B‘)‘ (A+B)‘‘ (A‘+B‘)‘‘ (A+B)‘
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Generic Model of Static CMOS
VDD
A1
...
An
Z
C
gnd
NAND NOR
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Systematic Static CMOS Logic Design
Example Function: Z=AB+C VDD
CMOS always inverts => add
extra inverter: Z=AB+C A B
Start at the output and find a
way through n-MOSFETS to C
ground: Z
serial for AND (AB)
parallel for OR (C)
A C
Draw the way to Vdd by using the dual
n-network and p-MOSFETS
B
If everything is done right, there will never be
gnd
a conducting path between Vdd and gnd.
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Register Transfer Blocks: Arithmetic
Numerous applications are based on mathematical operations
Digital Filters
Processor Arithmetic Logic Units
implemented as combinatorial
A logic circuitry
multi-bit register / x
storage elements B
+ Y
C
Y=AxB+C
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Sequential Logic
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Basic Register / Storage Element
In CMOS we can store a 0 or a 1 in a loop of two inverters:
Vdd
01 Q
01 10
10 Q Q Q
01 10
One inverter drives the input of the other
Only outputs so far (how boring!) gnd
impossible to externaly drive a node without short-
circuit
Q x=1: Q Q
We need to open the loop to set a Q
specific logic value: x=0: Vdd Q
x
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R = Reset
CMOS Latch / R-S-Latch S = Set
Q
Q
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CMOS Latch / D-Latch
1 R
e
D e Q
0
1 DQ
Q
D Q
D
1 e Q
S
1 D
Enable signal e
Level-controlled <=> Latch 0 Q
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CMOS Flip-flop
c c Q
e Q e Q Q
D Q
D D DQ Q
c
(alternatively)
Master Slave
c Q
Clock edge-controlled (c) <=> flip-flop D
Most important sequential element
Used in (almost all) sychronous digital circuits - Q
Used as register banks
Counter, shift registers
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CMOS Flip-flop
clk
e Q e Q Q
D D q DQ Q
Master Slave
clk
clk
D
q
Q
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CMOS Flip-flop
clk
e Q e Q Q
D D q DQ Q q can only
Master Slave propagate a new
value to Q at
beginning of Slave
clk latch enablement
(clk = 1).
clk During clk = 1,
D q cannot change its
value any more.
q
Clock-edge
Q sensitive behavior.
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CMOS Flip-flop
clk
e Q e Q Q
D D q DQ Q
Master Slave
clk
clk
D
q
Q
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Flip-flop Timing
c
D Q
50%
t tc2q
D c
Flip-flop characteristics:
50% setup-time: Data must be stable
t tsetup before clock edge
tsetup thold hold-time: Data must be stable for
thold after clock edge
Q
clock-to-output delay: Data will be
visible at output tc2q after clock
edge
t
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Synchronous Sequential Logic
Tlogic,min
Tlogic,max
• Timing Constraints: Minimum Tclk = maximum f
Setup constraint: Tclk > Tc2q + Tlogic,max + Tsetup is bounded by the Setup
Hold constraint: Tc2q + Tlogic,min > Thold constraint of sequential
logic!
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Hold Time Constraint
R1 R2
D1 Q1 D2 Q2
Assumption:
2 different registers, R1 and R2
Tlogic, min
R1 is faster (shorter Tc2q, Tstp, Thld) than R2
clk
clk
Tc2q, R1
Every Tlogic, min < Tcrit causes a Hold Time violation
Q1 X since:
Tcrit Tc2q,R1 + Tlog,min < Thld,R2
D2 XXX X X XX
Thld, R2
Q2 X
Tc2q, R2
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