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LM397
SNOS977F – MAY 2001 – REVISED MAY 2016

LM397 Single General-Purpose Voltage Comparator

1 Features 3 Description
1• TA = 25°C. Typical Values Unless Otherwise The LM397 device is a single voltage comparator
Specified. with an input common mode that includes ground.
The LM397 is designed to operate from a single 5-V
• 5-Pin SOT-23 Package to 30-V power supply or a split power supply. Its low
• Industrial Operating Range −40°C to +85°C supply current is virtually independent of the
• Single or Dual Power Supplies magnitude of the supply voltage.
• Wide Supply Voltage Range 5 V to 30 V The LM397 features an open-collector output stage.
• Low Supply Current 300 µA This allows the connection of an external resistor at
the output. The output can directly interface with TTL,
• Low Input Bias Current 7 nA CMOS and other logic levels, by tying the resistor to
• Low Input Offset Current ±1 nA different voltage levels (level translator).
• Low Input Offset Voltage ±2 mV The LM397 is available in the space-saving 5-Pin
• Response Time 440 ns (50-mV Overdrive) SOT-23 package and is pin-compatible to TI’s TL331,
• Input Common-Mode Voltage 0 to VS – 1.5 V a single differential comparator.

2 Applications Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
• A/D Converters
LM397 SOT-23 (5) 2.90 mm × 1.60 mm
• Pulse, Square-Wave Generators
(1) For all available packages, see the orderable addendum at
• Peak Detector the end of the data sheet.
• Industrial Applications
Typical Circuit
VS

RPULL-UP
VIN -
R1
VO

R3
R2

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM397
SNOS977F – MAY 2001 – REVISED MAY 2016 [Link]

Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 7
2 Applications ........................................................... 1 7.4 Device Functional Modes.......................................... 8
3 Description ............................................................. 1 8 Application and Implementation .......................... 9
4 Revision History..................................................... 2 8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 11
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 11
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 11
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 11
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 12
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 12
6.6 Typical Characteristics .............................................. 6 11.2 Trademarks ........................................................... 12
7 Detailed Description .............................................. 7 11.3 Electrostatic Discharge Caution ............................ 12
7.1 Overview ................................................................... 7 11.4 Glossary ................................................................ 12
7.2 Functional Block Diagram ......................................... 7 12 Mechanical, Packaging, and Orderable
Information ........................................................... 12

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (October 2015) to Revision F Page

• Changed incorrect Pin Functions table entries. Pins 4 and 5 were swapped. ....................................................................... 3

Changes from Revision D (March 2013) to Revision E Page

• Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 8

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[Link] SNOS977F – MAY 2001 – REVISED MAY 2016

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View

-
1 5
VIN VS

2
GND

3 4
+
VIN OUTPUT

Pin Functions
PIN
TYPE DESCRIPTION
NAME NO.
GND 2 P Ground
OUTPUT 4 O Output
VIN+ 3 I Noninverting Input
VIN– 1 I Inverting Input
VS 5 P Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VIN differential 30 30 V
Supply voltages ±15 30 V
Voltage at input pins −0.3 30 V
Junction temperature (3) 150 ºC
Soldering Infrared or Convection (20 sec.) 235 ºC
information Wave Soldering (10 sec.) 260 ºC
Storage Temperature, Tstg −65 150 ºC

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) ±2000
V(ESD) V
discharge Machine Model (1) (2) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.3 Recommended Operating Conditions

MIN MAX UNIT
Supply voltage, VS 5 30 V
(1)
Temperature −40 85 °C

(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

LM397
THERMAL METRIC (1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance (2) 186 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 92.8 °C/W
RθJB Junction-to-board thermal resistance 38.9 °C/W
ψJT Junction-to-top characterization parameter 5.6 °C/W
ψJB Junction-to-board characterization parameter 38.4 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

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[Link] SNOS977F – MAY 2001 – REVISED MAY 2016

6.5 Electrical Characteristics

Unless otherwise specified, all limits are ensured for TA = 25°C, VS = 5 V, V− = 0 V, VCM = V+/2 = VO.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
VS = 5 V to 30 V, TA = 25ºC 2 7
VOS Input offset voltage mV
VO = 1.4 V, VCM = 0 V At the temperature extremes 10
TA = 25ºC 1.6 50
IOS Input offset current VO = 1.4 V, VCM = 0 V nA
At the temperature extremes 250
TA = 25ºC 10 250
IB Input bias current VO = 1.4 V, VCM = 0 V nA
At the temperature extremes 400
RL = open, VS = 5 V 0.25 0.7
IS Supply current mA
RL = open, VS = 30 V 0.3 2
IO Output sink current VIN+ = 1 V, VIN− = 0 V, VO = 1.5 V 6 13 mA
VIN+ = 1 V, VIN− = 0 V, VO = 5 V 0.1 nA
ILEAKAGE Output leakage current
VIN = 1 V, VIN = 0 V, VO = 30 V
+ −
1 µA
IO = −4 mA, VIN+ = 0 V, TA = 25ºC 180 400
VOL Output voltage low mV
VIN− = 1 V At the temperature extremes 700
Common-mode input TA = 25ºC 0 VS – 1.5
VCM VS = 5 V to 30 V (3) V
voltage range At the temperature extremes 0 VS – 2
VS = 15 V, VO = 1.4 V to 11.4 V,
AV Voltage gain 120 V/mV
RL > = 15 kΩ connected to VS
Input overdrive = 5 mV
900
Propagation delay RL = 5.1 kΩ connected to 5 V, CL = 15 pF
tPHL ns
(high to low) Input overdrive = 50 mV
250
RL = 5.1 kΩ connected to 5 V, CL = 15 pF
Input Overdrive = 5 mV
940 µs
Propagation delay RL = 5.1 kΩ connected to 5 V, CL = 15 pF
tPLH
(low to high) Input overdrive = 50 mV
440 ns
RL = 5.1 kΩ connected to 5 V, CL = 15 pF

(1) All limits are specified by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(3) The input common-mode voltage of either input should not be permitted to go below the negative rail by more than 0.3V. The upper end
of the common-mode voltage range is VS – 1.5 V at 25°C.

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SNOS977F – MAY 2001 – REVISED MAY 2016 [Link]

6.6 Typical Characteristics

TA = 25°C. Unless otherwise specified.

0.45 14
-40°C
0.4 -40°C
12

INPUT BIAS CURRENT (nA)

SUPPLY CURRENT (mA)

0.35 25°C 25°C

10
0.3
85°C
85°C 8
0.25

0.2 6
0.15
4
0.1

0.05 2

0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

Figure 1. Supply Current vs Supply Voltage Figure 2. Input Bias Current vs Supply Current
1 2.5
R -40°C
OUTPUT SATURATION VOLTAGE (V)

-40 C R
25 C

INPUT OFFSET VOLTAGE (mV)

85°C

25°C
0.1 R
85 C

1.5

0.01 1 2
1 10 100 0 5 10 15 25 30
0
OUTPUT SINK CURRENT (mA) SUPPLY VOLTAGE (V)

Figure 3. Output Saturation Voltage vs Output Sink Current Figure 4. Input Offset Voltage vs Supply Voltage

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7 Detailed Description

7.1 Overview
A comparator is often used to convert an analog signal to a digital signal. The comparator compares an input
voltage (VIN) at the noninverting pin to the reference voltage (VREF) at the inverting pin. If VIN is less than VREF
the output (VO) is low (VOL). However, if VIN is greater than VREF, the output voltage (VO) is high (VOH). Refer to
Figure 6.
VS
VOLTS

VO
RPULL-UP
VREF -
VO
VIN VREF
+

- TIME
V
VIN
Figure 5. Basic Comparator

Figure 6. Basic Comparator Output

7.2 Functional Block Diagram

VS

VIN+
OUTPUT
VIN-

GND

7.3 Feature Description

7.3.1 Input Stage
The LM397 has a bipolar input stage. The input common-mode voltage range is from 0 to (VS – 1.5 V).

7.3.2 Output Stage

The LM397 has an open-collector grounded-emitter NPN output transistor for the output stage. This requires an
external pullup resistor connected between the positive supply voltage and the output. The external pullup
resistor should be high enough resistance so to avoid excessive power dissipation. In addition, the pullup resistor
should be low enough resistance to enable the comparator to switch with the load circuitry connected. Because it
is an open-collector output stage, several comparator outputs can be connected together to create an OR’ing
function output. With an open collector, the output can be used as a simple SPST switch to ground. The amount
of current which the output can sink is approximately 10 mA. When the maximum current limit is reached, the
output transistor will saturate and the output will rise rapidly (Figure 7).

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Feature Description (continued)

5
-40°C

OUTPUT SATURATION VOLTAGE (V)

4.5
85°C
4

3.5
25°C
3
2.5

2
1.5
1
0.5
0
1 10 100
OUTPUT SINK CURRENT (mA)

Figure 7. Output Saturation Voltage vs Output Sink Current

7.4 Device Functional Modes

7.4.1 Hysteresis
The basic comparator configuration may oscillate or produce a noisy output if the applied differential input is near
the input offset voltage of the comparator. This tends to occur when the voltage on the input is equal or very
close to the other input voltage. Adding hysteresis can prevent this problem. Hysteresis creates two switching
thresholds (one for the rising input voltage and the other for the falling input voltage). Hysteresis is the voltage
difference between the two switching thresholds. When both inputs are nearly equal, hysteresis causes one input
to effectively move quickly pass the other. Thus, effectively moving the input out of region that oscillation may
occur.
For an inverting configured comparator, hysteresis can be added with a three resistor network and positive
feedback. When input voltage (VIN) at the inverting node is less than non-inverting node (VT), the output is high.
The equivalent circuit for the three resistor network is R1 in parallel with R3 and in series with R2. The lower
threshold voltage VT1 is calculated by Equation 1:
VT1 = ((VS R2) / (((R1 R3) / (R1 + R3)) + R2)) (1)
When VIN is greater than VT, the output voltage is low. The equivalent circuit for the three resistor network is R2
in parallel with R3 and in series with R1. The upper threshold voltage VT2 is calculated by Equation 2:
VT2 = VS ((R2 R3) / (R2 + R3)) / (R1 + ((R2 R3) / (R2 + R3))) (2)
The hysteresis is defined in Equation 3:
ΔVIN = VT1 – VT2 (3)

VO

VT2 VT1

0 VIN

Figure 8. Inverting Configured Comparator - LM397

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[Link] SNOS977F – MAY 2001 – REVISED MAY 2016

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

LM397 will typically be used to compare a single signal to a reference or two signals against each other.

8.2 Typical Application

VS

RPULL-UP
VIN -
R1
VO

R3
R2

Figure 9. Inverting Comparator With Hysteresis

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 1 as the input parameters.

Table 1. Design Parameters

DESIGN
EXAMPLE VALUE
PARAMETER
Input voltage range 0 V to VS – 1.5 V
Supply voltage 5 V to 30 V
Logic supply voltage
5 V to 30 V
(RPULLUP voltage)
Output current
1 µA to 20 mA
(VLOGIC/RPULLUP)
Input overdrive
100 mV
voltage
Reference voltage 5.5 V

8.2.2 Detailed Design Procedure

When using TL331 in a general comparator application, determine the following:
• Input voltage range
• Minimum overdrive voltage
• Output and drive current

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[Link] Input Voltage Range

When choosing the input voltage range, the input common mode voltage range (VCM) must be taken in to
account. If temperature operation is above or below 25°C the VCM can range from 0 V to VS – 1.5 V. This limits
the input voltage range to as high as VS – 1.5 V and as low as 0 V. Operation outside of this range can yield
incorrect comparisons.
Below is a list of input voltage situation and their outcomes:
1. When both IN– and IN+ are both within the common mode range:
(a) If IN– is higher than IN+ and the offset voltage, the output is low and the output transistor is sinking
current
(b) If IN– is lower than IN+ and the offset voltage, the output is high impedance and the output transistor is
not conducting
2. When IN– is higher than common mode and IN+ is within common mode, the output is low and the output
transistor is sinking current
3. When IN+ is higher than common mode and IN– is within common mode, the output is high impedance and
the output transistor is not conducting
4. When IN– and IN+ are both higher than common mode, the output is low and the output transistor is sinking
current

[Link] Minimum Overdrive Voltage

Overdrive Voltage is the differential voltage produced between the positive and negative inputs of the comparator
over the offset voltage. To make an accurate comparison; the overdrive voltage should be higher than the input
offset voltage. Overdrive voltage can also determine the response time of the comparator, with the response time
decreasing with increasing overdrive.

[Link] Output and Drive Current

Output current is determined by the pullup resistance (RPULLUP) and VS voltage. The output current will produce a
output low voltage (VOL) from the comparator. In which VOL is proportional to the output current. Use Figure 3 to
determine VOL based on the output current. The output current can also effect the transient response.

8.2.3 Application Curves

10 10
OUTPUT (V)

VS = 5V, RPULL-UP = 5.1k: TO VS VS = 5V, RPULL-UP = 5.1k: TO VS

OUTPUT (V)

8 8
CL = 15pF TO GND CL = 15pF TO GND
6 6

4 4
VOD = 5mV 2
2
VOD = 50mV
0 0 VOD = 5mV
10 VOD = 50mV 10
0 0
INPUT (mV)
INPUT (mV)

50 50
0 0
OVERDRIVE - OVERDRIVE
-
50 VOLTAGE (VOD) 50 VOLTAGE (VOD)
-100 -100
200 400 800 1200 1400 2000 200 400 800 1200 1400 2000
TIME (ns) TIME (ns)

Figure 10. Response Time for Various Input Overdrives – Figure 11. Response Time for Various Input Overdrives –
tPHL tPLH

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9 Power Supply Recommendations

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.

10 Layout

10.1 Layout Guidelines

Comparators are very sensitive to input noise. For best results, maintain the following layout guidelines:
• Use a printed-circuit-board (PCB) with a good, unbroken low-inductance ground plane. Proper grounding (use
of ground plane) helps maintain specified performance of the LM397.
• To minimize supply noise, place a decoupling capacitor (0.1-μF ceramic, surface-mount capacitor) as close
as possible to VS as shown in Figure 12.
• On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from the output.
• Solder the device directly to the PCB rather than using a socket.
• For slow-moving input signals, take care to prevent parasitic feedback. A small capacitor (1000 pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to propagation delay when the impedance is low. Run the top-side ground plane between the
output and inputs.
• Run the ground pin ground trace under the device up to the bypass capacitor, shielding the inputs from the
outputs.

10.2 Layout Example

Run the input traces
as far away from
the supply lines Use low-ESR, ceramic
as possible bypass capacitor
VS+

IN+ IN+
V+ GND
VS± or GND
V±

OUT OUT

IN- IN-

GND

Only needed for

dual-supply
operation

Figure 12. Comparator Board Layout

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11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 21-May-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LM397MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 C397
LM397MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 C397
& no Sb/Br)
LM397MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 85 C397
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 21-May-2016

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 20-Dec-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM397MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM397MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM397MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 20-Dec-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM397MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LM397MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LM397MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/C 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/C 04/2017

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/C 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/D 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/D 11/2018

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/D 11/2018

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
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