CISC vs RISC

Instruction Set Architectures

1. CISC — Complex Instruction Set Computing
CISC (Complex Instruction Set Computing) is a processor design philosophy in which the CPU is
built to execute a large number of instructions, many of which are complex and capable of
performing multiple low-level operations — such as a memory load, arithmetic operation, and
memory store — all within a single instruction.

The name itself captures the key idea: the instruction set is rich, varied, and complex. In CISC
architectures, the hardware is designed to be powerful so that the software (programs and compilers)
does not have to work as hard.

Historical Background
CISC emerged in the 1960s and 1970s when computer memory was extremely expensive and
programmers wrote code directly in assembly language. To reduce the number of instructions a
program needed (thereby saving memory), chip designers packed as much functionality as possible
into each instruction.

The guiding philosophy was: "let the hardware do the work." IBM's System/360 (1964) and Intel's
x86 family (1978 onward) are classic CISC architectures.

How CISC Works

Inside a CISC processor, complex instructions are interpreted using a technique called microcode, a
hidden layer of even simpler internal instructions that the CPU uses internally to carry out each
visible instruction. Think of microcode as a translation layer: when you issue a complex
MULTIPLY-AND-STORE instruction, the CPU internally breaks it into many tiny micro-steps that
the hardware actually executes.
Key Features of CISC
• Large number of instructions -sometimes hundreds of different operations
• Variable-length instructions -some take 1 byte, others up to 15 bytes (in x86)
• Multiple clock cycles per instruction -complex instructions may take 5, 10 or more cycles
• Any instruction can directly read from or write to memory during execution
• Fewer general-purpose registers -because instructions work directly with memory
• Programs require fewer lines of assembly code
• Many addressing modes: direct, indirect, indexed, relative, and more

CISC Code Example (x86 Assembly — Intel/AMD)

In x86 CISC, a single instruction can perform multiple operations simultaneously:

; Task: Multiply the value at memory address [BX] by 10 and store result

; CISC (x86) — ONE instruction does load + multiply + store

IMUL EAX, [BX], 10 ; Load from [BX], multiply by 10, result in EAX

; Add value in memory directly to a register (accesses memory inside instruction)

ADD AX, [1000h] ; Fetches from memory AND adds — all in ONE instruction
 ; Load from memory in a single step
MOV AX, [SI] ; Load from memory address in SI into register AX

The IMUL instruction above does three things at once: accesses memory, performs multiplication,
and stores the result all within one instruction. This is the hallmark of CISC design.
Real-World CISC Processors

• Intel x86 / x86-64: Intel Core i3, i5, i7, i9, Xeon (used in desktops, laptops, servers)
• AMD Ryzen, AMD EPYC: AMD's modern CISC processors competing directly with Intel
• IBM System/360 and descendants: Mainframe computing

2. RISC -Reduced Instruction Set Computing

RISC (Reduced Instruction Set Computing) is a processor design in which the CPU is built with a
small set of simple, highly optimized instructions, where each instruction performs exactly one basic
operation and completes in a single clock cycle.

The viewpoint is: "keep the hardware simple and let the compiler (software) do the work." By
simplifying the instruction set, the hardware becomes faster, simpler, easier to pipeline, and more
power-efficient.

Historical Background
RISC was developed in the 1980s through research at IBM, the University of California at Berkeley
(the RISC-I project by David Patterson), and Stanford University (the MIPS project by John
Hennessy). Researchers analyzed real programs and discovered that approximately 80% of execution
time was spent on just 20% of the available instructions and those were all simple ones.

They concluded that complex hardware for rarely-used instructions was a waste of silicon and power.
Instead, a small, fast, deeply-pipelined processor could outperform a complex CISC chip. This
insight led to the RISC revolution of the 1980s and 90s.

How RISC Works — Load/Store Architecture

RISC processors use a design called load/store architecture. This means only two specific instruction
types can access memory:
• LOAD: copies a value from memory into a register
• STORE: copies a value from a register back to memory

All other instructions such as arithmetic, logic, and comparisons work exclusively on data already in
registers. This simplifies the hardware massively and makes pipelining very efficient. Unlike CISC,
there is no microcode; instructions are executed directly by hardwired logic circuits.
Key Features of RISC
• Small, uniform instruction set - typically 50 to 150 instructions
• Fixed-length instructions -all instructions are the same size (commonly 32 bits)
• One clock cycle per instruction -enables predictable, fast execution
• Only LOAD and STORE instructions touch memory
 • Large number of general-purpose registers - often 32 or more
• Simple hardwired control -no microcode layer needed
• Highly pipeline-friendly -one instruction per stage, every stage the same length
• More lines of code needed per task, but each executes extremely fast

2.5 RISC Code Example (MIPS Assembly)

In MIPS RISC, the same multiply-and-store task requires separate instructions for each step:

; Task: Multiply the value at memory address in R2 by 10 and store result

; RISC (MIPS) FOUR separate instructions needed:

LW R1, 0(R2) ; Step 1 - LOAD: fetch value from memory into register R1
ADDI R3, R0, 10 ; Step 2 -load the constant 10 into register R3
MUL R4, R1, R3 ; Step 3 - multiply R1 x R3, result goes into R4
SW R4, 0(R2) ; Step 4 -STORE: write result from R4 back to memory

; Key rule: memory is only touched by LW (Load Word) and SW (Store Word)
; All arithmetic operates only on registers

Compare this to the CISC example - four instructions versus one. However, each RISC instruction
completes in exactly one clock cycle and all four can be pipelined (overlapped), making the overall
throughput very high.
RISC Code Example (ARM Assembly — Smartphones & Apple M Chips)
; Add two numbers from memory and save result
LDR R0, [R1] ; Load first value from memory address in R1
LDR R2, [R3] ; Load second value from memory address in R3
ADD R4, R0, R2 ; Add them -operates only on registers
STR R4, [R5] ; Store result into memory at address in R5

Real-World RISC Processors

• ARM Cortex series: Used in virtually every smartphone -Apple A-series, Qualcomm
Snapdragon
• Apple M1 / M2 / M3 / M4: ARM-based chips in MacBooks and iPads - outperform many
x86 chips
• MIPS: Used in routers, embedded systems, early PlayStation consoles
• RISC-V: Open-source ISA, rapidly growing in IoT, embedded, and custom chip design
• SPARC: Used in Sun/Oracle servers
• PowerPC: Used in IBM servers and older Apple Macs (pre-Intel era)
•
Pipelining -The Key Advantage of RISC

Pipelining means overlapping the execution stages of multiple instructions so the CPU is always
doing useful work on several instructions simultaneously. Think of a factory assembly line, while
one car is being painted, another is being assembled, and another is being inspected.
Because RISC instructions are all the same fixed size and take the same number of cycles, they flow
through the pipeline smoothly with no stalls:

Clock cycle: 1 2 3 4 5 6
Instruction 1: Fetch Decode Exec Mem Write
Instruction 2: Fetch Decode Exec Mem Write
Instruction 3: Fetch Decode Exec Mem Write
Instruction 4: Fetch Decode Exec Mem Write

All four instructions complete in 8 cycles instead of 4x5 = 20 cycles

In CISC, variable-length instructions mean the processor often cannot tell where the next instruction
starts until it finishes the current one. This creates pipeline stalls and dramatically reduces
throughput.

4. CISC vs RISC - Comparison

Feature CISC RISC
Complex Instruction Set Reduced Instruction Set
Computing Computing
DESIGN PHILOSOPHY
Core idea Hardware does as much as Compiler (software) does the
possible. One instruction = work. One instruction = one
many operations. operation.
Philosophy coined 1960s–70s: save memory by 1980s: maximize speed by
packing power into instructions simplifying each instruction
Instruction count Large - hundreds of different Small - typically 50–150
instructions available carefully optimized instructions
INSTRUCTION FORMAT
Instruction length Variable length - 1 to 15 bytes Fixed length- all instructions
per instruction (in x86) same size, typically 32 bits
Instruction One instruction can: load + One instruction does exactly one
complexity compute + store simultaneously basic operation
Clock Multiplecycles-complex Ideally 1 cycle per instruction -
cycles/instruction instructions may take 5–20 predictable and fast
cycles
Addressing modes Many: direct, indirect, indexed, Few: usually only register and
base+offset, relative, and more base+offset (register indirect)
MEMORY & REGISTERS
Memory access Any instruction can read/write Only LOAD and STORE
memory during execution instructions access memory; all
Feature CISC RISC
Complex Instruction Set Reduced Instruction Set
Computing Computing
others use registers only
Number of registers Fewer - x86 originally had only More -ARM and MIPS typically
8 general-purpose registers have 32 general-purpose
registers
Register usage Instructions operate on memory All arithmetic works on registers
operands directly- fewer - more registers reduce memory
registers needed traffic
HARDWARE DESIGN
Implementation Uses microcode - a hidden layer Uses hardwired control -
of micro-instructions inside the instructions executed directly by
chip logic circuits; no microcode
Hardware complexity High -large decoders, microcode Low - simple, regular hardware;
ROM, complex control logic easier to verify and manufacture
Pipelining Difficult-variable-length Easy -uniform instruction size
instructions cause stalls in the enables efficient, deep
pipeline pipelining
Transistor usage Many transistors spent on More transistors available for
microcode and complex decode registers, cache, and functional
logic units
SOFTWARE & PERFORMANCE
Code size Smaller-fewer instructions Larger - more instructions
needed per task; saves memory needed; one CISC instruction
space may need 4–6 RISC ones
Compiler complexity Simpler compiler - can map More complex compiler -must
high-level code to single break operations into multiple
instructions simple steps
Execution speed Slower per instruction; Faster per instruction; executes
compensated by doing more per many simple instructions
instruction extremely rapidly
Power consumption Higher - complex hardware Lower - simple hardware is
draws more power; less suited to power-efficient; dominant in
mobile smartphones and IoT
REAL-WORLD INFORMATION
Processor examples Intel x86/x86-64 (Core i-series, ARM (Cortex, Apple M1-M4),
Feature CISC RISC
Complex Instruction Set Reduced Instruction Set
Computing Computing
Xeon), AMD Ryzen, AMD MIPS, RISC-V, SPARC,
EPYC, IBM System/360 PowerPC
Typical use cases Desktop computers, laptops, Smartphones, tablets, embedded
servers — where power is systems, IoT, wearables, modern
readily available high-perf CPUs
Origin 1960s–70s — designed when 1980s — emerged from
memory was expensive and academic research at Berkeley
assembly was common (RISC-I) and Stanford (MIPS)

The Modern Reality - Lines Have Blurred

The CISC vs RISC divide is no longer as sharp as it was in the 1980s and 90s. Two major
developments explain why:
Modern CISC Chips Use RISC Internally
Starting with the Intel Pentium Pro (1995), Intel's x86 processors began translating complex CISC
instructions into small, RISC-like micro-operations (micro-ops) internally before executing them.
The programmer still sees the CISC instruction set, but the silicon underneath behaves like a RISC
machine.

This approach gives Intel and AMD the best of both worlds: backward compatibility with decades of
x86 software, combined with the speed and pipelining benefits of RISC-style execution. AMD does
the same in all its modern processors.

RISC Chips Have Grown More Sophisticated

ARM chips originally a model of RISC simplicity have gained powerful extensions: NEON (SIMD
multimedia), SVE (scalable vector extensions), TrustZone (security), and more. Apple's M-series
chips, which are ARM-based RISC processors, now outperform many x86 server chips in
performance per watt, achieving what was thought impossible just a decade ago.
RISC design principles dominate modern chip design at the hardware level, but CISC instruction
sets remain dominant on the software level for desktop and server computing due to decades of
backward compatibility. When you buy a laptop or PC today, you are using a CISC instruction set
(x86) executed on RISC-like internal hardware.