國立清華大學 電機工程學系(碩博士班)

106 學年度 第一學期

EE6250 超大型積體電路測試 — 期中考題 (Nov. 9, 2017)

1. (20%) Answer the following questions.

(a) What does a neighborhood pattern sensitive fault commonly used in memory mean? Explain in one
or two sentences. (5%)
A cell is affected by when its neighbors form a pattern.
(b) Is it true that it takes only one test vector to detect an transistor open fault? (5%)
No.
(c) In the 9-valued D-algorithm for ATPG, logic symbol ‘u/1’ actually corresponds to two 5-valued
symbols. One of them is ‘1’. What is the other? (5%)
D’ (or 0/1)
(d) A detection probability of a stuck-at fault by one test vector is denoted as p, then what is the
detection probability of this fault by applying n test vectors from a statistical point of view? We
assume that every test vector has the same detection probability for this fault. (5%)
1-(1-p)n

2. (10%) Complete the deductive fault simulation as indicated in the figure below to derive the final
detected faults by the current test pattern. The fault-free values are {a=0, b=0, c=0, d=1, Z=0}.The fault
lists at signals a, b, and d are denoted as La, Lb, and Ld, respectively. Express your answer of the final
detected faults as a symbolic formula in terms of La, Lb, Ld and some union, complement, or intersession
operators as discussed in class. Note that a fault not contained in any of La, Lb, Ld need not be considered.

a
0 0
0
b c
Test Circuit 0
Z
Pattern

d 1

Lz = La．Lb．Ld

3. (10%) Answer the following questions about test time.

(a) Why is test time important in VLSI testing? (5%)
Longer test time means higher test cost.
(b) Consider the full-scan methodology for a circuit with 99 flip-flops. A combinational ATPG program
produces 123 vectors to fully test the logic. Compute the minimum number of clock cycles needed to
apply these vectors, assuming that the system clock and test clock are the same and there is only one
scan chain. (Note: the scan-in operation and scan-out operation are assumed to be overlapped
whenever possible. In this calculation, we also ignore the cycles for applying the PI sub-vectors and
the cycles for observing the PO sub-vectors.) (5%)
123*(99+1)+99 = 12399 clocks

4. (10%) Consider a 3-input logic circuit with the Boolean function as f(a, b, c) = ab + bc. Answer the
following two questions.
(a) What are the faulty functions under a stuck-at-0 and a stuck-at-1, respectively? The resulting
functions are Boolean functions of variables b and c. Denote the answers as fa=0(b, c) and fa=1(b, c),
respectively. (5%)
fa=0(b, c) = bc , fa=1(b, c) = b

1
 (b) What is the value combination of signals b and c that can make the Boolean difference df/da become
true? (5%)
df/da = fa=0(b, c)⊕fa=1(b, c) = bc’
5. (10%) Derive a test vector for G stuck-at-1 fault in the circuit shown below.

A F

G
B

Z
C E
D

(A, B, C, D) = (1, 1, 1, 0)
6. (10%) Complete the following diagram of a Level-Sensitive Scan Design. The normal-mode operation
(which captures the data from D to Q) is controlled by two-phase non-overlapping clocks {CK1CK3},
while the scan-mode operation (which captures the data SD to Q) is controlled by two-phase
non-overlapping clocks {CK2CK3}.

D Q

CK1 Circuit
SD To be Added
CK2

CK3

7. (15%) Answer the following questions involved in the D-algorithm.

(a) In the left figure, is it true that signal C is called a J-frontier? (5%)
No.
(b) In the left figure, what can you imply about the value of signal C after signal A is assigned value D' ?
(5%)
C=0
(c) In the right figure, what signal can be implied after signal G is assigned to logic '1'? (5%)

A F
A
C B 1 G
D
B
C E
Note: A signal without any value label is assumed to have a value of ‘X’
Note: Signal value D means ‘1/0’ in the D-algorithm.

B=1

2
8. (15%) Consider an NAND gate with three input signals, {x1, x2, x3} and an output signal y. The
controllability probability of the inputs are: {CY0(x1) = 0.1, CY1(x1) = 0.9}, {CY0(x2) = 0.5, CY1(x2)
= 0.5}, and {CY0(x3) = 0.8, CY1(x3) = 0.2}. Answer the following questions.
(a) What binary value is controlling if applied to the input of an NAND gate? Note that a controlling
value is a binary value when applied to an input of a logic gate can unilaterally decide its output
value, regardless of the values of the other side inputs. (5%)
0
(b) List all stuck-at faults associated with its input/output signals after the fault collapsing process,
assuming both the equivalence and dominance relations are used. (5%)

x1, x2, x3 y x1 x2 x3 y x1 x2 x3 y
sa1 sa1 sa1 sa1 sa0 sa0 sa0 sa0
000 1 0
001 1 0
010 1 0
011 1 0 0
100 1 0
101 1 0 0
110 1 0 0
111 0 1 1 1 1
Fault Equivalence: (y s-a-1, x1 s-a-0, x2 s-a-0, x3 s-a-0) answer one of all.
Fault Dominance: (y s-a-0 > x1 s-a-1), (y s-a-0 > x2 s-a-1), (y s-a-0 > x3 s-a-1)

(c) During the PODEM algorithm, if the objective is to set the NAND gate’s output to logic ‘0’ at a
moment when the values of its inputs are {x1 = 1, x2 = 'X', x3 = 'X'}, then which one of its inputs
should be selected for the backtrace? (5%)
It is several unsolved problems, so we need to choose the hardest one firstly. x3 should be resolve,
because of the lowest controllability of 1.