參考解答
National Tsing Hua University, Taiwan
EE-6250 超大型積體電路測試 (VLSI Testing)
(Closed-Book) Midterm Exam., Spring Semester, 2024 (April 15, 2024)
(七大題，總分 100 分)
1. (15%) Answer the following question briefly.
(a) In IC testing, what does CP refer to? How does it differ from FT? (5%) ➔ CP means Chip Probing
or Wafer-Level Sorting. CP is the testing of bare dies, while FT is the testing of packaged ICs.
(b) What does the acronym “dppm” stand for in IC testing? (5%) ➔ Defective Parts Per Million
(c) What is the aging mechanism when excessive current flows through an interconnect for an extended
time? What kind of damage is likely to occur? (5%) ➔ The interconnect may become open
gradually due to Electromigration
2. (15%) Answer the following question briefly.
(a) Consider an inverter with the input signal u and output signal w. The pMOS transistor is assumed
to be stuck-open. How can you test this fault by applying logic value at u and observing at w? (Hint:
you need a two-cycle test.) (5%) ➔ u is applied to two logic values in sequence, (1→0)
(b) Consider a NOR gate, q=(m+n)’. There are in total 6 stuck-at faults {q/0, q/1, m/0, m/1, n/0, n/1}.
After applying the fault equivalence relation, {m/1, n/1, q/0} are merged as an equivalence class.
After applying the fault dominance relation, what can you say about the remaining three faults?
Which stuck-at-fault can be further dropped? (5%) ➔ Easy fault is dropped, so, q/1 is dropped.
(c) Consider the following PLA fault. If the circled cross-point is missing, what is its equivalent fault in
the gate-level circuit? Note that you have to mark the fault site clearly and provide its stuck-at
value. (5%)
A B C f1 f2 A B C
stuck-at-0
f1
f2
Missing Cross-Point
3. (15%) Consider a circuit realizing a Boolean function, f = (ab + a’d + c’).
(a) Derive the Boolean difference df/db. Express your answer as a Boolean expression in terms of {a, c,
d}. (Note: you can derive it by any technique) (5%) ➔ df/db=ac
(b) If the output of the AND gate produces (a’d) is denoted as g in the two-level logic circuit
representing f. Derive the Boolean difference df/dg (5%). ➔ df/dg=a’c + b’c
(c) Derive the only 3-valued test pattern for g stuck-at-0 fault. (5%) (Hint: the result you have derived
for question (b) is useful). (5%) ➔ Test Set for g-stuck-at-0 is (a, b, c, d)=(0, x, 1, 1)
4. (15%) Answer the following questions during the execution of the D-algorithm.
(a) A gate, say g1, is included in a D-frontier at the moment. What can we say about the values
assigned to the inputs and output of this gate? (5%) ➔ Some input(s) are D or D’, but the output is
x.
(b) A gate, say g2, is included in a J-frontier at the moment. What can you say about values assigned to
the inputs and output of this gate at this moment? (5%) ➔ They are not justified yet, meaning the
1
inputs cannot imply the value of the output yet.
(c) Under what conditions that the D-algorithm declare a test pattern has been successfully found for a
given target fault? (5%) ➔ (1) We have seen a fault effect at some primary output, (2) and the
J-frontier is empty.
5. (15%) Consider the following implication problem during the D-algorithm using techniques discussed in
class.
(a) Consider a 3-input NAND gate, K=(abc)’. At a moment, if (a, b, c, K) is assigned (1, x, x, 0). What
should we imply when signal b is further assigned to 1. (5%) ➔ c is implied to ‘1’.
(b) Consider a 2-input OR gate, L=ef. At a moment, if (e, f, L)=(D, x, x). What should we imply when
signal f is further assigned to D’. (5%) ➔ L is implied to ‘1’.
(c) What we can imply when P is assigned to 0? (5%) ➔ B is implied to ‘0’.
1 D
A
x
B x
P
x
x
C E
6. (15%) Consider the 9-value D-algorithm.
(a) What two logic values of {0, 1, D’, D, x} does u/1 contain? (5%) ➔ {D’, 1}
(b) Consider a NOR gate in the circuit under test, z=(a+b)’. If there is a fault effect D at b to be passed
to z, what value needs to be assigned to the side input a? (5%) ➔ a is assigned to ‘u/0’
(c) At the end of the pattern generation for a target fault, the primary input assignments are (x1, x2, x3,
x4, x5) = (D’, 1, 1, u/0, u/0). Then, what is the final test pattern derived? (5%) ➔ (x1, x2, x3, x4, x5)
= (0, 1, 1, 0, 0)
7. (10%) Consider the following problems.
(a) Consider the full-scan methodology for a circuit with 99 flip-flops. A combinational ATPG program
produces 123 vectors to fully test the logic. Compute the minimum number of clock cycles needed to
apply these vectors, assuming that the system clock and test clock are the same and there is only one
scan chain. (Note: the scan-in operation and scan-out operation are assumed to be overlapped
whenever applicable. In this calculation, we also ignore the cycles for applying the PI sub-vectors
and the cycles for observing the PO sub-vectors.) (5%) ➔ (99+1)*123 + 99 = 12399 cycles
(b) Complete the following diagram of a Level-Sensitive Scan Design. The normal-mode operation
(which captures the data from D to Q) is controlled by two-phase non-overlapping clocks
{CK1→CK3}, while the scan-mode operation (which captures the data SD to Q) is controlled by
two-phase non-overlapping clocks {CK2→CK3}. (5%)
D Q
CK1 Circuit
SD To be Added
CK2
CK3
2
D Q1 Q2
CK1
SD
CK2
CK3