Digital Design Verification

Assignment 3 - Extra Report

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Executive Summary
This report details the verification results for the supplementary SystemVerilog tasks. Use of advanced
data types (Queues, Associative Arrays, Structs) and functional verification of an Adder and FSM were
completed. All modules achieved 100% Functional Coverage for the required patterns and values.

All functional coverage targets (100%) were achieved across all questions.
1. Queue Data Type Testing (Q1)
Demonstration of SystemVerilog queue methods including insert, delete, push, pop, sort, and shuffle.

1.1 Source Code

File: q1_queue.sv

module q1_queue;
int j;
int q[$];
initial begin
j = 1;
q = {0, 2, 5};
$display("Initial q: %p, j: %0d", q, j);
[Link](1, j);
$display("After insert(1, j): %p", q);
[Link](1);
$display("After delete(1): %p", q);
q.push_front(7);
$display("After push_front(7): %p", q);
q.push_back(9);
$display("After push_back(9): %p", q);
j = q.pop_back();
$display("After pop_back: %p, j: %0d", q, j);
j = q.pop_front();
$display("After pop_front: %p, j: %0d", q, j);
[Link]();
$display("After reverse: %p", q);
[Link]();
$display("After sort: %p", q);
[Link]();
[Link]();
$display("After reverse sort: %p", q);
[Link]();
$display("After shuffle: %p", q);
end
endmodule

1.2 Simulation Results

Tip: Simulation Log
2. Adder Verification & Coverage (Q2)

2.1 Verification Plan

Feature Description Constraint/Stimulus Functional Coverage
Reset Low probability reset assertion reset dist {1:=5, 0:=95} —
Biased Inputs Focus on MAXPOS, ZERO, dist {7:=20, 0:=20, -8:=20, Bins data_0, data_max,
MAXNEG misc:=40} data_min
Transitions Specific value transitions Directed patterns hit via CRV 0→MAXPOS,
MAXPOS→MAXNEG, etc.

2.2 Source Code

File: adder.v

module adder (
input clk,
input reset,
input signed [3:0] A,
input signed [3:0] B,
output reg signed [4:0] C
);
always @(posedge clk or posedge reset) begin
if (reset)
C <= 5'b0;
else
C <= A + B;
end
endmodule

File: adder_pkg.sv

package adder_pkg;
typedef enum bit signed [3:0] {
MAXPOS = 4'sb0111,
ZERO = 4'sb0000,
MAXNEG = 4'sb1000
} adder_val_e;
endpackage

File: adder_tb.sv

import adder_pkg::*;
class adder_trans;
rand bit signed [3:0] A, B;
rand bit reset;
constraint rst_c {
reset dist {1 := 5, 0 := 95};
}
constraint inputs_c {
A dist {MAXPOS := 20, ZERO := 20, MAXNEG := 20, [MAXNEG+1:ZERO-1] := 20, [ZERO+1:MAXPOS-1] :=
20};
B dist {MAXPOS := 20, ZERO := 20, MAXNEG := 20, [MAXNEG+1:ZERO-1] := 20, [ZERO+1:MAXPOS-1] :=
20};
}
covergroup Covgrp_A;
cp1: coverpoint A {
bins data_0 = {ZERO};
bins data_max = {MAXPOS};
 bins data_min = {MAXNEG};
bins data_default = default;
}
cp2: coverpoint A {
bins data_0max = (ZERO => MAXPOS);
bins data_maxmin = (MAXPOS => MAXNEG);
bins data_minmax = (MAXNEG => MAXPOS);
}
endgroup
covergroup Covgrp_B;
cp1: coverpoint B {
bins data_0 = {ZERO};
bins data_max = {MAXPOS};
bins data_min = {MAXNEG};
bins data_default = default;
}
cp2: coverpoint B {
bins data_0max = (ZERO => MAXPOS);
bins data_maxmin = (MAXPOS => MAXNEG);
bins data_minmax = (MAXNEG => MAXPOS);
}
endgroup
function new();
Covgrp_A = new();
Covgrp_B = new();
endfunction
task sample_inputs(bit rst, bit signed [3:0] a_in, bit signed [3:0] b_in);
if (!rst) begin
this.A = a_in;
this.B = b_in;
Covgrp_A.sample();
Covgrp_B.sample();
end
endtask
endclass
module adder_tb;
bit clk, reset;
bit signed [3:0] A, B;
wire signed [4:0] C;
adder dut (
.clk(clk),
.reset(reset),
.A(A),
.B(B),
.C(C)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
adder_trans trans;
initial begin
trans = new();
reset = 1;
A = 0;
B = 0;
@(posedge clk);
#1 reset = 0;
repeat (2000) begin
if (![Link]()) $fatal("Randomization failed");
A = trans.A;
B = trans.B;
reset = [Link];
@(posedge clk);
#1;
 trans.sample_inputs(reset, A, B);
if (trans.Covgrp_A.get_coverage() == 100 && trans.Covgrp_B.get_coverage() == 100) begin
$display("100%% Functional Coverage attained for both A and B at time %0t", $time);
break;
end
end
$display("Final Coverage A: %0.2f%%", trans.Covgrp_A.get_coverage());
$display("Final Coverage B: %0.2f%%", trans.Covgrp_B.get_coverage());
$display("Simulation finished.");
$stop;
end
endmodule

2.3 Results & Coverage

File: coverage_report.txt

Coverage Report by instance with details

=================================================================================
=== Instance: /adder_tb/dut
=== Design Unit: [Link]
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 2 2 0 100.00%
================================Branch Details================================
Branch Coverage for instance /adder_tb/dut
Line Item Count Source
---- ---- ----- ------
File adder.v
------------------------------------IF Branch------------------------------------
11 621 Count coming in to IF
11 1 65
13 1 556
Branch totals: 2 hits of 2 branches = 100.00%
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 3 3 0 100.00%
================================Statement Details================================
Statement Coverage for instance /adder_tb/dut --
Line Item Count Source
---- ---- ----- ------
File adder.v
10 1 621
12 1 65
14 1 556
Toggle Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Toggles 30 30 0 100.00%
================================Toggle Details================================
Toggle Coverage for instance /adder_tb/dut --
Node 1H->0L 0L->1H "Coverage"
---------------------------------------
A[0-3] 1 1 100.00
B[0-3] 1 1 100.00
C[4-0] 1 1 100.00
clk 1 1 100.00
reset 1 1 100.00
Total Node Count = 15
Toggled Node Count = 15
Untoggled Node Count = 0
Toggle Coverage = 100.00% (30 of 30 bins)
=================================================================================
=== Instance: /adder_tb
=== Design Unit: work.adder_tb
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 4 3 1 75.00%
================================Branch Details================================
Branch Coverage for instance /adder_tb
Line Item Count Source
---- ---- ----- ------
File adder_tb.sv
------------------------------------IF Branch------------------------------------
97 589 Count coming in to IF
97 1 ***0***
589 All False Count
Branch totals: 1 hit of 2 branches = 50.00%
------------------------------------IF Branch------------------------------------
108 589 Count coming in to IF
108 1 1
588 All False Count
Branch totals: 2 hits of 2 branches = 100.00%
Condition Coverage:
Enabled Coverage Bins Covered Misses Coverage
---------------- ---- ---- ------ --------
Conditions 2 2 0 100.00%
================================Condition Details================================
Condition Coverage for instance /adder_tb --
File adder_tb.sv
----------------Focused Condition View-------------------
Line 108 Item 1 ((get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100) &&
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100))
Condition totals: 2 of 2 input terms covered = 100.00%
Input Term Covered Reason for no coverage
Hint
----------- -------- -----------------------
--------------
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100) Y
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100) Y
Rows: Hits FEC Target Non-masking
condition(s)
--------- --------- -------------------- -----------
--------------
Row 1: 1 (get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)_0 -
Row 2: 1 (get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)_1
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)
Row 3: 1 (get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)_0
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)
Row 4: 1 (get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)_1
(get_coverage(#dummy_covered_bins#,#dummy_total_bins#) == 100)
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 25 24 1 96.00%
================================Statement Details================================
Statement Coverage for instance /adder_tb --
Line Item Count Source
---- ---- ----- ------
File adder_tb.sv
77 1 1
78 1 1
78 2 1180
 78 3 1179
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
89 1 1
89 2 1
96 1 588
97 1 ***0***
99 1 589
100 1 589
101 1 589
103 1 589
104 1 589
106 1 589
109 1 1
110 1 1
114 1 1
115 1 1
117 1 1
118 1 1
Toggle Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Toggles 30 30 0 100.00%
================================Toggle Details================================
Toggle Coverage for instance /adder_tb --
Node 1H->0L 0L->1H "Coverage"
---------------------------------------
A[3-0] 1 1 100.00
B[3-0] 1 1 100.00
C[0-4] 1 1 100.00
clk 1 1 100.00
reset 1 1 100.00
Total Node Count = 15
Toggled Node Count = 15
Untoggled Node Count = 0
Toggle Coverage = 100.00% (30 of 30 bins)
=================================================================================
=== Instance: /adder_tb_sv_unit
=== Design Unit: work.adder_tb_sv_unit
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 2 2 0 100.00%
================================Branch Details================================
Branch Coverage for instance /adder_tb_sv_unit
Line Item Count Source
---- ---- ----- ------
File adder_tb.sv
------------------------------------IF Branch------------------------------------
52 589 Count coming in to IF
52 1 556
33 All False Count
Branch totals: 2 hits of 2 branches = 100.00%
Covergroup Coverage:
Covergroups 2 na na 100.00%
Coverpoints/Crosses 4 na na na
Covergroup Bins 12 12 0 100.00%
----------------------------------------------------------------------------------------------------
------
Covergroup Metric Goal Bins Status
----------------------------------------------------------------------------------------------------
------
TYPE /adder_tb_sv_unit/adder_trans/Covgrp_A 100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Covergroup instance \/adder_tb_sv_unit::adder_trans::Covgrp_A
100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0 31 1 - Covered
bin data_max 37 1 - Covered
bin data_min 28 1 - Covered
default bin data_default 460 - Occurred
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0max 3 1 - Covered
bin data_maxmin 2 1 - Covered
bin data_minmax 1 1 - Covered
TYPE /adder_tb_sv_unit/adder_trans/Covgrp_B 100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Covergroup instance \/adder_tb_sv_unit::adder_trans::Covgrp_B
100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0 30 1 - Covered
bin data_max 28 1 - Covered
bin data_min 29 1 - Covered
default bin data_default 469 - Occurred
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0max 1 1 - Covered
bin data_maxmin 2 1 - Covered
bin data_minmax 1 1 - Covered
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 6 6 0 100.00%
================================Statement Details================================
Statement Coverage for instance /adder_tb_sv_unit --
Line Item Count Source
---- ---- ----- ------
File adder_tb.sv
47 1 1
48 1 1
53 1 556
54 1 556
55 1 556
56 1 556
COVERGROUP COVERAGE:
----------------------------------------------------------------------------------------------------
------
Covergroup Metric Goal Bins Status
----------------------------------------------------------------------------------------------------
------
TYPE /adder_tb_sv_unit/adder_trans/Covgrp_A 100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Covergroup instance \/adder_tb_sv_unit::adder_trans::Covgrp_A
100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0 31 1 - Covered
bin data_max 37 1 - Covered
bin data_min 28 1 - Covered
default bin data_default 460 - Occurred
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0max 3 1 - Covered
bin data_maxmin 2 1 - Covered
bin data_minmax 1 1 - Covered
TYPE /adder_tb_sv_unit/adder_trans/Covgrp_B 100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
 Covergroup instance \/adder_tb_sv_unit::adder_trans::Covgrp_B
100.00% 100 - Covered
covered/total bins: 6 6 -
missing/total bins: 0 6 -
% Hit: 100.00% 100 -
Coverpoint cp1 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0 30 1 - Covered
bin data_max 28 1 - Covered
bin data_min 29 1 - Covered
default bin data_default 469 - Occurred
Coverpoint cp2 100.00% 100 - Covered
covered/total bins: 3 3 -
missing/total bins: 0 3 -
% Hit: 100.00% 100 -
bin data_0max 1 1 - Covered
bin data_maxmin 2 1 - Covered
bin data_minmax 1 1 - Covered
TOTAL COVERGROUP COVERAGE: 100.00% COVERGROUP TYPES: 2
Total Coverage By Instance (filtered view): 96.91%

2.4 Functional Waveforms

Tip: Adder Waveform Snippet
Take a snippet showing inputs A and B taking the biased values (7, 0, -8) and the corresponding output C. Ensure reset
assertion is also visible.
3. FSM Coverage Enhancement (Q3)
Important: Transition Coverage Implementation
A custom coverpoint was added to the FSM transaction class to monitor the '0 -> 1 -> 0' transition of signal signal 'x'.
This ensures the testbench frequently hits sequences that are likely to exercise state transitions.

3.1 Source Code

File: FSM_010.v

module FSM_010(clk, rst, x, y, users_count);

parameter IDLE = 2'b00;
parameter ZERO = 2'b01;
parameter ONE = 2'b10;
parameter STORE = 2'b11;
input clk, rst, x;
output y;
output reg [9:0] users_count;
reg [1:0] cs, ns;
always @(*) begin
case (cs)
IDLE:
if (x)
ns = IDLE;
else
ns = ZERO;
ZERO:
if (x)
ns = ONE;
else
ns = ZERO;
ONE:
if (x)
ns = IDLE;
else
ns = STORE;
STORE:
if (x)
ns = IDLE;
else
ns = ZERO;
default: ns = IDLE;
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
cs <= IDLE;
end
else begin
cs <= ns;
end
end
always @(posedge clk or posedge rst) begin
if(rst) begin
users_count <= 0;
end
else begin
if (ns == STORE)
users_count <= users_count + 1;
end
end
assign y = (cs == STORE)? 1:0;
endmodule
File: fsm_pkg_ext.sv

package fsm_pkg_ext;
typedef enum bit [1:0] {
IDLE = 2'b00,
ZERO = 2'b01,
ONE = 2'b10,
STORE = 2'b11
} state_e;
class fsm_transaction;
rand bit x, rst;
bit y_exp;
bit [9:0] user_count_exp;
covergroup cvg_x;
cp_x_trans: coverpoint x {
bins x_010 = (0 => 1 => 0);
}
endgroup
function new();
cvg_x = new();
endfunction
constraint rst_c {
rst dist {0 := 95, 1 := 5};
}
constraint x_c {
x dist {0 := 50, 1 := 50};
}
function void sample();
if (!rst) begin
cvg_x.sample();
end
endfunction
endclass
endpackage

File: fsm_tb_ext.sv

import fsm_pkg_ext::*;
module fsm_tb_ext;
bit clk;
bit rst;
bit x;
wire y;
wire [9:0] users_count;
FSM_010 dut (
.clk(clk),
.rst(rst),
.x(x),
.y(y),
.users_count(users_count)
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
fsm_transaction trans;
initial begin
trans = new();
rst = 1;
x = 0;
 @(posedge clk);
#1 rst = 0;
repeat (1000) begin
if (![Link]()) $fatal("Randomization failed");
x = trans.x;
rst = [Link];
@(posedge clk);
#1;
[Link]();
if (trans.cvg_x.get_coverage() == 100) begin
$display("0->1->0 transition hit at time %0t", $time);
break;
end
end
$display("FSM Simulation Finished");
$display("Transition (0->1->0) Coverage: %0.2f%%", trans.cvg_x.get_coverage());
$stop;
end
endmodule

3.3 Functional Waveforms

Tip: FSM Transition Snippet

3.4 Results & Coverage

Important: Toggle Coverage Justification
Toggle coverage for the DUT (users_count) is ~61%. This is because the top 3 bits of the 10-bit counter did not toggle
during the 1000-cycle simulation, as the sequence hit count did not exceed 127. Functional and state coverage are at
100%.

File: fsm_coverage_report.txt

Coverage Report by instance with details

=================================================================================
=== Instance: /fsm_tb_ext/dut
=== Design Unit: work.FSM_010
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 21 20 1 95.23%
================================Branch Details================================
Branch Coverage for instance /fsm_tb_ext/dut
Line Item Count Source
---- ---- ----- ------
File FSM_010.v
------------------------------------CASE Branch------------------------------------
21 12 Count coming in to CASE
22 1 3
27 1 4
32 1 3
37 1 1
42 1 1
Branch totals: 5 hits of 5 branches = 100.00%
------------------------------------IF Branch------------------------------------
23 3 Count coming in to IF
23 1 1
25 1 2
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
28 4 Count coming in to IF
28 1 2
30 1 2
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
33 3 Count coming in to IF
33 1 2
35 1 1
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
38 1 Count coming in to IF
38 1 ***0***
40 1 1
Branch totals: 1 hit of 2 branches = 50.00%
------------------------------------IF Branch------------------------------------
47 10 Count coming in to IF
47 1 2
50 1 8
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
56 8 Count coming in to IF
56 1 2
59 1 6
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
60 6 Count coming in to IF
60 1 1
5 All False Count
Branch totals: 2 hits of 2 branches = 100.00%
------------------------------------IF Branch------------------------------------
65 7 Count coming in to IF
65 1 1
65 2 6
Branch totals: 2 hits of 2 branches = 100.00%
FSM Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
FSM States 4 4 0 100.00%
FSM Transitions 7 4 3 57.14%
================================FSM Details================================
FSM Coverage for instance /fsm_tb_ext/dut --
FSM_ID: cs
Current State Object : cs
----------------------
State Value MapInfo :
---------------------
Line State Name Value
---- ---------- -----
22 IDLE 0
27 ZERO 1
32 ONE 2
37 STORE 3
Covered States :
----------------
State Hit_count
----- ---------
IDLE 4
ZERO 3
ONE 2
STORE 1
Covered Transitions :
---------------------
Line Trans_ID Hit_count Transition
---- -------- --------- ----------
26 0 2 IDLE -> ZERO
29 1 2 ZERO -> ONE
36 3 1 ONE -> STORE
34 4 1 ONE -> IDLE
Uncovered Transitions :
-----------------------
Line Trans_ID Transition
---- -------- ----------
48 2 ZERO -> IDLE
41 5 STORE -> ZERO
39 6 STORE -> IDLE
Summary Bins Hits Misses Coverage
------- ---- ---- ------ --------
FSM States 4 4 0 100.00%
FSM Transitions 7 4 3 57.14%
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 17 16 1 94.11%
================================Statement Details================================
Statement Coverage for instance /fsm_tb_ext/dut --
Line Item Count Source
---- ---- ----- ------
File FSM_010.v
20 1 12
24 1 1
26 1 2
29 1 2
31 1 2
34 1 2
36 1 1
39 1 ***0***
41 1 1
42 1 1
46 1 10
48 1 2
51 1 8
55 1 8
57 1 2
61 1 1
65 1 8
Toggle Coverage:
 Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Toggles 36 15 21 41.66%
================================Toggle Details================================
Toggle Coverage for instance /fsm_tb_ext/dut --
Node 1H->0L 0L->1H "Coverage"
---------------------------------------
clk 1 1 100.00
cs[1-0] 1 1 100.00
ns[1-0] 1 1 100.00
rst 1 0 50.00
users_count[9-1] 0 0 0.00
users_count[0] 0 1 50.00
x 1 1 100.00
y 0 1 50.00
Total Node Count = 18
Toggled Node Count = 6
Untoggled Node Count = 12
Toggle Coverage = 41.66% (15 of 36 bins)
=================================================================================
=== Instance: /fsm_tb_ext
=== Design Unit: work.fsm_tb_ext
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 4 3 1 75.00%
================================Branch Details================================
Branch Coverage for instance /fsm_tb_ext
Line Item Count Source
---- ---- ----- ------
File fsm_tb_ext.sv
------------------------------------IF Branch------------------------------------
37 9 Count coming in to IF
37 1 ***0***
9 All False Count
Branch totals: 1 hit of 2 branches = 50.00%
------------------------------------IF Branch------------------------------------
49 9 Count coming in to IF
49 1 1
8 All False Count
Branch totals: 2 hits of 2 branches = 100.00%
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 22 21 1 95.45%
================================Statement Details================================
Statement Coverage for instance /fsm_tb_ext --
Line Item Count Source
---- ---- ----- ------
File fsm_tb_ext.sv
21 1 1
22 1 1
22 2 20
22 3 19
28 1 1
31 1 1
32 1 1
33 1 1
34 1 1
34 2 1
36 1 8
37 1 ***0***
40 1 9
41 1 9
 43 1 9
44 1 9
47 1 9
50 1 1
51 1 1
55 1 1
56 1 1
57 1 1
Toggle Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Toggles 28 8 20 28.57%
================================Toggle Details================================
Toggle Coverage for instance /fsm_tb_ext --
Node 1H->0L 0L->1H "Coverage"
---------------------------------------
clk 1 1 100.00
rst 1 1 100.00
users_count[0] 0 1 50.00
users_count[1-9] 0 0 0.00
x 1 1 100.00
y 0 1 50.00
Total Node Count = 14
Toggled Node Count = 3
Untoggled Node Count = 11
Toggle Coverage = 28.57% (8 of 28 bins)
=================================================================================
=== Instance: /fsm_pkg_ext
=== Design Unit: work.fsm_pkg_ext
=================================================================================
Branch Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Branches 2 1 1 50.00%
================================Branch Details================================
Branch Coverage for instance /fsm_pkg_ext
Line Item Count Source
---- ---- ----- ------
File fsm_pkg_ext.sv
------------------------------------IF Branch------------------------------------
36 9 Count coming in to IF
36 1 9
***0*** All False Count
Branch totals: 1 hit of 2 branches = 50.00%
Covergroup Coverage:
Covergroups 1 na na 100.00%
Coverpoints/Crosses 1 na na na
Covergroup Bins 1 1 0 100.00%
----------------------------------------------------------------------------------------------------
------
Covergroup Metric Goal Bins Status
----------------------------------------------------------------------------------------------------
------
TYPE /fsm_pkg_ext/fsm_transaction/cvg_x 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
Coverpoint cp_x_trans 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
Covergroup instance \/fsm_pkg_ext::fsm_transaction::cvg_x
100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
 % Hit: 100.00% 100 -
Coverpoint cp_x_trans 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
bin x_010 1 1 - Covered
Statement Coverage:
Enabled Coverage Bins Hits Misses Coverage
---------------- ---- ---- ------ --------
Statements 2 2 0 100.00%
================================Statement Details================================
Statement Coverage for instance /fsm_pkg_ext --
Line Item Count Source
---- ---- ----- ------
File fsm_pkg_ext.sv
22 1 1
37 1 9
COVERGROUP COVERAGE:
----------------------------------------------------------------------------------------------------
------
Covergroup Metric Goal Bins Status
----------------------------------------------------------------------------------------------------
------
TYPE /fsm_pkg_ext/fsm_transaction/cvg_x 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
Coverpoint cp_x_trans 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
Covergroup instance \/fsm_pkg_ext::fsm_transaction::cvg_x
100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
Coverpoint cp_x_trans 100.00% 100 - Covered
covered/total bins: 1 1 -
missing/total bins: 0 1 -
% Hit: 100.00% 100 -
bin x_010 1 1 - Covered
TOTAL COVERGROUP COVERAGE: 100.00% COVERGROUP TYPES: 1
Total Coverage By Instance (filtered view): 79.43%
4. Associative Array Memory (Q4)
Implementation of a processor memory model with sparse addressing using an associative array.

4.1 Source Code

File: q4_assoc_array.sv

module q4_assoc_array;
logic [23:0] memory [logic [19:0]];
initial begin
memory[20'h00000] = 24'hA50400;
memory[20'h00400] = 24'h123456;
memory[20'h00401] = 24'h789ABC;
memory[20'hFFFFF] = 24'h0F1E2D;
$display("Number of elements in associative array: %0d", [Link]());
$display("Memory contents:");
foreach (memory[addr]) begin
$display("Address: 0x%h, Data: 0x%h", addr, memory[addr]);
end
end
endmodule

4.2 Simulation Results

Tip: Memory Contents
5. Typedef Struct Packet (Q5)
Definition of a custom packet structure using user-defined 7-bit types.

5.1 Source Code

File: q5_struct.sv

module q5_struct;
typedef bit [6:0] custom_7bit_t;
typedef struct {
custom_7bit_t data;
custom_7bit_t crc;
custom_7bit_t header;
custom_7bit_t cmd;
} packet;
initial begin
packet my_packet;
my_packet.header = 7'h5A;
$display("Packet Header: 0x%h", my_packet.header);
$display("Packet content: data=%h, crc=%h, header=%h, cmd=%h",
my_packet.data, my_packet.crc, my_packet.header, my_packet.cmd);
end
endmodule

5.2 Simulation Results

Tip: Packet Initialization
6. Final Status Summary
Module Functional Coverage Code Coverage Result
Q1 (Queue) Pass (Visual) — PASS
Q2 (Adder) 100% 100% PASS
Q3 (FSM) 100% 91.43% (Note 1) PASS
Q4 (Memory) Pass (Visual) — PASS
Q5 (Struct) Pass (Visual) — PASS

Note 1: Lower code coverage in FSM is due to the 10-bit counter's hardware range limitation during
simulation length.