Digital Logic Design

Complete Study Guide

Sequential Logic & Important Topics

● SR · D · JK Flip-Flops ● NAND / NOR Latches

● Counters (Sync / Async / Up / Down) ● 7-Segment Display
● BCD Adder · Comparator · Encoder · Decoder · MUX/DEMUX

Beginner → Advanced Truth & State Tables Logisim Steps MCQs & Viva

Exam Preparation Mentor | DLD Complete Notes | 2024–2025

DLD Study Guide — Sequential Logic & Important Topics | Page 1

 ■ Table of Contents

Chapter 1 — Sequential Circuits — Introduction

■ 1.1 Definition & Classification
■ 1.2 Combinational vs Sequential
■ 1.3 Clock Signals & Timing

Chapter 2 — Latches
■ 2.1 SR (NOR) Latch
■ 2.2 NAND Latch

Chapter 3 — Flip-Flops
■ 3.1 SR Flip-Flop
■ 3.2 D Flip-Flop
■ 3.3 JK Flip-Flop
■ 3.4 Characteristic & Excitation Tables
■ 3.5 Timing Diagrams

Chapter 4 — Practical Circuits

■ 4.1 Burglar Alarm Circuit
■ 4.2 Key-Based System

Chapter 5 — Counters
■ 5.1 Asynchronous (Ripple) Counter
■ 5.2 Synchronous Counter
■ 5.3 Up / Down Counter
■ 5.4 Mod-N Counter Design
■ 5.5 7-Segment Display Interface

Chapter 6 — Combinational Circuits

■ 6.1 BCD Adder
■ 6.2 Comparator
■ 6.3 BCD to Excess-3 Converter
■ 6.4 Decoder
■ 6.5 Encoder
■ 6.6 Multiplexer (MUX)
■ 6.7 Demultiplexer (DEMUX)

Chapter 7 — Exam Preparation

■ 7.1 MCQs (All Topics)
■ 7.2 Viva Questions

DLD Study Guide — Sequential Logic & Important Topics | Page 2

■ 7.3 Short & Long Questions
■ 7.4 Important Formulas & Rules

DLD Study Guide — Sequential Logic & Important Topics | Page 3

 Chapter 1 — Sequential Circuits: Introduction

1.1 Definition
A Sequential Circuit is a digital circuit whose output depends on both the current inputs AND
the past history (state) of the circuit. Unlike combinational circuits, sequential circuits contain
memory elements (flip-flops or latches) that store the current state.

OUTPUT = f(Current Inputs, Current State)

NEXT STATE = g(Current Inputs, Current State)

1.2 Combinational vs Sequential — Comparison

Feature Combinational Circuit Sequential Circuit

Memory No memory Has memory (FF/Latch)

Output depends on Current inputs only Inputs + Past state

Clock Not required Usually required

Examples Adder, MUX, Decoder Counter, Register, FF

Feedback No feedback Feedback present

Design complexity Simpler More complex

1.3 Classification of Sequential Circuits

A) Based on Timing
• Synchronous Sequential Circuits: All flip-flops are triggered by a common clock signal.
State changes occur only at clock edges (rising or falling).
• Asynchronous Sequential Circuits: Flip-flops change state immediately when inputs
change. No common clock. Faster but harder to design (race conditions possible).

B) Based on Output
• Mealy Machine: Output depends on current state AND current inputs. Output can change
asynchronously with inputs. Generally fewer states needed.
• Moore Machine: Output depends ONLY on the current state. Output changes only at clock
edges. More stable, easier to design.

Property Mealy Machine Moore Machine

Output depends on State + Input State only

Number of states Fewer More

Output changes With input changes Only at clock edge

Circuit complexity More complex Simpler output logic

1.4 Clock Signal & Edge Triggering

A clock signal is a periodic square wave that synchronises all flip-flops in a synchronous circuit.

DLD Study Guide — Sequential Logic & Important Topics | Page 4

 • Rising Edge (Positive Edge): Transition from 0 → 1 (most common trigger)
• Falling Edge (Negative Edge): Transition from 1 → 0
• Level Triggered: Responds to HIGH or LOW level (used in latches)

Timing Diagram Terms:

tsetup — Setup time: input must be stable BEFORE clock edge
thold — Hold time: input must remain stable AFTER clock edge
tpd — Propagation delay: time from clock edge to output change
T — Clock period; f = 1/T = clock frequency

1.5 State Diagram, State Table & Characteristic Equation

Every sequential circuit can be described using:
• State Diagram: Graphical representation. Circles = states, Arrows = transitions, Labels on
arrows = input/output (Mealy) or just input (Moore).
• State Table: Tabular form listing Present State, Input, Next State, Output.
• Characteristic Equation: Boolean equation describing Q(next) in terms of Q(present) and
inputs.

DLD Study Guide — Sequential Logic & Important Topics | Page 5

 Chapter 2 — Latches (SR NOR & NAND)

2.1 SR (NOR) Latch

The SR Latch is the most basic memory element. It has two cross-coupled NOR gates with
inputs S (Set) and R (Reset) and outputs Q and Q' (complement).

Circuit Description
• Gate 1 (NOR): Inputs = R, Q' → Output = Q
• Gate 2 (NOR): Inputs = S, Q → Output = Q'
• Q and Q' are fed back as inputs to each other (cross-coupling).

SR NOR Latch — Truth Table

S R Q (next) Q' (next) Operation

0 0 Q (no change) Q' (no change) Hold / Memory

0 1 0 1 RESET (Q=0)

1 0 1 0 SET (Q=1)

1 1 0 0 FORBIDDEN (Invalid)

■■ S=1, R=1 is FORBIDDEN in SR NOR Latch because both outputs become 0

simultaneously, violating Q ≠ Q'. The final state is unpredictable when inputs return to 00.

Characteristic Equation
Q(next) = S + R'·Q (with constraint: S·R = 0)

2.2 NAND Latch (Active-LOW SR Latch)

The NAND Latch uses two cross-coupled NAND gates. The inputs S' and R' are active LOW (0
= active, 1 = inactive).

NAND Latch — Truth Table

S' (S-bar) R' (R-bar) Q (next) Q' (next) Operation

1 1 Q (no change) Q' (no change) Hold / Memory

1 0 0 1 RESET (Q=0)

0 1 1 0 SET (Q=1)

0 0 1 1 FORBIDDEN (Invalid)

■■ S'=0, R'=0 is FORBIDDEN in NAND Latch — both outputs become 1 simultaneously.

NOR vs NAND Latch Comparison

Feature NOR Latch NAND Latch

Gates used NOR gates NAND gates

Active level Active HIGH (1=active) Active LOW (0=active)

Forbidden state S=R=1 S'=R'=0

DLD Study Guide — Sequential Logic & Important Topics | Page 6

 Normal state (hold) S=R=0 S'=R'=1

Preferred use Positive logic systems Negative logic / practical ICs

2.3 Logisim Implementation — SR NOR Latch

Step-by-Step:
• 1. Open Logisim → New Circuit → Name it 'SR_NOR_Latch'
• 2. Place two NOR gates (Gates library) on the canvas
• 3. Add two Input pins: label them S and R
• 4. Add two Output pins: label them Q and Q_bar
• 5. Connect: NOR Gate 1 inputs ← R and Q_bar output; output → Q
• 6. Connect: NOR Gate 2 inputs ← S and Q output; output → Q_bar
• 7. This creates the cross-coupling (feedback) loop
• 8. Simulate: Set S=1,R=0 → Q becomes 1. Set S=0,R=0 → Q holds 1
• 9. Test all input combinations and verify truth table
■ In Logisim, when you first run the circuit, you may see 'Error' or 'X'. Set S=1,R=0 first to initialize
the latch to a known state.

DLD Study Guide — Sequential Logic & Important Topics | Page 7

 Chapter 3 — Flip-Flops (SR, D, JK)

3.1 SR Flip-Flop (Clocked SR Latch)

An SR Flip-Flop is a clocked version of the SR latch. It has an additional Clock (CLK) input. The
flip-flop changes state only on the active clock edge.
• Inputs: S (Set), R (Reset), CLK (Clock)
• Outputs: Q, Q' (complement)

SR Flip-Flop — Characteristic Table

CLK S R Q(t+1) Comment

↑ 0 0 Q(t) No Change (Hold)

↑ 0 1 0 Reset

↑ 1 0 1 Set

↑ 1 1 ? Forbidden / Undefined

Characteristic Equation: Q(t+1) = S + R'·Q(t) [S·R = 0 required]

SR Flip-Flop — Excitation Table

The excitation table tells us what inputs S and R are needed to achieve a desired state transition
(used in sequential circuit design).

Q(t) (Present) Q(t+1) (Next) S (required) R (required)

0 0 0 X (don't care)

0 1 1 0

1 0 0 1

1 1 X (don't care) 0

3.2 D Flip-Flop (Data / Delay Flip-Flop)

The D Flip-Flop eliminates the forbidden state problem of the SR flip-flop by connecting S
through an inverter to R (so R = S'). It has a single data input D.
• Inputs: D (Data), CLK
• Outputs: Q, Q'
• Key property: Output Q follows input D after every clock edge.

D Flip-Flop — Characteristic Table

CLK D Q(t+1) Comment

↑ 0 0 Output resets to 0

↑ 1 1 Output sets to 1

Characteristic Equation: Q(t+1) = D

D Flip-Flop — Excitation Table

DLD Study Guide — Sequential Logic & Important Topics | Page 8

 Q(t) Q(t+1) D (required)

0 0 0

0 1 1

1 0 0

1 1 1

■ D Excitation is always equal to Q(t+1) — the simplest excitation table! D flip-flops are used in shift
registers, data storage, pipeline registers.

3.3 JK Flip-Flop (Universal Flip-Flop)

The JK Flip-Flop is the most versatile flip-flop. It eliminates the forbidden state by adding
feedback. When J=K=1, the output toggles (Q flips to Q').
• Inputs: J (set-like), K (reset-like), CLK
• Outputs: Q, Q'
• J=K=1 → Toggle (flip the output) — this is the key feature!

JK Flip-Flop — Characteristic Table

CLK J K Q(t+1) Comment

↑ 0 0 Q(t) No Change (Hold)

↑ 0 1 0 Reset

↑ 1 0 1 Set

↑ 1 1 Q'(t) Toggle

Characteristic Equation: Q(t+1) = J·Q'(t) + K'·Q(t)

JK Flip-Flop — Excitation Table

Q(t) Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

■■ JK is called 'Universal' because it can be configured as SR, D, or T flip-flop. JK with

J=K=1 is also called a T (Toggle) Flip-Flop.

3.4 Flip-Flop Comparison Summary

Property SR FF D FF JK FF

Inputs S, R D J, K

Forbidden state S=R=1 None None

Toggle operation No No J=K=1

Char. equation S+R'Q D JQ'+K'Q

DLD Study Guide — Sequential Logic & Important Topics | Page 9

 Excitation complexity Medium Simplest Complex

Main use Basic memory Registers Counters, Freq dividers

3.5 Timing Diagram Description (JK Flip-Flop Example)

A timing diagram shows how Q changes with each clock edge based on J and K values:
• Clock: Regular square wave (↑ = rising edge trigger)
• Assume initial Q = 0
• Cycle 1: J=1, K=0 → SET → Q becomes 1
• Cycle 2: J=0, K=0 → HOLD → Q stays 1
• Cycle 3: J=1, K=1 → TOGGLE → Q becomes 0
• Cycle 4: J=0, K=1 → RESET → Q stays 0 (already 0)
• Cycle 5: J=1, K=1 → TOGGLE → Q becomes 1
■ In exams, always read J and K values JUST BEFORE the rising clock edge.

3.6 Logisim — Flip-Flop Implementation

D Flip-Flop in Logisim:
• 1. Go to Memory library → Drag 'D Flip-Flop' onto canvas
• 2. Add Input pin for D, another for CLK
• 3. Add Output pins for Q and Q'
• 4. Connect D input to D pin of FF, CLK to CLK pin
• 5. Run simulation: Toggle CLK while changing D — observe Q follows D

JK Flip-Flop in Logisim:
• 1. Memory library → 'J-K Flip-Flop'
• 2. Add inputs J, K, CLK; outputs Q, Q'
• 3. Test: Set J=1,K=1 and keep clocking — Q will toggle each clock cycle
• 4. Use Chronogram (Simulate menu) to view timing diagram automatically

DLD Study Guide — Sequential Logic & Important Topics | Page 10

 Chapter 4 — Practical Circuits: Burglar Alarm & Key System

4.1 Burglar Alarm Circuit

A Burglar Alarm Circuit uses an SR latch as its core. When a sensor is triggered (S=1), the
alarm activates and LATCHES ON — it stays ON even after the sensor returns to 0. Only a
manual RESET can turn it off.

Why SR Latch is Perfect for this:

• The MEMORY property of the latch keeps alarm ON once triggered
• Sensor triggers SET input (S) momentarily — alarm stays on
• Security personnel press RESET button to clear alarm

Truth Table / Operation

Event S (Sensor) R (Reset) Q (Alarm) State

Normal 0 0 Previous state Hold — no alarm

Intrusion! 1 0 1 ALARM ON (latched)

After sensor off 0 0 1 Still ON (memory!)

Guard resets 0 1 0 Alarm cleared

Circuit Design:
• Input S ← Motion/Magnetic sensor (active HIGH when triggered)
• Input R ← Reset push button (normally 0, press = 1)
• Output Q ← Connected to alarm buzzer/LED
• Use NOR latch or clocked SR FF for the memory element
• Add an AND gate with an ENABLE line for armed/disarmed control

Enhanced Design with ARM/DISARM:

• Add ENABLE signal: Alarm only works when ARMED (ENABLE=1)
• Effective S input = Sensor AND ENABLE
• Logic: Q(alarm) = SR_Latch(S=Sensor·Enable, R=Reset)

4.2 Key-Based System

A Key-Based System is a digital combination lock. The correct key sequence must be entered
to unlock. Uses sequential logic to check each bit in sequence.

Simple 4-bit Key System:

• Stores a 4-bit secret key code (e.g., 1011)
• User enters 4 bits via switches
• A comparator checks entered code against stored key
• If all 4 bits match → UNLOCK signal goes HIGH
• Wrong entry → system resets after 3 tries (with counter)

Design Components:

DLD Study Guide — Sequential Logic & Important Topics | Page 11

 • 4 D Flip-Flops (shift register) to store entered sequence
• 4 XNOR gates to compare each bit (XNOR outputs 1 when both inputs equal)
• 4-input AND gate: all XNOR outputs must be 1 for UNLOCK
• 2-bit counter: counts wrong attempts, locks after 3 failures

UNLOCK = bit3_match · bit2_match · bit1_match · bit0_match

bit_match = XNOR(entered_bit, key_bit)
■ XNOR gate truth: A XNOR B = 1 when A=B, 0 when A≠B. Perfect for bit comparison.

DLD Study Guide — Sequential Logic & Important Topics | Page 12

 Chapter 5 — Counters (Async, Sync, Up/Down, 7-Segment)

5.1 Introduction to Counters

A Counter is a sequential circuit that goes through a predefined sequence of states upon
application of clock pulses. Counters are used in frequency division, timers, address generation,
and event counting.
• n flip-flops → 2^n states (maximum)
• Mod-N counter: counts from 0 to N-1 then resets
• 3 FF → Mod-8 (counts 0–7), 4 FF → Mod-16 (counts 0–15)

5.2 Asynchronous (Ripple) Counter

In an Asynchronous Counter, the clock is applied only to the first flip-flop. Each subsequent
flip-flop is clocked by the output Q of the previous flip-flop. Also called a Ripple Counter
because the clock effect 'ripples' through.

3-bit Asynchronous Up Counter (Mod-8)

• Uses 3 JK flip-flops with J=K=1 (toggle mode)
• FF0 (LSB): clocked by main CLK
• FF1: clocked by Q0 (output of FF0)
• FF2 (MSB): clocked by Q1 (output of FF1)
• Trigger on FALLING edge of each FF output (for up count)

State Sequence — 3-bit Ripple Up Counter

Clock Pulse Q2 (MSB) Q1 Q0 (LSB) Decimal Count

Initial 0 0 0 0

1 0 0 1 1

2 0 1 0 2

3 0 1 1 3

4 1 0 0 4

5 1 0 1 5

6 1 1 0 6

7 1 1 1 7

8 0 0 0 0 (reset)

Advantages & Disadvantages

Advantages Disadvantages

Simple design Propagation delay accumulates

Less hardware Not suitable for high-speed

Easy to expand Glitches in intermediate states

Low power Clock skew issues

DLD Study Guide — Sequential Logic & Important Topics | Page 13

5.3 Synchronous Counter
In a Synchronous Counter, ALL flip-flops receive the same clock signal simultaneously. State
changes occur at the same time → no ripple delay → faster and more reliable.
• All flip-flops triggered by same CLK edge
• AND gates detect when lower-order bits are all 1 (carry logic)
• FF0 (LSB): J=K=1 always (toggles every clock)
• FF1: J=K=Q0 (toggles when Q0=1)
• FF2: J=K=Q0·Q1 (toggles when Q0=Q1=1)
• FF3: J=K=Q0·Q1·Q2 (toggles when Q0=Q1=Q2=1)

General rule: J(n)=K(n) = Q(n-1)·Q(n-2)·...·Q0

5.4 Up/Down Counter

An Up/Down Counter can count in either direction based on a control signal (M). When M=1:
counts UP (0→1→2→...→N-1→0). When M=0: counts DOWN (N-1→...→1→0→N-1).
• Uses a MODE (M) control input
• AND-OR logic selects between up-count and down-count carry chains
• Up carry: uses Q outputs. Down carry: uses Q' (complement) outputs

Logic for each FF (except FF0):

J = K = (M·Q(prev)) + (M'·Q'(prev))

3-bit Up/Down Counter State Table (M=1 Up, M=0 Down)

M (Mode) Current State Next State Direction

1 (UP) 000 001 ↑ Counting Up

1 (UP) 101 110 ↑ Counting Up

1 (UP) 111 000 ↑ Wraps to 0

0 (DOWN) 000 111 ↓ Counting Down

0 (DOWN) 011 010 ↓ Counting Down

0 (DOWN) 001 000 ↓ Back to 0

5.5 Mod-N Counter Design

A Mod-N counter counts from 0 to N-1. If 2^n > N, we use n flip-flops and add a reset logic to
skip states N through 2^n - 1.

Design Steps for Mod-6 Counter (counts 0–5):

• Step 1: Determine minimum flip-flops: 2^n ≥ 6 → n=3 (3 flip-flops)
• Step 2: Normal 3-bit counter counts 0–7. We need to skip 6 and 7.
• Step 3: Detect state 6 (Q2=1,Q1=1,Q0=0) using NAND/AND gate
• Step 4: Connect detection output to CLR (clear/reset) of all flip-flops
• Step 5: When state 6 is detected → instant reset to 000
• Step 6: Counter sequence: 000→001→010→011→100→101→(110 detected)→000

DLD Study Guide — Sequential Logic & Important Topics | Page 14

 Reset logic for Mod-6: CLR = Q2 · Q1 (NAND feedback)
■ Mod-10 (BCD Counter): Uses 4 FFs, resets at count 10 (1010). CLR = Q3·Q1 detects state 10.

5.6 Seven-Segment Display Interface with Counter

A Seven-Segment Display has 7 LED segments (a,b,c,d,e,f,g) that can display digits 0–9. We
interface it with a BCD counter through a BCD-to-7-Segment Decoder.

System Architecture:
• Clock → BCD Counter (Mod-10) → BCD-to-7-Seg Decoder → 7-Segment Display

BCD to 7-Segment Truth Table (Common Cathode)

Digit DCBA a b c d e f g

0 0000 1 1 1 1 1 1 0

1 0001 0 1 1 0 0 0 0

2 0010 1 1 0 1 1 0 1

3 0011 1 1 1 1 0 0 1

4 0100 0 1 1 0 0 1 1

5 0101 1 0 1 1 0 1 1

6 0110 1 0 1 1 1 1 1

7 0111 1 1 1 0 0 0 0

8 1000 1 1 1 1 1 1 1

9 1001 1 1 1 1 0 1 1

Segment Boolean Equations (simplified):

a = D + B + A'C + AC' (segment 'a' is ON for digits
0,2,3,5,6,7,8,9)

Logisim Steps — BCD Counter with 7-Segment:

• 1. Place a 4-bit Binary Counter from Memory library
• 2. Connect CLK input and EN (enable) = 1
• 3. Place '7-Segment Display' from Input/Output library
• 4. Place a BCD-to-7Seg decoder (build custom or use hex display)
• 5. Connect 4 counter outputs (Q3,Q2,Q1,Q0) to decoder inputs
• 6. Connect decoder outputs (a–g) to display segment inputs
• 7. Run simulation — display should cycle through 0,1,2,...,9,0,...
• 8. For Mod-10: add NAND gate to detect Q3·Q1 and connect to CLR

DLD Study Guide — Sequential Logic & Important Topics | Page 15

 Chapter 6 — Combinational Circuits

6.1 BCD Adder

A BCD Adder adds two BCD (Binary Coded Decimal) digits and produces a BCD result. BCD
uses 4 bits to represent digits 0–9 only. When the binary sum exceeds 9 (or a carry is
generated), we must add 6 (0110) to correct the result.

Why Add 6?
• 4-bit binary can represent 0–15, but BCD only uses 0–9
• States 10–15 (1010–1111) are invalid in BCD
• Adding 6 (0110) skips these invalid states and wraps correctly
• Example: 8+9=17 → binary: 10001 → invalid BCD! → 10001+0110=10111 → BCD result:
1,0111 → 17 ✓

Correction Logic:
Add 6 if: Carry_out = 1 OR (S3·S2=1) OR (S3·S1=1)
Where S3,S2,S1,S0 = 4-bit sum bits from first 4-bit adder

BCD Adder Circuit Design:

• Stage 1: 4-bit binary adder adds A[3:0] + B[3:0] → Sum S[3:0] + Carry C4
• Stage 2: Correction detection: Z = C4 + S3S2 + S3S1
• Stage 3: If Z=1, second 4-bit adder adds 0110 to S[3:0]
• Stage 4: Final output is corrected BCD sum + output carry

6.2 Comparator
A Comparator compares two binary numbers A and B and gives three outputs: A>B, A=B, A<B.

1-bit Comparator:
A B A gt B A=B A lt B

0 0 0 1 0

0 1 0 0 1

1 0 1 0 0

1 1 0 1 0

A>B = A.B' A=B = XNOR(A,B) = A'B'+AB A<B = A'.B

4-bit Comparator (e.g., IC 7485):

• Compares 4-bit numbers A[3:0] and B[3:0]
• Starts comparison from MSB (A3 vs B3)
• If A3≠B3 → result determined immediately
• If A3=B3 → compare A2 vs B2, and so on down to LSB
• Has cascade inputs (Iagtb, Iaeqb, Ialtb) for multi-chip expansion

DLD Study Guide — Sequential Logic & Important Topics | Page 16

6.3 BCD to Excess-3 Converter
The Excess-3 code is obtained by adding 3 (0011) to each BCD digit. It is a self-complementing
code useful in BCD arithmetic.

Decimal BCD (A B C D) Excess-3 (W X Y Z)

0 0000 0011

1 0001 0100

2 0010 0101

3 0011 0110

4 0100 0111

5 0101 1000

6 0110 1001

7 0111 1010

8 1000 1011

9 1001 1100

Simplified Boolean Equations (using K-map):

W = A + BC + BD
X = B'C + B'D + BC'D'
Y = C'D' + CD
Z = D'

6.4 Decoder
A Decoder is a combinational circuit that converts n input lines to a maximum of 2^n output lines.
Exactly ONE output line goes HIGH at a time.
• 2-to-4 Decoder: 2 inputs (A, B) → 4 outputs (Y0, Y1, Y2, Y3)
• 3-to-8 Decoder: 3 inputs → 8 outputs
• BCD-to-Decimal: 4 inputs → 10 outputs (IC 7442)

2-to-4 Decoder Truth Table:

A B Y0 Y1 Y2 Y3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Y0=A'B' Y1=A'B Y2=AB' Y3=AB

■ Decoders with Enable (E): Output is active only when E=1. Used as DEMUX when data is applied
to the enable input.

6.5 Encoder

DLD Study Guide — Sequential Logic & Important Topics | Page 17

An Encoder is the inverse of a decoder. It converts 2^n input lines to n output lines. Only ONE
input should be HIGH at a time (except priority encoder).
• 4-to-2 Encoder: 4 inputs → 2-bit binary output
• 8-to-3 Encoder: 8 inputs → 3-bit binary output
• Priority Encoder: If multiple inputs HIGH, highest-priority input wins

4-to-2 Encoder Truth Table:

I3 I2 I1 I0 Y1 Y0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Y1 = I2 + I3 Y0 = I1 + I3

6.6 Multiplexer (MUX)

A Multiplexer (data selector) selects one of 2^n data inputs and forwards it to a single output
based on n select lines.
• 2:1 MUX: 1 select, 2 inputs → 1 output
• 4:1 MUX: 2 selects (S1,S0), 4 inputs (I0–I3) → 1 output
• 8:1 MUX: 3 selects, 8 inputs → 1 output

4:1 MUX Operation:

S1 S0 Output Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

Y = S1'S0'·I0 + S1'S0·I1 + S1S0'·I2 + S1S0·I3

■ MUX as Universal Logic: Any Boolean function of n variables can be implemented using a 2^n : 1
MUX. Apply variable combinations to select lines.

6.7 Demultiplexer (DEMUX)

A Demultiplexer routes a single input to one of 2^n outputs based on n select lines. It is the
inverse of a MUX.
• 1:4 DEMUX: 2 selects, 1 input → 4 outputs
• 1:8 DEMUX: 3 selects, 1 input → 8 outputs

1:4 DEMUX Operation:

S1 S0 Y0 Y1 Y2 Y3

0 0 D 0 0 0

DLD Study Guide — Sequential Logic & Important Topics | Page 18

 0 1 0 D 0 0

1 0 0 0 D 0

1 1 0 0 0 D

■ A Decoder with Enable acts as a DEMUX when data is applied to Enable pin and select lines
route it to outputs.

DLD Study Guide — Sequential Logic & Important Topics | Page 19

 Chapter 7 — Exam Preparation: MCQs, Viva & Questions

7.1 Multiple Choice Questions (MCQs)

In an SR NOR latch, the forbidden state is:
(A) S=0, R=0
(B) S=1, R=0
(C) S=0, R=1
(D) S=1, R=1
✓ Answer: (D) S=1, R=1
Explanation: S=R=1 makes both Q and Q' = 0, which is contradictory and leads to unpredictable
behaviour.

The characteristic equation of a JK Flip-Flop is:

(A) Q(t+1)=J+K
(B) Q(t+1)=JQ'+K'Q
(C) Q(t+1)=J·Q'(t)+K'·Q(t)
(D) Q(t+1)=D
✓ Answer: (C) Q(t+1)=J·Q'(t)+K'·Q(t)
Explanation: JK FF: Q(t+1) = J·Q'(t) + K'·Q(t). This covers all four JK input combinations.

Which flip-flop has the simplest excitation table?

(A) SR Flip-Flop
(B) JK Flip-Flop
(C) D Flip-Flop
(D) T Flip-Flop
✓ Answer: (C) D Flip-Flop
Explanation: D FF: Q(t+1) = D always, so excitation table just shows D = Q(t+1).

A 3-bit ripple counter has a maximum count of:

(A) 6
(B) 7
(C) 8
(D) 16
✓ Answer: (B) 7
Explanation: 3-bit counter counts 0 to 7 (that's 8 states), maximum count reached is 7.

In a synchronous counter, all flip-flops are triggered by:

(A) Output of previous FF
(B) Common clock
(C) Individual clocks
(D) Enable signal
✓ Answer: (B) Common clock
Explanation: All FFs receive the same CLK simultaneously — this eliminates ripple delay.

To build a Mod-6 counter, minimum flip-flops required are:

(A) 2
(B) 3

DLD Study Guide — Sequential Logic & Important Topics | Page 20

 (C) 4
(D) 6
✓ Answer: (B) 3
Explanation: 2^2=4 < 6 < 8=2^3, so we need 3 flip-flops.

In a BCD adder, correction (+6) is applied when:

(A) Sum < 9
(B) Sum > 9 or carry = 1
(C) Sum = 9
(D) Inputs are equal
✓ Answer: (B) Sum > 9 or carry = 1
Explanation: BCD is only valid 0-9. Sum >9 or any carry means we exceeded BCD, so add 6.

Which gate is used for bit comparison in a digital comparator?

(A) AND
(B) OR
(C) XOR
(D) XNOR
✓ Answer: (D) XNOR
Explanation: XNOR gives output 1 when both inputs are equal, perfect for equality check.

A 4:1 Multiplexer has how many select lines?

(A) 1
(B) 2
(C) 3
(D) 4
✓ Answer: (B) 2
Explanation: 4 inputs need 2^n ≥ 4 → n=2 select lines.

The Excess-3 code for decimal 5 is:

(A) 0101
(B) 0111
(C) 1000
(D) 1001
✓ Answer: (C) 1000
Explanation: 5 + 3 = 8 → binary 1000.

In a JK flip-flop, J=1 K=1 causes:

(A) Set
(B) Reset
(C) No change
(D) Toggle
✓ Answer: (D) Toggle
Explanation: J=K=1 is the unique TOGGLE condition of the JK FF.

Which type of counter has propagation delay issues?

(A) Synchronous
(B) Asynchronous
(C) Up-Down
(D) Ring

DLD Study Guide — Sequential Logic & Important Topics | Page 21

 ✓ Answer: (B) Asynchronous
Explanation: Asynchronous (ripple) counter: each FF waits for previous → delay accumulates.

A DEMUX routes:
(A) Many inputs to one output
(B) One input to many outputs
(C) Two inputs to two outputs
(D) N inputs to N outputs
✓ Answer: (B) One input to many outputs
Explanation: DEMUX = 1-to-many routing based on select lines.

In BCD to 7-segment display for digit '0', segment 'g' is:

(A) ON (1)
(B) OFF (0)
(C) Don't care
(D) Depends on type
✓ Answer: (B) OFF (0)
Explanation: Digit 0 = segments a,b,c,d,e,f ON, g OFF (middle segment not lit for 0).

A Moore machine output depends on:

(A) Inputs only
(B) Current state and inputs
(C) Current state only
(D) Clock only
✓ Answer: (C) Current state only
Explanation: Moore machine: output = f(state) only, unlike Mealy where output = f(state, input).

DLD Study Guide — Sequential Logic & Important Topics | Page 22

 7.2 Viva Questions & Answers

Q: What is the difference between a latch and a flip-flop?

A: A latch is level-triggered (responds to input level); a flip-flop is edge-triggered (responds only at
clock edge). Latches are faster but less controlled.

Q: Why is J=K=1 not a problem in JK flip-flop but S=R=1 is a problem in SR?

A: In JK, J=K=1 causes a defined TOGGLE operation using feedback from Q outputs. In SR, S=R=1
forces both Q=Q'=0 simultaneously, violating Q ≠ Q'.

Q: What is the purpose of the Enable input in a decoder?

A: The Enable activates/deactivates the entire decoder. When Enable=0, all outputs = 0. This allows
using decoders as DEMUX or combining multiple decoders.

Q: Why is Excess-3 called a self-complementing code?

A: The 9's complement of any BCD digit can be found by simply inverting all bits of its Excess-3
code. This simplifies BCD subtraction circuits.

Q: What happens in a ripple counter if the clock frequency is very high?

A: Propagation delay accumulates through each FF. At high frequencies, later FFs haven't settled
before the next clock arrives, causing incorrect counts (glitches).

Q: How many flip-flops are needed for a Mod-12 counter?

A: 2^3=8 < 12 ≤ 16=2^4, so we need 4 flip-flops. Reset at count 12 (1100) using the logic Q3·Q2.

Q: What is the difference between MUX and DEMUX?

A: MUX: many-to-one (selects one of N inputs to route to output). DEMUX: one-to-many (routes
single input to one of N outputs).

Q: Explain the burglar alarm working in terms of SR latch.

A: Sensor triggers S=1 momentarily → Q latches to 1 (alarm ON). Even when S returns to 0, Q
stays 1 (memory effect). Only R=1 (reset button) clears the alarm.

Q: What is a characteristic equation of a flip-flop?

A: A Boolean equation expressing Q(next) as a function of Q(present) and inputs. SR:
Q(t+1)=S+R'Q; D: Q(t+1)=D; JK: Q(t+1)=JQ'+K'Q.

Q: How does a synchronous counter differ from an asynchronous counter?

A: Synchronous: all FFs share same clock → no propagation delay → faster, glitch-free.
Asynchronous: each FF clocked by previous FF output → delay accumulates → slower.

DLD Study Guide — Sequential Logic & Important Topics | Page 23

 7.3 Short & Long Questions

Short Questions (2–3 marks)

Q1. Define a sequential circuit. How does it differ from a combinational circuit?
Q2. Write the truth table of a NAND latch. What is its forbidden state?
Q3. What is the characteristic equation of a JK Flip-Flop?
Q4. Draw the excitation table for a D Flip-Flop.
Q5. What is a Mod-N counter? How many FFs are needed for Mod-10?
Q6. Differentiate between synchronous and asynchronous counters.
Q7. What is BCD addition? Give one example where correction is needed.
Q8. Draw the truth table for a 2:4 decoder.
Q9. What is the role of select lines in a multiplexer?
Q10. Define Excess-3 code. What is Excess-3 of decimal 7?
Q11. What is a priority encoder?
Q12. Explain the toggle condition in a JK flip-flop.

Long Questions (5–10 marks)

Q1. Design a 3-bit synchronous up-counter using JK flip-flops. Show truth table, K-map
simplification, logic equations, and circuit diagram.

Q2. Explain the SR, D, and JK flip-flops in detail. Compare their characteristic tables,
excitation tables, and applications.

Q3. Design a BCD adder and explain with a worked example: 7 + 6 = ?

Q4. Explain the BCD-to-7-segment decoder. Write Boolean equations for all 7 segments
and draw the complete interface with a BCD counter.

Q5. Design a Mod-6 synchronous counter. Show state diagram, state table, JK excitation,
K-map minimization, and Logisim implementation steps.

Q6. Explain the working of a burglar alarm circuit using SR latch. Draw circuit, truth table,
and timing diagram. Add ARM/DISARM feature.

Q7. Compare Mealy and Moore machines with state diagrams. Design a Mealy machine
that detects the sequence '101' in a serial bit stream.

Q8. Explain MUX and DEMUX with truth tables and Boolean equations. Show how a 4:1
MUX can implement any 3-variable Boolean function.

DLD Study Guide — Sequential Logic & Important Topics | Page 24

 7.4 Important Formulas, Rules & Key Points

■ Important Formulas
FF count for Mod-N counter:
n = ■log■(N)■ (ceiling of log base 2 of N)

SR Char. Equation:
Q(t+1) = S + R'·Q(t) [SR = 0 required]

D Char. Equation:
Q(t+1) = D

JK Char. Equation:
Q(t+1) = J·Q'(t) + K'·Q(t)

T Char. Equation:
Q(t+1) = T⊕Q(t) [T FF: toggles when T=1]

BCD correction:
Add 6 if Sum > 9 OR Carry = 1

Excess-3 code:
Excess-3 = BCD + 0011 (add 3)

MUX output (4:1):

Y = Σ m■·I■ (sum of minterm × input)

Comparator A=B:
XNOR of each bit-pair, then AND all results

Counter max count:

2■ − 1 (n = number of flip-flops)

Clock frequency:
f = 1/T (T = clock period)

Ripple counter freq:

Output frequency = Input CLK / 2■

■ Key Rules to Remember

• ✦ NOR Latch: Forbidden = S=R=1 | NAND Latch: Forbidden = S'=R'=0 (OPPOSITE!)
• ✦ JK is called 'Universal FF' — can mimic SR (K=J'), D (K=J'), T (J=K)
• ✦ D FF excitation: D = Q(next) — always! No logic needed.
• ✦ JK excitation: use X (don't-cares) when Q doesn't change from/to 1 to 1 or 0 to 0
• ✦ Synchronous counter: NO propagation delay. Asynchronous: delay × number of FFs
• ✦ Mod-N counter: needs ■log■N■ FFs. Reset at count N using AND/NAND logic.
• ✦ BCD valid range: 0000 to 1001 (0 to 9). States 1010–1111 are INVALID.
• ✦ XNOR = Equality checker: output 1 when both inputs are same

DLD Study Guide — Sequential Logic & Important Topics | Page 25

 • ✦ Decoder output: exactly ONE output HIGH at a time
• ✦ Encoder input: exactly ONE input HIGH at a time (except priority encoder)
• ✦ MUX: select lines choose which input to pass to output
• ✦ 7-segment: segment 'g' (middle) is OFF for digits 0,1,7
• ✦ State diagram circles = states, arrows = transitions, labels = inputs/outputs
• ✦ Mealy: fewer states than Moore for same function

■ Most Frequently Asked Exam Topics

• ★ JK Flip-Flop: characteristic table, excitation table, timing diagram
• ★ SR Latch: forbidden state, difference from SR FF
• ★ D Flip-Flop: excitation table (simplest to remember!)
• ★ Counter design: Mod-N using JK FFs with K-map
• ★ BCD Adder: correction logic, worked example
• ★ 7-Segment display: segment truth table, Boolean equations
• ★ MUX: truth table, Boolean equation, using MUX for logic functions
• ★ Decoder vs Encoder: differences, truth tables

DLD Study Guide — Sequential Logic & Important Topics | Page 26