AD0 - AD15

Vcc
16 - bit Address/Data Bus
CLK

RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)

(QS0)/ ALE M/IO (S2)

(RQ/GT0) HOLD DT/R (S1)

(RQ/GT1) HLDA DEN (S0)

Gnd Gnd

FIG: Logic Diagram 8086 of Microprocessor

SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%

Freq. i/p T-State Version

Clock Frequency: 5 MHz 200 nsec 8086

8 MHz 125 nsec 8086-2
10 MHz 100 nsec 8086-1

In 8088 CPU:
 Length of internal FIFO queue is 4-bytes.
 AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
 Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
 M/IO becomes IO/M.
 Other pin functions and definitions remain same.
 PIN FUNCTION
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground. Two ground pins
Clock input signal with 33% duty cycle. It Determines the speed of
CLK
processor.
It causes the processor to reset itself if the RESET is high atleast for 4
clock periods.
RESET
At reset processor sets CS = FFFFh and clear the PSW, IP, DS, ES, SS
and instruction queue (IPQ).
Address/Data multiplexed bus. The address comes first and can be
AD0-AD15
latched externally. Then bus can be made free to carry the data.
Address/Status bus multiplexed bus. The upper 4-bit address comes
first and then come the status signals.
 Status S6 always LOW i.e. S6=0 always.
A16-A19 /
 Status S5 gives current status of IF flag i.e. S5=IF always.
S6 –S3
 Status S4 & S3 gives the information about current segment (register)
being used as shown below. The S4 & S3 bits may also be used as A21
& A20 to address four separate 1MB-memory banks.

Status Signals
Meaning
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No Segment
1 1 Data Segment

Bus High Enable. A LOW on this pin enables the most significant
BHE/S7 data bus (D8-D15) during a read or write operation. After BHE
information, comes the status S7 which always remains LOW.
Read signal. A LOW on this signal instructs the selected I/O or
RD
memory device to give its data content onto the data bus.
Slow peripheral or memory devices use it. A LOW on this input tells
the processor that the device is not yet ready for data transfer and
READY
thus causing processor to enter into wait states. A HIGH on this
input continues normal operation of 8086.
Interrupt Request. A level triggered interrupt. External hardware
INTR can used this pin to interrupt normal operation of processor. This
signal is recognized if and only if flag IF=1 in flag register.
Non Maskable Interrupt. A positive edge triggered interrupt.
NMI Always served by the 8086 irrespective of status of IF flag. Thus
always used for critical conditions.
Test input is sampled by WAIT instruction of 8086. If TEST=1 the
WAIT instruction waits for this signal to become 0. As soon as it
TEST
becomes 0 processor works further. If it is already 0 WAIT
instruction works as NOP.
Minimum/Maximum Mode. A LOW on this signal configures the
MN/MX 8086 in maximum mode and a HIGH configures it to minimum mode
of operation.
 20 10

Vcc GND

3 1D 1Q|2
D
5
2D CLK 2Q 6
3D 3Q 9
4D 40
13 12
5D 74LS373 5Q 15
14
6D 6Q 16
17
7D 7Q 19
18
8D 80
G

11 1
Enable Output
Control
Function Table
Output Enable
Control G D Output
L H H H
L H
L
H
L
X
X
X
Qo
 BHE
BHES7 OE A19
Ajw/so Aj8
AN/SS '373 Aj7
As4 A6
8086 As
Aj4
A3
A12
Ai
Aj0 Address bus
Ag
Ag
A6
As
A4
As
A2
Ai
Ao
ALE G G
"373 OE '373 OE

AD1s Dis
AD14 D4
AD13
AD12
AD Di2
ADjo
Di
AD, Dio
ADg
Dg
AD, D& Data bus
AD6 D
ADs
AD, " D,
AD, D4
Da
AD,
AD, D,
ADo D,
M/IO Do
RD M/O
MN/MX WR RD Control bus
WR
+SV
 AD0 - AD15
Vcc
16 - bit Address/Data Bus
CLK

RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)

(QS0)/ ALE M/IO (S2)

(RQ/GT0) HOLD DT/R (S1)

(RQ/GT1) HLDA DEN (S0)

Gnd Gnd

FIG: Logic Diagram 8086 of Microprocessor

SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%

Freq. i/p T-State Version

Clock Frequency: 5 MHz 200 nsec 8086

8 MHz 125 nsec 8086-2
10 MHz 100 nsec 8086-1

In 8088 CPU:
 Length of internal FIFO queue is 4-bytes.
 AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
 Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
 M/IO becomes IO/M.
 Other pin functions and definitions remain same.
 VCC 1G

20 1
1 A1 1Y1
2 18

1 A2 1Y2
4 16

1 A3 1Y3
6 14
Function Table
1 A4 1Y4 1A1 1Y1
8 12
1G 2G Operation
1A2 1Y2
2 A1 2Y1 All O/Ps Enabled, i.e. I/Ps 1A i
11 9 1A3 1Y3 0 0 appears at O/Ps 1Yi & I/Ps 2A i
2 A2 2Y2 appears at O/Ps 2Yi.
13 7 1A4 74LS244 1Y4
O/Ps 1Yi Enabled, i.e. I/Ps 1A i
2A1
OCTAL 2Y1
0 1 appears at O/Ps 1Yi & O/Ps 2Yi
2 A3 2Y3
15 5 BUFFER in HIGH-Z State.
2A2 2Y2 O/Ps 2Yi Enabled, i.e. I/Ps 2A i
2 A4 2Y4 1 0
17 3 2A3 2Y3 appears at O/Ps 2Yi & O/Ps 1Yi
in HIGH-Z State.
2A4 2Y4
10 19 All O/Ps in HIGH-Z State.
1 1 OR
Gnd 2G 1G 2G I/P Isolated from O/P.

(a) Internal Logic Diagram (b) Functional Diagram (c) Function Table

74LS244 - OCTAL BUFFER/ LINE DRIVER/ LINE RECEIVER

VCC GND
A1 B1
20 10
A1 B1 A2 B2
2 18

A3 B3
A2 B2
3 17 A4 B4
74LS245
A5 Transceiver B5
A3 B3
4 16
A6 B6
A4 B4
5 15 A7 B7
A5 B5
6 14 A8 B8
A6 B6
7 13 DIR G
A7 B7
8 12
(b) Functional Diagram
A8 B8
9 11

Function Table
Direction
Enable Operation
Control
G DIR
0 0 Data flow
from B to A.
1 19 0 1 Data flow
from A to B.
DIR G
Direction Enable
1 X Isolation
Control
(a) Logic Diagram
(c) Function Table

74LS245 TRANCEIVERS

1
 M/IO Buffered
M/IO RD control
RD WR bus
'244
WR

BHE
BHE/S7 Aj9
A*
A|NSS '373
A1
As
8086 Aes G OE As
A4
A?
A Buffered
Ao address
Ay bus
Ax
A1
A6
As
As
A
A
A
Ao
ALE
'373 OE '373 OE

AD1s Dis
ADi4
ADi
Di+
Di
ADi2 '245 Di2
AD| D
ADi0
AD,
Do
Dy
ADg G DIR Dx

AD,
AD,
AD, D6
AD, Ds
AD, '245 DA
AD, Di
AD, D.
- D,
ADo
DIR Do
DEN
DT/R
 A0 A1 A2 A3 B0 B1 B2 B3

SEL (B)

Y0 Y1 Y2 Y3

Fig: 74LS157 NIBBLE MULTIPLEXER

Function Table
1 SELECT Vcc 16
Select
Operation
SEL (B) 2 A3 STROBE 15

Nibble B is routed to output Y. 3 B3 A 0 14

0
i.e. Y0, Y1, Y2, Y3 = A0, A1, A2, A3
4 Y3 74LS157 B0 13
Nibble A is routed to output Y.
1 A2 Y0 12
i.e. Y0, Y1, Y2, Y3 = B0, B1, B2, B3 5

SEL(B) – SELECT NIBBLE CONTROL 6 B2 A 1 11

– SELECT NIBBLE B?
7 Y2 B1 10
– 1 for YES i.e. Nibble B is selected.
– 0 for NO i.e. Nibble A is selected. Gn d Y1 9
8
This control signal is used to select one of
the two input Nibbles.

(c) Function Table

 AD0 - AD15
Vcc
16 - bit Address/Data Bus
CLK

RESET
A16 - A19 / S3 - S6
READY
4 - bit Address/Status Bus
TEST
BHE / S7
NMI
MN / MX
(MAX INTR 8086 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)

(QS0)/ ALE M/IO (S2)

(RQ/GT0) HOLD DT/R (S1)

(RQ/GT1) HLDA DEN (S0)

Gnd Gnd

FIG: Logic Diagram 8086 of Microprocessor

SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%

Freq. i/p T-State Version

Clock Frequency: 5 MHz 200 nsec 8086

8 MHz 125 nsec 8086-2
10 MHz 100 nsec 8086-1

In 8088 CPU:
 Length of internal FIFO queue is 4-bytes.
 AD8 to AD15 changes to A8 to A15 as only 8-bit data bus is there.
 Signal BHE/S7 changes to SSO, which is logically equivalent to signal S0.
The signal is always HIGH when 8088 is operating in maximum mode.
 M/IO becomes IO/M.
 Other pin functions and definitions remain same.
 AD0 – AD7
Vcc 8 - bit Address/Data Bus
CLK A8 - A15
RESET 8 - bit Address Bus

READY A16 - A19 / S3 - S6

4 - bit Address/Status Bus
TEST
SSO (HIGH)
NMI
MN / MX
(MAX INTR 8088 (MAX
MODE) RD MODE)
(QS1)/INTA WR/(LOCK)

(QS0)/ ALE IO/M (S2)

(RQ/GT0) HOLD DT/R (S1)

(RQ/GT1) HLDA DEN (S0)

Gnd Gnd

FIG: Logic Diagram of 8088 Microprocessor

SUPPLY:
Supply Voltage: Single +5V DC +/- 10%
Ground: System Ground (Two pins)
CLOCK:
Duty Cycle: 33%

Freq. i/p T-State Version

Clock Frequency: 5 MHz 200 nsec 8088

8 MHz 125 nsec 8088-2
10 MHz 100 nsec 8088-1
 OE IO/M Buffered
IOM
RD RD control
'244
WR bus
WR

OE A19
Aj9/s6
A18/s5 A18
Aj1S4 '373 Aj7
Aj6/53 A6

8088

A1s As
A4 A4
A3
A13 Buffered
A2 '244
A12
A| address
Al Ajo bus
A1o
Ag
Ag
As OE

A6

A4
A2
A
Ao

G '373 OE
ALE

A1 B1 D,
AD, A6 B6 D6
AD6 Ds
AD, As Bs Buffered
A4 B4 D,
ADA "245 data
Ag B D, bus
AD, D2
AD,
Az B2
A BË D,
AD, Ao Do
ADo Bo
G DIR
DTX DEN
 PIN FUNCTION
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground. Two ground pins
Clock input signal with 33% duty cycle. It Determines the speed of
CLK
processor.
It causes the processor to reset itself if the RESET is high atleast for 4
clock periods.
RESET
At reset processor sets CS = FFFFh and clear the PSW, IP, DS, ES, SS
and instruction queue (IPQ).
Address/Data multiplexed bus. The address comes first and can be
AD0-AD15
latched externally. Then bus can be made free to carry the data.
Address/Status bus multiplexed bus. The upper 4-bit address comes
first and then come the status signals.
 Status S6 always LOW i.e. S6=0 always.
A16-A19 /
 Status S5 gives current status of IF flag i.e. S 5=IF always.
S6 –S3
 Status S4 & S3 gives the information about current segment (register)
being used as shown below. The S 4 & S3 bits may also be used as A21
& A20 to address four separate 1MB-memory banks.

Status Signals
Meaning
S4 S3
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No Segment
1 1 Data Segment

Bus High Enable. A LOW on this pin enables the most significant
BHE/S7 data bus (D8-D15) during a read or write operation. After BHE
information, comes the status S7 which always remains LOW.
Read signal. A LOW on this signal instructs the selected I/O or
RD
memory device to give its data content onto the data bus.
Slow peripheral or memory devices use it. A LOW on this input tells
the processor that the device is not yet ready for data transfer and
READY
thus causing processor to enter into wait states. A HIGH on this
input continues normal operation of 8086.
Interrupt Request. A level triggered interrupt. External hardware
INTR can used this pin to interrupt normal operation of processor. This
signal is recognized if and only if flag IF=1 in flag register.
Non Maskable Interrupt. A positive edge triggered interrupt.
NMI Always served by the 8086 irrespective of status of IF flag. Thus
always used for critical conditions.
Test input is sampled by WAIT instruction of 8086. If TEST=1 the
WAIT instruction waits for this signal to become 0. As soon as it
TEST
becomes 0 processor works further. If it is already 0 WAIT
instruction works as NOP.
Minimum/Maximum Mode. A LOW on this signal configures the
MN/MX 8086 in maximum mode and a HIGH configures it to minimum mode
of operation.
There are total 8-pins which have dual meaning and have different definitions in
minimum and maximum mode of operation. The maximum mode pin names are
indicated within the brackets in the logic diagram.

Minimum Mode Pin Definitions

Memory/IO Selects. When M/IO = 1 it selects the memory operation
M/IO
and if M/IO = 0 it selects the I/O operation.
Address Latch Enable. The signal is used to enable external latches.
ALE These latches are used to hold address information present on AD 0 - AD15
and A16 - A19 bus.
Write signal. A LOW on this signal instructs the selected I/O or memory
WR
device to accept the data content of the data bus.
Data Transmit/Receive. When HIGH it tells that Microprocessor is
transmitting and at LOW it tells that Microprocessor is receiving the data.
DT/R
The signal is used to inform the direction of data transfer to external
transceivers like 8286.
DEN Data Buffer Enable. This signal is used to enable data bus buffers.
Note: Both DT/R and DEN are used in fully buffered mode
Interrupt Acknowledgement. This signal is generated in response to
INTA
INTR request after which requesting device supplies the interrupt vector.
This input is used to request a direct memory access (DMA). When
HOLD=1 processor completes its current machine cycle and enter into
HOLD
hold state. In this state processor places its data, address and control
bus in high impedance state.
Hold Acknowledge. A HIGH on this pin tells the DMA requesting device
HLDA that the processor has entered into HOLD state and the requesting device
can use the system busses.

Maximum Mode Pin Definitions

As earlier mentioned 8-pins are defined to have different meaning in maximum
mode of operation. These pins and their data directions are shown in a simplified
maximum mode logic diagram in following paragraphs.
This pin is used when multiple processors are connected to single bus.
When this signal is activated it prevents other processors from driving
LOCK
the system busses. This is called locking of busses. The signal goes LOW
whenever an instruction with LOCK prefix is executed.
Bus Request/Bus Grant. These pins are used for DMA request and
RQ0/GT0 grant in maximum mode of operation. They are same as HOLD & HLDA of
& minimum mode except that they are now available on a single pin and
RQ1/GT1 are active LOW. These pins are also used to connect numeric coprocessor
(8087) in maximum mode. RQ0/GT0 pin has higher priority than RQ 1/GT1.
Queue Status. These two pins inform about the current status of
QS1, QS0 internal queue of 8086, as shown below. The Numeric coprocessor
(8087) uses these pins to get the current queue status of 8086.
 S0
LOCK Queue Status Signals
S1 Meaning
QS1 QS0
RQ/GT0 8086 No operation, Queue is
Maximum 0 0
S2 IDLE.
Mode
RQ/GT1 0 1 First byte of OPCODE.
Pins
QS0 1 0 Internal Queue is EMPTY.
Subsequent byte of an
1 1
MN/MX QS1 OPCODE.

Status Bits. These bits indicate the function of current bus cycle. These
S2,S1,S0 pins are decoded externally by the 8288 bus controller. The below table
summarizes the function encoded on these bits.

STATUS BITS
MEANING
S2 S1 S0
0 0 0 Interrupt Acknowledgement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 HALT
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive or Inactive

Note: Status signal S2 tells weather it is a Memory Operation or an IO Operation and is

equivalent to signal M/IO. When it is LOW it indicates an IO operation and at HIGH it
indicates a memory operation.
 X1
Clock CLK
X2
Section PCLK Output
EFI Section
OSC
F/C READY
CSYNC 8284 RESET
ASYNC Reset
Ready AEN1 Section
RES
Section
RDY1
Vcc Power
AEN2
Supply
RDY2 Gnd

Logic Diagram 8284 CLOCK GENERATOR

PIN FUNCTION
POWER SUPPLY
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground.
CLOCK SECTION
X1, X2 Crystal Oscillator Input. Appropriate crystal is to be connected here.
External Frequency Input. Clock signal from some other sources to be
EFI
connected here.
External Frequency/Crystal Select. When F/C =0 Crystal oscillator
F/C
(X1, X2) is selected while at F/C=1 EFI input is selected for clock input.
Clock Synchronization for EFI input. The pin must be grounded when X1
CSYNC
& X2 are used.
RESET SECTION
RES Active Low RESET input.
READY SECTION
Address Enable. They are used to selectively enable or disable the bus
AEN1, AEN2
READY signals RDY1 & RDY2.
RDY1, RDY2 Bus READY signals. Two devices can be connected for ready request.

Ready Synchronization. It selects 1-stage ready synchronization when

ASYNC
ASYNC=1 while it selects 2-stage ready synchronization if ASYNC=0.
OUTPUT SECTION
CLOCK output to be connected to CLK input of 8086/8088 processor. It
CLK
is 1/3 of crystal or EFI input frequency and has 33% duty cycle.
Peripheral Clock. It is a 50% duty cycle clock whose frequency is 1/6
PCLK of crystal or EFI frequency, or half of the frequency at CLK output. It is
used for peripheral devices in the system.
OSC Oscillator output is a TTL signal with frequency same as crystal or EFI.
RESET Reset output to be connected to RESET input of 8086/8088 processor.

READY Ready output to be connected to READY input of 8086/8088 processor.

 X1
CLK CLK
15 MHz
CRYSTAL
X2
8 8
F/C 2 0
8 8
+5V
CSYNC 4 6

10K
RESET RESET

10
RES
uF

SYSTEM
RESET

 External crystal is connected between X1 & X2 as source for crystal

oscillator. Depending upon the version it can be 15MHz, 24MHz, or 30
MHz for the speeds of 5 MHz, 8 MHz, or 10 MHz respectively.
 Since X1 & X2 are used F/C and CSYNC are grounded.
 RC network with time constant 100 msec is used to provide active low
reset.
 Diode is used to protect from negative spikes.
 When power is first on voltage across capacitor is 0V so logic 0 is
applied at RES input.
 In short time RES input become Logic1 as capacitor charges to +5V.
 A push button allows operator to reset the system as it allows the
capacitor to discharge.
 8284 applies the RESET to 8086 processor at negative edge of each
clock.
 The 8284 ensure that RESET signal must stay high for at least 50µsec.
 The processor samples the reset at the positive edge of clock.
 S0 MWTC
8086 Status MRDC
S1
Input Command
IORC Signals
S2
IOWC

CLK AMWC
Control C
Inputs
AEN 8288 AIOWC
CEN INTA
IOB DEN Addr Latch,
ALE Transceiver
Power Vcc
DT/R Controls
Supply
Gnd
MCE/PDEN
Logic Diagram 8288 BUS CONTROLLER
PIN FUNCTION
POWER SUPPLY
Vcc +5V +/- 10%
Gnd Ground pin connected to system ground.
STATU INPUTS
S0, S1, S2 Status Inputs. Connected to corresponding status pins of 8086.
CONTROL INPUTS
CLK Clock Input. It must be connected to CLK output pin of 8284.
Address Enable. A low on this input causes the 8288 to enable memory
AEN
control signals.
Control Enable. A high on this input enables the command output
CEN
signals of 8288.
I/O Bus Mode. A high on this input selects I/O bus mode while a low
IOB
selects system bus mode.
COMMAND SIGNALS
MRDC Memory Read Control Signal.
MWTC Memory Write Control Signal.
IORC I/O Read Control Signal.
IOWC I/O Write Control Signal.
Advance Memory Write Control Signal. Same as MWTC signal but the
AMWC
signal is activated one clock pulse earlier than the normal write.
Advance I/O Write Control Signal. Same as IOWC signal but the signal is
AIOWC
activated one clock pulse earlier than the normal write.
INTA Interrupt Acknowledge. Same as INTA of 8086
DT/R Same as DT/R of 8086.
ALE Same as ALE of 8086.
DEN Same as DEN of 8086. Note that it is active high signal in 8288.
Master Cascade/Peripheral Data. It selects master cascade operation
MCE/PDEN (MCE) for 8259 interrupt controller if IOB=0 and if IOB=1 it enables the
IO bus transceivers (PDEN) which is used in multibus configuration.