ECE 902

Modeling and Optimization

of VLSI Interconnects
([Link]
Instructor: Lei He
Email: he@[Link]
Office: EH3423
Telephone: 262-3736
Office hour: TR 1:30-3pm

Course Prerequisites

n No official prerequisites
u Mainly self-contained

n Knowledge to help you appreciate more

u ECE320 Electrodynamics
u ECE555/755 Digital Circuits and Components
u CS577 Introduction to Algorithms
 References

n Cong et al., Performance Optimization of VLSI

Interconnect Layout, Integration, the VLSI Journal
21 (1996) 1--94.
n Selected papers from TCAD, TODAES, and major
CAD conferences such as DAC, ICCAD and ISPD
n H. Bakoglu, Circuits, Interconnects, and Packaging
for VLSI, Addison Wesley
n J. Rabaey, Digital Integrated Circuits: A Design
Perspective, Prentice Hall

Related VLSI CAD Conferences and Journals

n ACM IEEE Design Automation Conference (DAC)

n International Conference on Computer Aided Design(ICCAD)

n IEEE International Symposium on Circuits and Systems (ISCAS)
n Design, Automation and Test in Europe (DATE)
n Asia and South Pacific Design Automation Conference (ASP-
DAC)
n International symposium on physical design (ISPD)
n IEEE Transactions on CAD of Circuits and systems (TCAD)
n ACM Trans. on Design Automation of Electronic Systems
(TODAES)
n IEEE Transactions on Circuits and Systems (TCAS)
n IEEE Trans. on VLSI Systems (TVLSI)
Grading Policy

n Homework 20%
n Quiz 10%
n Paper presentation 25%
n Use transparencies or video projector
n Graded by fellow students
n Term project 45%
n Bonus points
u For active participation

n Grade A for score > 85

Term Project
n One of the following:
u Survey of selected papers (1 person, at most 40 points)
u Programming project (2 persons in a term)
F Web-based bus modeling and optimization

F A CAD tool to perform repeater planning during floor

planning
F Or a topic agreed by instructor

u Writing requirements
F In a conference paper style
Course Outline
n Overview and Introduction (1 lecture)

n Interconnect Extraction and Modeling (3 lectures)

n Interconnect Delay Modeling (3 lectures)
n Device Optimization (3 lectures)
n Interconnect Topology Optimization (2 lectures)
n Interconnect Sizing (2 lectures)
n Simultaneous Device and Interconnect
Optimization (1 lecture)
n Interconnect Estimation and Planning

Course Outline

n Noise Modeling, Avoidance and Control (4

lectures)
n Interconnect Power Model and Reduction (3
lectures)
n System-level Interconnect Prediction ** (1 lecture)
n On-chip bus design** (1 lecture)
Course Schedule
n Lectures only on Wednesdays for the first two weeks
u i.e., lecture given by TA on Sept. 12 th

n Meet Sept. 19th and 21st

n Meet three times a week starting Sept. 24th

n Projects assigned no later than Nov. 7th

u Start to meet twice a week then

n Term report due on the last day of this semester

u With a grace period of two days

Skills to Learn
n Interconnect modeling and design

n Programming / writing / presentation

Overview
n Moore’s Law
n CMOS scaling theory
n Interconnect performance implied by NTRS’97
n Need for a new design paradigm

Basic Components In VLSI Circuits

n Devices Pad Meta

l
Via Metal 2

u Transistors
u Logic gates and cells Data Path
PLA I/O
u Function blocks

n Interconnects ROM/RAM

u Local signals
u Global signals A/D Converter
Random logic

u Clock signals
u Power/ground
networks
 Determining Factors of System Performance

Combinational
Logic

Storage
element
Clock Period ≥ td-gates + td-interconnects + tskew + tsu + tds

}
td-gates = gate delay in comb. logic
td-interconnects = interconnect delay in comb. logic Interconnect
tskew = clock skew delay
tsu = set-up time
tds = delay within storage elements

Importance of VLSI Interconnect Design

nTechnology Trends:
uDeep sub-micron design: < 0.18 micron CMOS technology
uHigh-Speed : > 500 MHz ~ 5 GHz
nImpact on VLSI System Design
uInterconnect delay becomes the dominating factor in
system performance
oConsumes 50%-70% clock cycle
uDistributed nature of interconnects becomes significant
oBecomes distributed RCL circuits or lossy transmission lines.

Interconnect-Driven Design
Moore’s Law and NTRS

n Moore’s Law
u The min. transistor feature size decreases by 0.7X every three
years (Electronics Magazine, Vol. 38, April 1965)
u True in the past 30 years!
n National Technology Roadmap for Semiconductors
(NTRS’97)
Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07
Year 1997 1999 2001 2003 2006 2009
# transistors 11M 21M 40M 76M 200M 520M
On-Chip Clock (MHz) 750 1200 1400 1600 2000 2500
Area (mm2) 300 340 385 430 520 620
Wiring Levels 6 6-7 7 7 7-8 8-9

Ideal Scaling of MOS Transistors

W

S G
D

tgox Leff
Xj B
Figure 1.1 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
The main dimensions that determine device properties are gate oxide thickness
tgox; gate length L, gate width W; and junction depth Xj

Assumptions:
aAll horizontal & vertical dimensions of a transistor( W, L,
tgox, Xj) are reduced by S
aAll voltages ( Voo, VTN, V TP ) are reduced by S
aSubstrate doping (Nsub ) is increased by S
a(VTN, VTP: threshold voltages of N and P transistors)
 TABLE 1.1 Scaling of MOS Transistors
Parameter
Parameter ScalingFactor
Scaling Factor
Dimensions(W,
Dimensions (W, L, L,ttgox, ,XX)j) 1/S
1/S
gox j
Substratedoping
Substrate doping(N (NSUB)) SS
SUB
Voltages(V
Voltages (VD D, ,VVTN, ,VVTP)) 1/S
1/S
DD TN TP
W åox
Current per
Current device(I(IDSDS∝∝ W åox (V
perdevice (VDDDD − VT)
2
− VT) 2 ))
LL ttgox
gox 1/S
1/S
WL
Gatecapacitanc
Gate (Cgg==åå
capacitancee(C oxWL (VDD − VT)
ox (VDD − VT) 2 ))
2

ttgox
gox 1/S
1/S
V DD
Transistor on
Transistor on--resistance
resistance(R (Rtrtr∝ ∝V DD ))
IIDSDS
11
Cg∆ g∆V
Intrinsic date
Intrinsic datedelay
delay(ô (ô== C V
==R RtrtrC
Cg)g)
IIavav 1/S
1/S
2
Power-dissipationper
Power-dissipation pergate
gate(P=IV)
(P=IV) 1/S
1/S2
Power--delay
Power delayproduct
product per
pergate (P××ô)
gate(P ô) 1/S3 3
1/S
Areaper
Area perdevice
device(A=WL)
(A=WL) 1/S2 2
1/S
Power-dissipationdensity
Power-dissipation density(P/A)
(P/A) 11

Current Through an n-channel MOS Transistor

Linear VDS= VGS-Vτ
IDS

VGS

VDS
FIGURE 2.2 I-V characteristics of an nMOS transistor

o Vgs ≤ Vtn (Cut-off)

[ ]
Ios= â n (Vgs − Vtn )Vos − Vos2 /2 Vds ≤ Vgs − Vtn (Linear in terms of VGS)
â = (Vgs − Vtn )

Vds ≥ Vgs − Vtn (Saturation,
 n 2 independent of VDS)
w
â n = ì n .c gox . Gain Factor
L
å ox geometric dimentsions of the
electron mobility
ô gox transistor
 Ideal Scaling of VLSI Interconnects

wsp wint
Hint
lint tox

Figure 1.2 Basic interconnection parameters

Assumptions:
a Cross Sectional dimensions ( Wint, Hint, Wsp,
Tox) are reduced by S
a Die Size and global interconnection Lengths are
increased by Sc

Table 1.2 Scaling of Local and Global Interconnections

Parameter
Parameter ScalingFactor
Scaling Factor
Crosssectional
Cross sectionalDimensions
Dimensions(W
(W int, ,HH int, ,W
W sp, ,t t ox) ) 1/S
1/S
int int sp ox
1
Resistanceper
Resistance perunit
unit length (Rintint==ññintint 1
length(R ))
W intH int 2
W intH int SS2
Wint
Capacitanceeper
Capacitanc perunit
unitlength
length(C (Cintint==εεo ox xWint ))
t to ox x 11
RCconstant
constantper
perunit
unitlength
length(R
(R intCC int) ) 2
RC int int SS2
Local interconnection RC delay (l(l loc) )
Local interconnection RC delay
loc
1/S
1/S
2
Localinterconne
Local interconnection
ctionRRCCdelay
delay(R
(R CC l l )) int int 2
int int l ol oc c
11
Diesize
Die size(D
(D C) ) SSCC
C
Global interconnection length(l(l int) )
Global interconnection length SS C
int C
2
Globalinterconne
interconnection
ctionRC
RCdelay
delay(R
(RintintCCintintl l2int ) 2
(S C) 2) 2
Global int ) SS2 (S C
Transistorline
Transistor linetime
timeofofflight
flight(l(l int/v/v c) ) SS C
int c C
Local Interconnects under Different Scaling Rules
Table 5.1 Scaling of Local Interconnections
Ideal
Ideal Qussi-Ideal Constant-R
Qussi-Ideal Constant-R Generalized
Generalized
Parameter
Parameter Scaling
Scaling Scaling
Scaling Scaling
Scaling Scaling
Scaling
Thickness(H
(Hint) ) 1/S 1/ SS 1/ 1/S H
Thickness int 1/S 1/ 1/ SS 1/S H

Width (W int) )
Width (W
int
1/S
1/S 1/S
1/S 1/
1/ SS
1/S
1/S WW
Separation(W(Wsp) ) 1/S 1/S 1/
1/ SS 1/S sp
Separation sp 1/S 1/S 1/S sp

Insulator thickness (t(t ox

Insulator thickness )) 1/S
1/S
1/ SS
1/ 1/
1/ SS 1/S ox
1/S
ox ox
Length(l(l loc) )
Length loc
1/S
1/S 1/S
1/S ≈≈1/S
1/S 1/S
1/S
Resistance
Resistance (R(Rint) ) SS SS 11 S SSH/S/S
S W
int W H

Capacitancetotosubstrate
Capacitance substrate 1/S
1/S 1/S3/23/2
1/S ≈≈1/S
1/S SSoxox/SS
/SSW
W
Capacitance between lines
Capacitance between lines 1/S
1/S
1/ SS
1/ ≈
≈ 1/S
1/S S sp
S /SS
sp
/SSH
H
RCdelay
RC delay(T)
(T) 11 ≈ 1/ SS
≈ 1/ ≈≈1/S
1/S ≈≈SSWWSSHH/S
/S2 2
2
Voltagedrop
drop(IR)
(IR) 1/ SS 1/S
Voltage 11 1/ 1/S SSWWSSHH/S/S2
Current density (J)
Current density (J) SS SS 11 S S
SWWSHH/S /S

not good for packing density

Global Interconnects under Different Scaling Rules

Table 5.2 Scaling of Global Interconnections

Ideal
Ideal Constant
Constant Constant Generalized
Constant Generalized
Parameter
Parameter Scaling
Scaling Dimension
Dimension Delay
Delay Scaling
Scaling
Thickness(H
Thickness (Hintint) ) 1/S 11 SSCC 1/SHH
1/S
1/S
Width(W
Width (Wintint) ) 1/S
1/S 11 SSCC 1/SWW
1/S
Separation(W
Separation (Wspsp) ) 1/S
1/S 11 SSCC 1/Sspsp
1/S
Insulatorthickness
Insulator thickness(t(toxox
)) 1/S
1/S 11 SSCC 1/Soxox
1/S
Length(l(llocloc
Length )) SSC
C
SSC
C
SSC
C
SSC
C

2
Resistance(R
(Rintint) ) 2
SSCC 1/SCC SSWWSSHS
HS C
SSSSC
C
Resistance 1/S C

Capacitance (Cintint) )
Capacitance (C S
SC C
SSCC SSCC ≈≈SSCC
2 2 2 2
RCdelay
delay(T)
(T) 11
SS(S(SCC) ) (SCC) )
(S SSWWSSHH(S(SCC) )
2 2 2 2
RC
≈≈1/S
1/S ≈≈SS SS /S
/S22
S: Scaling factor for device dimensions.
Sc:Scaling factor for chip size
Interconnect Parameters from NTRS’97

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

Res. ρ (uΩ
Ω /cm) 3.3 2.2 2.2 2.2 2.2 1.8
Dielectric constant 3.55 2.75 2.25 1.75 1.75 1.5
Min. wire width 0.25 0.18 0.15 0.13 0.10 0.07
Min. wire spacing 0.34 0.24 0.21 0.17 0.14 0.10
Metal aspect ratio 1.8:1 1.8:1 2.0:1 2.1:1 2.4:1 2.7:1
Via aspect ratio 2.2:1 2.2:1 2.4:1 2.5:1 2.7:1 2.9:1
Vdd (V) 2.15 1.65 1.35 1.35 1.05 0.75

Capacitance Computation

Cx

Ca Cf

n Capacitance extraction using a 3D field

solver (FastCap)
Derived Interconnect & Device Parameters
Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07
2X min. Ca (aF/um) 29.0 21.2 16.2 12.0 14.4 8.56
width & Cf (aF/um) 41.8 30.2 24.8 18.3 14.1 14.8
spacing
Cx(aF/um) 71.0 58.3 49.4 42.8 45.3 41.6
5X min. Ca (aF/um) 73.5 53.6 40.6 30.0 26.6 19.5
width & Cf (aF/um) 63.5 47.3 38.4 28.5 28.2 23.6
spacing
Cx(aF/um) 18.3 16.9 15.4 14.8 16.5 16.7
Buffer input cap. (fF) 0.17 0.12 0.11 0.085 0.070 0.042
Ω)
Buffer Rd (x10KΩ 1.71 1.86 2.26 2.25 2.39 2.42
Buffer intrin. delay (ps) 70.5 51.1 48.7 45.8 39.2 21.9

Impact of Interconnect Optimization on

Future Technology Generations
10 1mm

2cm DS

2cm BIS
1
Delay (ns)

2cm BISWS

Intrinsic gate
delay

0.1

0.01
0.25 0.18 0.15 0.13 0.1 0.07
Technology ( u m)
 Impact of Interconnect Optimization on
Future Technology Generations

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

1mm (ns) 0.059 0.049 0.051 0.044 0.052 0.042
2cm DS (ns) 2.589 2.48 2.65 2.62 3.73 4.67
2cm BIS (ns) 1.779 1.55 1.59 1.51 1.74 1.55
2cm BISWS (ns) 0.895 0.793 0.77 0.7 0.77 0.672

Significance of Coupling Capacitance

Cx/Ctotal
1
Min. Spacing
0.8

0.6
2x Min. Spacing
0.4

0.2

0
0.25 0.18 0.15 0.13 0.1 0.07

Technology Generation (um)

 Coupling Noise
0.350
0.300
a pair of in-phase aggressors
Noise (% Vdd)

0.250 a pair of skewed

0.200
0.150
0.100 one aggressor

0.050
0.000
250 180 150 100 70
Coupling noise from Technology
two adjacent(nm)
aggressors to the middle victim wire
with 2x min. spacing. Rise time is 10% of project clock period.

•Capacitive coupling depends strongly on both spatial and temporal relations!

Implications

n Communication is more expensive than computation

n Interconnect performance has become the bottleneck of
the overall circuit/system performance
n Interconnect modeling and optimization has become
very difficult due to the distributed nature of
interconnects and their spatial and temporal
interactions
n A new design paradigm/flow is needed to handle
interconnect-dominated designs in the future
VLSI Design Cycle

System Specification

Functional Design

X=(AB*CD)+(A+D)+(A(B+C))

Logic Design Y=(A(B+C))+AC+D+A(BC+D))

Circuit Design

VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging
 Need A New Paradigm for VLSI Design

Interconnection Transistors/Cells

Transistors/Cells Interconnection

Conventional Approach New Approach

Interconnect-Driven Design

Paradigm Change in Software Design

Data Program

Program Data/Object

Conventional Approach New Approach

Data Base Design

Object-oriented design
Summary

n Technology scaling according to Moore’s Law has been

the driving force behind the exponential growth of the
semiconductor industry
n Interconnect (esp. global interconnect) performance
and noise have become the bottleneck of the overall
system design
n Interconnect modeling and optimization has become
very important, yet difficult
n A new design paradigm is needed for interconnect-
driven (or interconnect-centric) design

Homework (due Sept. 20th outside EH3432)

n Read ITRS’99 ORTC and Interconnect

n [Link] (1999 edition)
n ORTC: overall roadmap technology characteristics
n Find two categories of differences between NTRS’97 (in this
notes) and ITRS’99 interconnect characteristics, and explain
reasons for such changes

n An open book quiz will be scheduled based on ITRS

ORTC and interconnect