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Course Name: Computer Architecture and Organization
Assignment- Week 5
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
How many minimum external connections are required for a 4096 × 16-bit memory chip?
a. 45
b. 47
c. 32
d. 48
Correct Answer: c
Detailed Solution:
There are 4096 addressable words.
Number of address lines = log(4096)=12
Data lines:
Word width = 16 bits → 16 data pins.
Control lines:
Use R/W′ and CS′ → 2 control pins.
Power & Ground:
VDD and GND → 2 pins.
Total = 12 (address) + 16 (data) + 2 (control) + 2 (power/ground) = 32
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QUESTION 2:
In a DRAM design, how many transistors and how many capacitors are required to implement a
64-bit word (i.e., 64 storage cells)?
a. 32 transistors and 32 capacitors
b. 64 transistors and 64 capacitors
c. 128 transistors and 128 capacitors
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d. 64 transistors and 128 capacitors
Correct Answer: b
Detailed Solution:
A DRAM cell is implemented as 1 transistor + 1 capacitor (often called 1T1C). Therefore, for
NNN bits, you need NNN transistors and NNN capacitors. The lecture/solutions material
explicitly contrasts this with SRAM’s 6-transistor cell and states DRAM uses one transistor
and one capacitor per cell.
For a 64-bit word:
• Transistors required =64×1=64
• Capacitors required =64×1=64
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QUESTION 3:
Which of the statements below is/are true?
a. SRAM does not require refresh circuitry, whereas DRAM requires periodic
refresh.
b. For the same capacity and word width, DRAM has larger cell area per bit than
SRAM.
c. Cache memories are typically built using SRAM, while main memory uses DRAM.
d. The access time of SRAM is higher than that of DRAM.
e. In DRAM, address lines are often multiplexed into row and column parts, driven
by RAS′ and CAS′.
Correct Answer: a, c ,e
Detailed Solution:
Option (a): True.
SRAM stores data in a latch and doesn’t need refresh; DRAM stores charge on a capacitor and
does need periodic refresh to counter leakage.
Option (b): False.
A DRAM cell uses 1 transistor + 1 capacitor (1T1C), giving higher density / smaller area than
an SRAM cell, which uses 6 transistors. Hence DRAM area per bit is smaller, not larger.
Option (c): True.
Standard system organization: SRAM → cache, DRAM → main memory.
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Option (d): False.
SRAM is the faster technology (lower access time) and is used for fast caches; DRAM has
higher access time.
Option (e): True.
Asynchronous DRAM uses multiplexed addresses (row then column) captured by active-low
RAS′ and CAS′ strobes.
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QUESTION 4:
Consider a 2 Mbit memory organized as 2048 (rows) and 128 (columns). If the data bus is 8-bit
wide, the total number of address lines required will be:
a. 18
b. 14
c. 15
d. 20
Correct Answer: a
Detailed Solution:
The total number of address lines is the sum of the bits needed to select the row and the bits
needed to select the column (i.e., the number of addressable words).
1. Check sizes as powers of two
• 2 Mbit = 221 bits.
• Data bus = 8 bits = 23.
So the number of addressable words (words of 8 bits) = 2 21/23=218. Therefore total
address lines = 18.
2. Row/column breakdown (alternate view)
• Row count = 2048 = 211 ⇒ row-address bits = 11.
• Column count = 128 = 27 ⇒ column-address bits = 7.
Total address bits = 11+7=18. Both derivations match.
Total = 18 address lines.
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QUESTION 5:
For a DDR memory module with a bus clock of 400 MHz and a 128-bit wide data path, what is
the maximum data transfer rate?
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a. 6.4 GB/s
b. 25.6 GB/s
c. 12.8 GB/s
d. 3.2 GB/s
Correct Answer: c
Detailed Solution:
DDR = double data rate, so it transfers data on both clock edges.
Transfers per second = 2× bus clock
= 2×400,000,000=800,000,000 transfers/second.
Bits per transfer = 128 bits.
Bits per second = transfers/sec × bits/transfer
= 800,000,000 × 128
Compute explicitly:
800,000,000 × 100 = 80,000,000,000
800,000,000 × 100=80,000,000,000
800,000,000 × 20 = 16,000,000,000
800,000,000 × 8 = 6,400,000,000
Sum = 80,000,000,000 + 16,000,000,000 + 6,400,000,000 = 102,400,000,000 bits /sec.
Bytes per second = bits/sec ÷ 8
= 102,400,000,000 ÷ 8 = 12,800,000,000 bytes/sec.
Convert to gigabytes/sec (GB/s): 12,800,000,000 bytes/sec = 12.8 GB/s.
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QUESTION 6:
You have 4 KByte memory chips. How many such chips are required to build a 32 KByte
memory system? Assume the processor data lines are 8-bits wide (byte-oriented). What will be
the address range for selecting the 3rd memory chip, assuming the first chip is numbered 0?
a. 8, 1800H to 1FFFH
b. 8, 2000H to 27FFH
c. 8, 1000H to 1FFFH
d. 8, 2000H to 2FFFH
Correct Answer: d
Detailed Solution:
Each memory chip has 4 KB=212 bytes, and the total memory required is 32 KB=215 bytes.
Therefore, the number of chips needed is 215/212=23=8, numbered from 0 to 7. Since the
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system is byte-addressable, 15 address lines (A14..A0) are needed. The lower 12 lines
(A11..A0) select a byte within a chip, while the upper 3 lines (A14..A12) select the chip
number. As per the question, the 1st chip is numbered 0, the 2nd chip numbered 1, and the
3rd chip numbered 2. For chip index 2, the chip-select bits are A14..A12 = 010, which gives a
start address 010_0000_0000_0000₂ = 2000H and an end address 010_1111_1111_1111₂ =
2FFFH.
For clarity, the chip address ranges are:
• Chip 0: 000_0000_0000_0000 → 0000H – 0FFFH
• Chip 1: 001_0000_0000_0000 → 1000H – 1FFFH
• Chip 2: 010_0000_0000_0000 → 2000H – 2FFFH
• Chip 3: 011_0000_0000_0000 → 3000H – 3FFFH
Thus, the 3rd chip (index 2) has the address range 2000H – 2FFFH.
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QUESTION 7:
Consider a memory system that takes 15 nanoseconds to service the access of a single 32-bit
word. What will be the maximum data transfer rate?
a. 2133.33 Mbits per second
b. 4266.67 Mbits per second
c. 266.67 Mbits per second
d. 1066.67 Mbits per second
Correct Answer: a
Detailed Solution:
In 15 nsec, we can transfer 32 bits.
So, in 1 sec, we can transfer 32 / (15 x 10-9) = 2.133 x 109 = 2133 Mbits
The correct option is (a).
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QUESTION 8:
Four 8 MByte memory chips (named M0, M1, M2, M3) are connected together to form an
interleaved byte-addressable memory system. The processor is byte-oriented. Which memory
modules will the addresses 00ABC3E1H and 00F4CDE2H map to?
a. M1 and M2
b. M0 and M2
c. M1 and M3
d. M1 and M4
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e. M3 and M4
Correct Answer: a
Detailed Solution:
The 8Mbyte memory chip will have 25 address lines, as 225 = 8M.
The total memory system will contain 4 such chips, and hence will have 25 address lines.
The high-order address lines A24..A2 will be connected to the address lines of the four chips,
while the low-order two address lines will be selecting one of the four chips:
M0: A1 = 0, A0 = 0
M1: A1 = 0, A0 = 1
M2: A1 = 1, A0 = 0
M3: A1 = 1, A0 = 1
For the memory address 00ABC3E1, A1 = 0, A0 = 1 ➔ M1
For the memory address 00F4CDE2, A1 = 1, A0 = 0 ➔ M2
The correct option is (a).
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QUESTION 9:
Which of the following is/are true?
a. Single Data Rate (SDR) SDRAM transfers two words per clock cycle.
b. Double Data Rate (DDR) SDRAM transfers data on both the rising and falling edges of
the clock.
c. A Dual In-line Memory Module (DIMM) is made up of multiple DRAM ICs mounted on a
PCB.
d. A SO-DIMM is electrically incompatible with a regular DIMM (they are always different
in signaling, not only form factor).
e. SDRAM devices often use an internal column counter to support burst transfers without
external CAS pulses.
Correct Answer: b, c, e
Detailed Solution:
b (True): DDR transfers on both rising and falling clock edges (double the transfers per clock).
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c (True): A DIMM is a module made of multiple DRAM ICs on a PCB to provide capacity and a
wide data path.
e (True): SDRAM commonly has an internal column counter to support burst/page transfers
without repeated external CAS.
a (False): SDR (single data rate) transfers one word per clock, not two.
d (False): SO-DIMM differs in form factor; it is not always electrically different in signaling.
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QUESTION 10:
In SDRAM, what does “burst mode” operation refer to?
a. Accessing multiple consecutive columns from the same row with a single column
address input.
b. Using multiple DRAM chips in parallel to widen the data bus.
c. Refreshing all rows in a short burst at startup.
d. Switching between SDR and DDR modes dynamically.
Correct Answer: a
Detailed Solution:
Burst mode allows SDRAM to read/write multiple consecutive columns from a selected row
by giving only the starting column address; an internal column counter handles the rest,
enabling high-speed block transfers.
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