COMPUTER ORGANIZATION

MODULE – 1

Basic operational concepts: -

To perform a given task an appropriate program consisting of a list of instructions is
stored in the memory. Individual instructions are brought from the memory into the
processor, which executes the specified operations. Data to be stored are also stored in the
memory.

Example: - Add LOCA, R0

This instruction adds the operand at memory location LOCA, to operand in register
R0 & places the sum into register. This instruction requires the performance of several steps,

1. First the instruction is fetched from the memory into the processor.
2. The operand at LOCA is fetched and added to the contents of R0
3. Finally the resulting sum is stored in the register R0

Transfers between the memory and the processor are started by sending the address
of the memory location to be accessed to the memory unit and issuing the appropriate control
signals. The data are then transferred to or from the memory.

MEMORY

MAR MDR
CONTROL

PC R0
R1
… ALU
…
IR …
…
Rn-1
n- s

Figure: Connections between the processor and the memory

 The fig shows how memory & the processor can be connected. In addition to the
ALU & the control circuitry, the processor contains a number of registers used for several
different purposes.

The instruction register (IR):- Holds the instructions that is currently being executed. Its
output is available for the control circuits which generates the timing signals that control the
various processing elements in one execution of instruction.

The program counter PC:-

This is another specialized register that keeps track of execution of a program. It
contains the memory address of the next instruction to be fetched and executed.

Besides IR and PC, there are n-general purpose registers R0 through Rn-1.
The other two registers which facilitate communication with memory are: -
1. MAR – (Memory Address Register):- It holds the address of the location to be
accessed.
2. MDR – (Memory Data Register):- It contains the data to be written into or read out
of the address location.

Operating steps are

1. Execution of the program starts when the PC is set to point to the first instruction of
the program.
2. Contents of PC are transferred to MAR and a Read Control Signal is sent to the
memory.
3. After the time required to access the memory, the word is read out of the memory and
loaded into the MDR.
4. Now contents of MDR are transferred to the IR & now the instruction is ready to be
decoded and executed.
5. If the instruction involves an operation by the ALU, it is necessary to obtain the
required operands.
6. An operand in the memory is fetched by sending its address to MAR & Initiating a
read cycle.
7. When the operand has been read from the memory to the MDR, it is transferred from
MDR to the ALU.
8. After one or two cycles, the ALU can perform the desired operation.
9. If the result of this operation is to be stored in the memory, the result is sent to MDR.
10. Address of location where the result is stored is sent to MAR & a write cycle is
initiated.
11. The contents of PC are incremented so that PC points to the next instruction that is to
be executed.

Bus structure: -
The simplest and most common way of interconnecting various parts of the
computer.

A group of lines that serve as a connecting port for several devices is called a bus.

In addition to the lines that carry the data, the bus must have lines for address and
control purpose.

Simplest way to interconnect is to use the single bus as shown

 INPUT MEMORY PROCESSOR OUTPUT

Figure: Single bus structure

Since the bus can be used for only one transfer at a time, only two units can actively
use the bus at any given time. Bus control lines are used to arbitrate multiple requests for use
of one bus.

Single bus structure is

 Low cost
 Very flexible for attaching peripheral devices

Multiple bus structure certainly increases, the performance but also increases the cost
significantly.

Performance: -
The most important measure of the performance of a computer is how quickly it can
execute programs. The speed with which a computer executes program is affected by the
design of its hardware. For best performance, it is necessary to design the compiles, the
machine instruction set, and the hardware in a coordinated way.

The total time required to execute the program is elapsed time is a measure of the
performance of the entire computer system. It is affected by the speed of the processor, the
disk and the printer. The time needed to execute a instruction is called the processor time.

Just as the elapsed time for the execution of a program depends on all units in a
computer system, the processor time depends on the hardware involved in the execution of
individual machine instructions. This hardware comprises the processor and the memory
which are usually connected by the bus as shown in the fig c.

Main Cache Processor

Memory Memory

Bus
 Fig d :The processor cache

The pertinent parts of the fig. c is repeated in fig. d which includes the cache memory
as part of the processor unit.

Let us examine the flow of program instructions and data between the memory and
the processor. At the start of execution, all program instructions and the required data are
stored in the main memory. As the execution proceeds, instructions are fetched one by one
over the bus into the processor, and a copy is placed in the cache later if the same instruction
or data item is needed a second time, it is read directly from the cache.

The processor and relatively small cache memory can be fabricated on a single IC
chip. The internal speed of performing the basic steps of instruction processing on chip is
very high and is considerably faster than the speed at which the instruction and data can be
fetched from the main memory. A program will be executed faster if the movement of
instructions and data between the main memory and the processor is minimized, which is
achieved by using the cache.

For example:- Suppose a number of instructions are executed repeatedly over a short period
of time as happens in a program loop. If these instructions are available in the cache, they can
be fetched quickly during the period of repeated use. The same applies to the data that are
used repeatedly.

Processor clock: -
Processor circuits are controlled by a timing signal called clock. The clock designer
the regular time intervals called clock cycles. To execute a machine instruction the processor
divides the action to be performed into a sequence of basic steps that each step can be
completed in one clock cycle. The length P of one clock cycle is an important parameter that
affects the processor performance.

Processor used in today’s personal computer and work station have a clock rates that
range from a few hundred million to over a billion cycles per second.

Basic performance equation: -

We now focus our attention on the processor time component of the total elapsed
time. Let ‘T’ be the processor time required to execute a program that has been prepared in
some high-level language. The compiler generates a machine language object program that
corresponds to the source program. Assume that complete execution of the program requires
the execution of N machine cycle language instructions. The number N is the actual number
of instruction execution and is not necessarily equal to the number of machine cycle
instructions in the object program. Some instruction may be executed more than once, which
in the case for instructions inside a program loop others may not be executed all, depending
on the input data used.

Suppose that the average number of basic steps needed to execute one machine cycle
instruction is S, where each basic step is completed in one clock cycle. If clock rate is ‘R’
cycles per second, the program execution time is given by

this is often referred to as the basic performance equation.

 We must emphasize that N, S & R are not independent parameters changing one may
affect another. Introducing a new feature in the design of a processor will lead to improved
performance only if the overall result is to reduce the value of T.

Clock rate:- These are two possibilities for increasing the clock rate ‘R’.

1. Improving the IC technology makes logical circuit faster, which reduces the time of
execution of basic steps. This allows the clock period P, to be reduced and the clock
rate R to be increased.
2. Reducing the amount of processing done in one basic step also makes it possible to
reduce the clock period P. however if the actions that have to be performed by an
instructions remain the same, the number of basic steps needed may increase.

Increase in the value ‘R’ that are entirely caused by improvements in IC technology
affects all aspects of the processor’s operation equally with the exception of the time it takes
to access the main memory. In the presence of cache the percentage of accesses to the main
memory is small. Hence much of the performance gain excepted from the use of faster
technology can be realized.

Performance measurements:-
It is very important to be able to access the performance of a computer, comp
designers use performance estimates to evaluate the effectiveness of new features.

The previous argument suggests that the performance of a computer is given by the
execution time T, for the program of interest.

Inspite of the performance equation being so simple, the evaluation of ‘T’ is highly
complex. Moreover the parameters like the clock speed and various architectural features are
not reliable indicators of the expected performance.

Hence measurement of computer performance using bench mark programs is done to

make comparisons possible, standardized programs must be used.

The performance measure is the time taken by the computer to execute a given bench
mark. Initially some attempts were made to create artificial programs that could be used as
bench mark programs. But synthetic programs do not properly predict the performance
obtained when real application programs are run.

A non profit organization called SPEC- system performance evaluation corporation

selects and publishes bench marks.

The program selected range from game playing, compiler, and data base applications
to numerically intensive programs in astrophysics and quantum chemistry. In each case, the
program is compiled under test, and the running time on a real computer is measured. The
same program is also compiled and run on one computer selected as reference.
The ‘SPEC’ rating is computed as follows.

Running time on the reference computer

SPEC rating =
Running time on the computer under test
If the SPEC rating = 50

Means that the computer under test is 50 times as fast as the ultra sparc 10. This is
repeated for all the programs in the SPEC suit, and the geometric mean of the result is
computed.

Let SPECi be the rating for program ‘i’ in the suite. The overall SPEC rating for the
computer is given by

SPEC rating =

Where ‘n’ = number of programs in suite.

Since actual execution time is measured the SPEC rating is a measure of the
combined effect of all factors affecting performance, including the compiler, the OS, the
processor, the memory of comp being tested.
Number Representation:- Consider an n-bit vector
B=
Where = 0 or 1 for 0 . This vector can represent unsigned integer values V in the
range 0 to -1, where
V(B) =
We obviously need to represent both positive and negative numbers. Three systems are used
for representing such numbers :
 Sign-and-magnitude
 1’s-complement
 2’s-complement
In all three systems, the leftmost bit is 0 for positive numbers and 1 for negative numbers. Fig
2.1 illustrates all three representations using 4-bit numbers. Positive values have identical
representations in al systems, but negative values have different representations. In the sign-
and-magnitude systems, negative values are represented by changing the most significant bit
(b3 in figure 2.1) from 0 to 1 in the B vector of the corresponding positive value. For
example, +5 is represented by 0101, and -5 is represented by 1101. In 1’s-complement
representation, negative values are obtained by complementing each bit of the corresponding
positive number. Thus, the representation for -3 is obtained by complementing each bit in the
vector 0011 to yield 1100. clearly, the same operation, bit complementing, is done in
converting a negative number to the corresponding positive value. Converting either way is
referred to as forming the 1’s-complement of a given number. Finally, in the 2’s-complement
system, forming the 2’s-complement of a number is done by subtracting that number from 2n.
B Values represented
Sign and
1's 2's
b3b2b1 b0 magnitude complement complement
0 1 1 1 +7 +7 +7
0 1 1 0 +6 +6 +6
0 1 0 1 +5 +5 +5
0 1 0 0 +4 +4 +4
0 0 1 1 +3 +3 +3
0 0 1 0 +2 +2 +2
0 0 0 1 +1 +1 +1
0 0 0 0 +0 +0 +0
1 0 0 0 -0 -0 -0
1 0 0 1 -1 -1 -1
1 0 1 0 -2 -2 -2
1 0 1 1 -3 -3 -3
1 1 0 0 -4 -4 -4
1 1 0 1 -5 -5 -5
1 1 1 0 -6 -6 -6
1 1 1 1 -7 -7 -7
Hence, the 2’s complement of a number is obtained by adding 1 to the 1’s complement of that
number.

Addition of Positive numbers:-

Consider adding two 1-bit numbers. The results are shown in figure 2.2. Note that the
sum of 1 and 1 requires the 2-bit vector 10 to represent the value 2. We say that the sum is 0
and the carry-out is 1. In order to add multiple-bit numbers, we use a method analogous to
that used for manual computation with decimal numbers. We add bit pairs starting from the
low-order (right) and of the bit vectors, propagating carries toward the high-order (left) end.
 0 1 0 1
+0 +0 +1 +1
____ ____ ___ ___
0 1 1 10

Carry-out
Figure 2.2 Addition of 1-bit numbers.

MEMORY LOCATIONS AND ADDRESSES:-

Number and character operands, as well as instructions, are stored in the memory of a
computer. The memory consists of many millions of storage cells, each of which can store a
bit of information having the value 0 or 1. Because a single bit represents a very small
amount of information, bits are seldom handled individually. The usual approach is to deal
with them in groups of fixed size. For this purpose, the memory is organized so that a group
of n bits can be stored or retrieved in a single, basic operation. Each group of n bits is referred
to as a word of information, and n is called the word length. The memory of a computer can
be schematically represented as a collection of words as shown in figure (a).

Modern computers have word lengths that typically range from 16 to 64 bits. If the
word length of a computer is 32 bits, a single word can store a 32-bit 2’s complement number
or four ASCII characters, each occupying 8 bits. A unit of 8 bits is called a byte.

Accessing the memory to store or retrieve a single item of information, either a word
or a byte, requires distinct names or addresses for each item location. It is customary to use
numbers from 0 through 2K-1, for some suitable values of k, as the addresses of successive
locations in the memory. The 2k addresses constitute the address space of the computer, and
the memory can have up to 2k addressable locations. 24-bit address generates an address
space of 224 (16,777,216) locations. A 32-bit address creates an address space of 2 32 or 4G (4
giga) locations.

BYTE ADDRESSABILITY:-
We now have three basic information quantities to deal with: the bit, byte and word.
A byte is always 8 bits, but the word length typically ranges from 16 to 64 bits. The most
practical assignment is to have successive addresses refer to successive byte

Fig a Memory words

n bits First word

Second word
…
…
… i-th word

…
…
 … Last word

(a) A signed integer

32 bits
b31 b30 ……. b1 b0

Sign bit: b31 = 0 for positive numbers

b32 = 1 for negative numbers

(b) Four characters

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII
Character character character character

Locations in the memory. This is the assignment used in most modern computers, and is the
one we will normally use in this book. The term byte-addressable memory is use for this
assignment. Byte locations have addresses 0,1,2, …. Thus, if the word length of the machine
is 32 bits, successive words are located at addresses 0,4,8,…., with each word consisting of
four bytes.

BIG-ENDIAN AND LITTLE-ENDIAN ASIGNMENTS:-

There are two ways that byte addresses can be assigned across words, as shown in fig
b. The name big-endian is used when lower byte addresses are used for the more significant
bytes (the leftmost bytes) of the word. The name little-endian is used for the opposite
ordering, where the lower byte addresses are used for the less significant bytes (the rightmost
bytes) of the word.

In addition to specifying the address ordering of bytes within a word, it is also

necessary to specify the labeling of bits within a byte or a word. The same ordering is also
used for labeling bits within a byte, that is, b7, b6, …., b0, from left to right.

Word
Address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

…. ….
…. ….
…. ….

2k-4 2k-3 2k-2 2k-1 2k-1 2k-2 2k-3 2k-4

2k-4 2k-4

(a) Big-endian assignment (b) Little-endian assignment

WORD ALIGNMENT:-
In the case of a 32-bit word length, natural word boundaries occur at addresses 0, 4,
8, …, as shown in above fig. We say that the word locations have aligned addresses . in
general, words are said to be aligned in memory if they begin at a byte address that is a
multiple of the number of bytes in a word. The memory of bytes in a word is a power of 2.
Hence, if the word length is 16 (2 bytes), aligned words begin at byte addresses 0,2,4,…, and
for a word length of 64 (23 bytes), aligned words begin at bytes addresses 0,8,16 ….

There is no fundamental reason why words cannot begin at an arbitrary byte address.
In that case, words are said to have unaligned addresses. While the most common case is to
use aligned addresses, some computers allow the use of unaligned word addresses.

ACCESSING NUMBERS, CHARACTERS, AND CHARACTER STRINGS:-

A number usually occupies one word. It can be accessed in the memory by specifying
its word address. Similarly, individual characters can be accessed by their byte address.

In many applications, it is necessary to handle character strings of variable length.

The beginning of the string is indicated by giving the address of the byte containing its first
character. Successive byte locations contain successive characters of the string. There are two
ways to indicate the length of the string. A special control character with the meaning “end of
string” can be used as the last character in the string, or a separate memory word location or
processor register can contain a number indicating the length of the string in bytes.

MEMORY OPERATIONS:-
Both program instructions and data operands are stored in the memory. To execute an
instruction, the processor control circuits must cause the word (or words) containing the
instruction to be transferred from the memory to the processor. Operands and results must
also be moved between the memory and the processor. Thus, two basic operations involving
the memory are needed, namely, Load (or Read or Fetch) and Store (or Write).

The load operation transfers a copy of the contents of a specific memory location to
the processor. The memory contents remain unchanged. To start a Load operation, the
processor sends the address of the desired location to the memory and requests that its
contents be read. The memory reads the data stored at that address and sends them to the
processor.

The store operation transfers an item of information from the processor to a specific
memory location, destroying the former contents of that location. The processor sends the
address of the desired location to the memory, together with the data to be written into that
location.

An information item of either one word or one byte can be transferred between the
processor and the memory in a single operation. Actually this transfer in between the CPU
register & main memory.

INSTRUCTIONS AND INSTRUCTION SEQUENCING:-

A computer must have instructions capable of performing four types of operations.
  Data transfers between the memory and the processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

REGISTER TRANSFER NOTATION:-

Transfer of information from one location in the computer to another. Possible
locations that may be involved in such transfers are memory locations that may be involved
in such transfers are memory locations, processor registers, or registers in the I/O subsystem.
Most of the time, we identify a location by a symbolic name standing for its hardware binary
address.

Example, names for the addresses of memory locations may be LOC, PLACE, A,
VAR2; processor registers names may be R0, R5; and I/O register names may be DATAIN,
OUTSTATUS, and so on. The contents of a location are denoted by placing square brackets
around the name of the location. Thus, the expression
R1 [LOC]
Means that the contents of memory location LOC are transferred into processor register R1.

As another example, consider the operation that adds the contents of registers R1 and
R2, and then places their sum into register R3. This action is indicated as
R3 [R1] + [R2]

This type of notation is known as Register Transfer Notation (RTN). Note that the
right-hand side of an RTN expression always denotes a value, and the left-hand side is the
name of a location where the value is to be places, overwriting the old contents of that
location.

ASSEMBLY LANGUAGE NOTATION:-

Another type of notation to represent machine instructions and programs. For this, we
use an assembly language format. For example, an instruction that causes the transfer
described above, from memory location LOC to processor register R1, is specified by the
statement
Move LOC, R1

The contents of LOC are unchanged by the execution of this instruction, but the old
contents of register R1 are overwritten.

The second example of adding two numbers contained in processor registers R1 and
R2 and placing their sum in R3 can be specified by the assembly language statement
Add R1, R2, R3

BASIC INSTRUCTIONS:-
The operation of adding two numbers is a fundamental capability in any computer.
The statement
C=A+B

In a high-level language program is a command to the computer to add the current

values of the two variables called A and B, and to assign the sum to a third variable, C. When
the program containing this statement is compiled, the three variables, A, B, and C, are
assigned to distinct locations in the memory. We will use the variable names to refer to the
corresponding memory location addresses. The contents of these locations represent the
values of the three variables. Hence, the above high-level language statement requires the
action.
C [A] + [B]

To carry out this action, the contents of memory locations A and B are fetched from
the memory and transferred into the processor where their sum is computed. This result is
then sent back to the memory and stored in location C.

Let us first assume that this action is to be accomplished by a single machine

instruction. Furthermore, assume that this instruction contains the memory addresses of the
three operands – A, B, and C. This three-address instruction can be represented symbolically
as
Add A, B, C

Operands A and B are called the source operands, C is called the destination operand,
and Add is the operation to be performed on the operands. A general instruction of this type
has the format.
Operation Source1, Source 2, Destination

If k bits are needed for specify the memory address of each operand, the encoded
form of the above instruction must contain 3k bits for addressing purposes in addition to the
bits needed to denote the Add operation.

An alternative approach is to use a sequence of simpler instructions to perform the

same task, with each instruction having only one or two operands. Suppose that two-address
instructions of the form
Operation Source, Destination

Are available. An Add instruction of this type is

Add A, B

Which performs the operation B [A] + [B].

A single two-address instruction cannot be used to solve our original problem, which
is to add the contents of locations A and B, without destroying either of them, and to place
the sum in location C. The problem can be solved by using another two-address instruction
that copies the contents of one memory location into another. Such an instruction is
Move B, C

Which performs the operations C [B], leaving the contents of location B unchanged.

Using only one-address instructions, the operation C [A] + [B] can be performed
by executing the sequence of instructions
Load A
Add B
Store C

Some early computers were designed around a single accumulator structure. Most
modern computers have a number of general-purpose processor registers – typically 8 to 32,
and even considerably more in some cases. Access to data in these registers is much faster
than to data stored in memory locations because the registers are inside the processor.
Let Ri represent a general-purpose register. The instructions
Load A, Ri
Store Ri, A and
Add A, Ri

Are generalizations of the Load, Store, and Add instructions for the single-accumulator case,
in which register Ri performs the function of the accumulator.

When a processor has several general-purpose registers, many instructions involve

only operands that are in the register. In fact, in many modern processors, computations can
be performed directly only on data held in processor registers. Instructions such as
Add Ri, Rj
Or
Add Ri, Rj, Rk
In both of these instructions, the source operands are the contents of registers Ri and
Rj. In the first instruction, Rj also serves as the destination register, whereas in the second
instruction, a third register, Rk, is used as the destination.

It is often necessary to transfer data between different locations. This is achieved

with the instruction
Move Source, Destination
When data are moved to or from a processor register, the Move instruction can be
used rather than the Load or Store instructions because the order of the source and destination
operands determines which operation is intended. Thus,
Move A, Ri
Is the same as
Load A, Ri
And
Move Ri, A
Is the same as
Store Ri, A

In processors where arithmetic operations are allowed only on operands that are
processor registers, the C = A + B task can be performed by the instruction sequence
Move A, Ri
Move B, Rj
Add Ri, Rj
Move Rj, C
In processors where one operand may be in the memory but the other must be in
register, an instruction sequence for the required task would be
Move A, Ri
Add B, Ri
Move Ri, C
The speed with which a given task is carried out depends on the time it takes to
transfer instructions from memory into the processor and to access the operands referenced
by these instructions. Transfers that involve the memory are much slower than transfers
within the processor.

INSTRUCTION EXECUTION AND STRAIGHT-LINE SEQUENCING:-

In the preceding discussion of instruction formats, we used to task C [A] + [B].
fig 2.8 shows a possible program segment for this task as it appears in the memory of a
computer. We have assumed that the computer allows one memory operand per instruction
and has a number of processor registers. The three instructions of the program are in
successive word locations, starting at location i. since each instruction is 4 bytes long, the
second and third instructions start at addresses i + 4 and i + 8.

Address Contents

Begin execution here i Move A, R0 3-instruction

i+4 Add B, R0 program
segment
i+8 Move R0, C

…
…

A
…
…
B Data for the
… program
…
C

Let us consider how this program is executed. The processor contains a register
called the program counter (PC), which holds the address of the instruction to be executed
next. To begin executing a program, the address of its first instruction (I in our example) must
be placed into the PC. Then, the processor control circuits use the information in the PC to
fetch and execute instructions, one at a time, in the order of increasing addresses. This is
called straight-line sequencing. During the execution of each instruction, the PC is
incremented by 4 to point to the next instruction. Thus, after the Move instruction at location
i + 8 is executed, the PC contains the value i + 12, which is the address of the first instruction
of the next program segment.

Executing a given instruction is a two-phase procedure. In the first phase, called

instruction fetch, the instruction is fetched from the memory location whose address is in the
PC. This instruction is placed in the instruction register (IR) in the processor. The instruction
in IR is examined to determine which operation is to be performed. The specified operation is
then performed by the processor. This often involves fetching operands from the memory or
from processor registers, performing an arithmetic or logic operation, and storing the result in
the destination location.

BRANCHING:-

Consider the task of adding a list of n numbers. Instead of using a long list of add
instructions, it is possible to place a single add instruction in a program loop, as shown in fig
b. The loop is a straight-line sequence of instructions executed as many times as needed. It
starts at location LOOP and ends at the instruction Branch > 0. During each pass through this
loop, the address of the next list entry is determined, and that entry is fetched and added to
R0.

i Move NUM1, R0
i+4 Add NUM2, R0
i+8 Add NUM3, R0
…
…
i+4n-4
Add NUMn, R0 i+4n
Move R0, SUM

….
…. SUM
NUM1
NUM2

NUMn
….
….

Move N, R1
Clear R0
Determine address of Program loop
“Next” number and add
“Next” number to R0
Decrement R1
Branch >0 LOOP
Move R0, SUM

…….
…….
…….
SUM
N n
NUM1 NUM2

……
…...
NUMn
…...

Fig b Using a loop to add n numbers

Assume that the number of entries in the list, n, is stored in memory location N, as
shown. Register R1 is used as a counter to determine the number of time the loop is executed.
Hence, the contents of location N are loaded into register R1 at the beginning of the program.
Then, within the body of the loop, the instruction.
 Decrement R1
Reduces the contents of R1 by 1 each time through the loop.
This type of instruction loads a new value into the program counter. As a result, the
processor fetches and executes the instruction at this new address, called the branch target,
instead of the instruction at the location that follows the branch instruction in sequential
address order. A conditional branch instruction causes a branch only if a specified condition
is satisfied. If the condition is not satisfied, the PC is incremented in the normal way, and the
next instruction in sequential address order is fetched and executed.
Branch > 0 LOOP

(branch if greater that 0) is a conditional branch instruction that causes a branch to

location LOOP if the result of the immediately preceding instruction, which is the
decremented value in register R1, is greater that zero. This means that the loop is repeated, as
long as there are entries in the list that are yet to be added to R0. at the end of the nth pass
through the loop, the Decrement instruction produces a value of zero, and hence, branching
does not occur.

CONDITION CODES:-
The processor keeps track of information about the results of various operations for
use by subsequent conditional branch instructions. This is accomplished by recording the
required information in individual bits, often called condition code flags. These flags are
usually grouped together in a special processor register called the condition code register or
status register. Individual condition code flags are set to 1 or cleared to 0, depending on the
outcome of the operation performed.

Four commonly used flags are

N(negative) Set to 1 if the result is negative; otherwise, cleared to 0

Z(zero) Set to 1 if the result is 0; otherwise, cleared to 0
V(overflow) Set ot1 if arithmetic overflow occurs; otherwise, cleared to 0
C(carry) Set to 1 if a carry-out results from the operation; otherwise, cleared to 0

The instruction Branch > 0, discussed in the previous section, is an example of a

branch instruction that tests one or more of the condition flags. It causes a branch if the value
tested is neither negative nor equal to zero. That is, the branch is taken if neither N nor Z is 1.
The conditions are given as logic expressions involving the condition code flags.

In some computers, the condition code flags are affected automatically by

instructions that perform arithmetic or logic operations. However, this is not always the case.
A number of computers have two versions of an Add instruction.

ADDRESSING MODES:-
In general, a program operates on data that reside in the computer’s memory. These
data can be organized in a variety of ways. If we want to keep track of students’ names, we
can write them in a list. Programmers use organizations called data structures to represent the
data used in computations. These include lists, linked lists, arrays, queues, and so on.
 Programs are normally written in a high-level language, which enables the
programmer to use constants, local and global variables, pointers, and arrays. The different
ways in which the location of an operand is specified in an instruction are referred to as
addressing modes.

Table 2.1 Generic addressing modes

Name Assembler syntax Addressing function

Immediate # Value Operand = Value

Register Ri EA = Ri
Absolute (Direct) LOC EA = LOC
Indirect (Ri) EA = [Ri]
(LOC) EA = [LOC]
Index X(Ri) EA = [Ri] + X
Base with index (Ri, Rj) EA = [Ri] + [Rj]
Base with index X (Ri, Rj) EA = [Ri] + [Rj] + X
and offset
Relative X(PC) EA = [PC] + X
Autoincrement (Ri)+ EA = [Ri]; Increment Ri
Autodecrement -(Ri) Decrement Ri; EA = [Ri]

EA = effective address
Value = a signed number

IMPLEMENTATION OF VARIABLE AND CONSTANTS:-

Variables and constants are the simplest data types and are found in almost every
computer program. In assembly language, a variable is represented by allocating a register or
memory location to hold its value. Thus, the value can be changed as needed using
appropriate instructions.

Register mode - The operand is the contents of a processor register; the name (address) of
the register is given in the instruction.

Absolute mode – The operand is in a memory location; the address of this location is given
explicitly in the instruction. (In some assembly languages, this mode is called Direct).

The instruction
Move LOC, R2

Processor registers are used as temporary storage locations where the data is a
register are accessed using the Register mode. The Absolute mode can represent global
variables in a program. A declaration such as
Integer A, B;

Immediate mode – The operand is given explicitly in the instruction.

For example, the instruction
Move 200immediate, R0
 Places the value 200 in register R0. Clearly, the Immediate mode is only used to
specify the value of a source operand. Using a subscript to denote the Immediate mode is not
appropriate in assembly languages. A common convention is to use the sharp sign (#) in front
of the value to indicate that this value is to be used as an immediate operand. Hence, we write
the instruction above in the form
Move #200, R0

INDIRECTION AND POINTERS:-

In the addressing modes that follow, the instruction does not give the operand or its
address explicitly, Instead, it provides information from which the memory address of the
operand can be determined. We refer to this address as the effective address (EA) of the
operand.

Indirect mode – The effective address of the operand is the contents of a register or memory
location whose address appears in the instruction.

To execute the Add instruction in fig (a), the processor uses the value which is in
register R1, as the effective address of the operand. It requests a read operation from the
memory to read the contents of location B. the value read is the desired operand, which the
processor adds to the contents of register R0. Indirect addressing through a memory location
is also possible as shown in fig (b). In this case, the processor first reads the contents of
memory location A, then requests a second read operation using the value B as an address to
obtain the operand.

Fig (a) Through a general-purpose register (b) Through a memory location

Add (A), R0
Add (R1), R0
… …
… Main …
… memory …
A B
Operand …
B …
…
R1 B Register Operands
B

Address Contents

Move N, R1
Move #NUM, R2
Clear R0
LOOP Add (R2), R0
Add #4, R2
Decrement R1
Branch > 0 LOOP
 Move R0, SUM

The register or memory location that contains the address of an operand is called a
pointer. Indirection and the use of pointers are important and powerful concepts in
programming.

In the program shown Register R2 is used as a pointer to the numbers in the list, and
the operands are accessed indirectly through R2. The initialization section of the program
loads the counter value n from memory location N into R1 and uses the immediate addressing
mode to place the address value NUM1, which is the address of the first number in the list,
into R2. Then it clears R0 to 0. The first two instructions in the loop implement the
unspecified instruction block starting at LOOP. The first time through the loop, the
instruction Add (R2), R0 fetches the operand at location NUM1 and adds it to R0. The
second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the
address value NUM2 when the above instruction is executed in the second pass through the
loop.

Where B is a pointer variable. This statement may be compiled into

Move B, R1
Move (R1), A
Using indirect addressing through memory, the same action can be achieved with
Move (B), A

Indirect addressing through registers is used extensively. The above program shows
the flexibility it provides. Also, when absolute addressing is not available, indirect addressing
through registers makes it possible to access global variables by first loading the operand’s
address in a register.

INDEXING AND ARRAYS:-

A different kind of flexibility for accessing operands is useful in dealing with lists
and arrays.

Index mode – the effective address of the operand is generated by adding a constant value to
the contents of a register.

The register use may be either a special register provided for this purpose, or, more
commonly, it may be any one of a set of general-purpose registers in the processor. In either
case, it is referred to as index register. We indicate the Index mode symbolically as
X (Ri)

Where X denotes the constant value contained in the instruction and Ri is the name of
the register involved. The effective address of the operand is given by

EA = X + [Rj]

The contents of the index register are not changed in the process of generating the
effective address. In an assembly language program, the constant X may be given either as an
explicit number or as a symbolic name representing a numerical value.

Fig a illustrates two ways of using the Index mode. In fig a, the index register, R1,
contains the address of a memory location, and the value X defines an offset (also called a
displacement) from this address to the location where the operand is found. An alternative
use is illustrated in fig b. Here, the constant X corresponds to a memory address, and the
contents of the index register define the offset to the operand. In either case, the effective
address is the sum of two values; one is given explicitly in the instruction, and the other is
stored in a register.

Fig (a) Offset is given as a constant

Add 20(R1), R2
…
…
…
1000 1000 R1
…
…
20 = offset …

Operands
1020

Add 1000(R1), R2
…
…
…

1000 20 R1
…
…
20 = offset …

1020 Operand

Fig (b) Offset is in the index register

Move #LIST, R0
Clear R1
Clear R2
Clear R3
Move N, R4
LOOP Add 4(R0), R1
Add 8(R0), R2
Add 12(R0), R3
Add #16, R0
Decrement R4
Branch>0 LOOP
 Move R1, SUM1
Move R2, SUM2
Move R3, SUM3

In the most basic form of indexed addressing several variations of this basic form
provide a very efficient access to memory operands in practical programming situations. For
example, a second register may be used to contain the offset X, in which case we can write
the Index mode as

(Ri, Rj)

The effective address is the sum of the contents of registers Ri and Rj. The second
register is usually called the base register. This form of indexed addressing provides more
flexibility in accessing operands, because both components of the effective address can be
changed.

Another version of the Index mode uses two registers plus a constant, which can be
denoted as

X(Ri, Rj)

In this case, the effective address is the sum of the constant X and the contents of
registers Ri and Rj. This added flexibility is useful in accessing multiple components inside
each item in a record, where the beginning of an item is specified by the (Ri, Rj) part of the
addressing mode. In other words, this mode implements a three-dimensional array.

RELATIVE ADDRESSING:-
We have defined the Index mode using general-purpose processor registers. A useful
version of this mode is obtained if the program counter, PC, is used instead of a general
purpose register. Then, X(PC) can be used to address a memory location that is X bytes away
from the location presently pointed to by the program counter.

Relative mode – The effective address is determined by the Index mode using the program
counter in place of the general-purpose register Ri.

This mode can be used to access data operands. But, its most common use is to
specify the target address in branch instructions. An instruction such as

Branch > 0 LOOP

Causes program execution to go to the branch target location identified by the name
LOOP if the branch condition is satisfied. This location can be computed by specifying it as
an offset from the current value of the program counter. Since the branch target may be either
before or after the branch instruction, the offset is given as a signed number.

Autoincrement mode – the effective address of the operand is the contents of a register
specified in the instruction. After accessing the operand, the contents of this register are
automatically to point to the next item in a list.

(Ri)+
Autodecrement mode – the contents of a register specified in the instruction are first
automatically decremented and are then used as the effective address of the operand.

-(Ri)

Move N, R1
Move #NUM1, R2
Clear R0
LOOP Add (R2)+, R0
Decrement R1
Branch>0 LOOP
Move R0, SUM

Fig c The Autoincrement addressing mode used in the program of fig 2.12

ASSEMBLY LANGUAGE:-
Machine instructions are represented by patterns of 0s and 1s. Such patterns are
awkward to deal with when discussing or preparing programs. Therefore, we use symbolic
names to represent the pattern. So far, we have used normal words, such as Move, Add,
Increment, and Branch, for the instruction operations to represent the corresponding binary
code patterns. When writing programs for a specific computer, such words are normally
replaced by acronyms called mnemonics, such as MOV, ADD, INC, and BR. Similarly, we
use the notation R3 to refer to register 3, and LOC to refer to a memory location. A complete
set of such symbolic names and rules for their use constitute a programming language,
generally referred to as an assembly language.

Programs written in an assembly language can be automatically translated into a

sequence of machine instructions by a program called an assembler. When the assembler
program is executed, it reads the user program, analyzes it, and then generates the desired
machine language program. The latter contains patterns of 0s and 1s specifying instructions
that will be executed by the computer. The user program in its original alphanumeric text
format is called a source program, and the assembled machine language program is called an
object program.

ASSEMBLER DIRECTIVES:-
In addition to providing a mechanism for representing instructions in a program, the
assembly language allows the programmer to specify other information needed to translate
the source program into the object program. We have already mentioned that we need to
assign numerical values to any names used in a program. Suppose that the name SUM is used
to represent the value 200. This fact may be conveyed to the assembler program through a
statement such as

SUM EQU 200

This statement does not denote an instruction that will be executed when the object
program is run; in fact, it will not even appear in the object program. It simply informs the
assembler that the name SUM should be replaced by the value 200 wherever it appears in the
program. Such statements, called assembler directives (or commands), are used by the
assembler while it translates a source program into an object program.
 100 Move N, R1
104 Move # NUM1,R2 108
Clear R0 LOOP 112
Add (R2), R0 116
Add #4, R2 120
Decrement R1 124
128 Branch>0 LOOP
132 Move R0, SUM

….
…. SUM 200
N …. 204
NUM1 208
NUM2 212
100

NUMn 604
….
….
….

Fig 2.17 Memory arrangement for the program in fig b.

ASSEMBLY AND EXECUTION OF PRGRAMS:-

A source program written in an assembly language must be assembled into a machine
language object program before it can be executed. This is done by the assembler program,
which replaces all symbols denoting operations and addressing modes with the binary codes
used in machine instructions, and replaces all names and labels with their actual values.

The assembler assigns addresses to instructions and data blocks, starting at the
address given in the ORIGIN assembler directives. It also inserts constants that may be given
in DATAWORD commands and reserves memory space as requested by RESERVE
commands.

As the assembler scans through a source programs, it keeps track of all names and the
numerical values that correspond to them in a symbol table. Thus, when a name appears a
second time, it is replaced with its value from the table. A problem arises when a name
appears as an operand before it is given a value. For example, this happens if a forward
branch is required. A simple solution to this problem is to have the assembler scan through
the source program twice. During the first pass, it creates a complete symbol table. At the end
of this pass, all names will have been assigned numerical values. The assembler then goes
through the source program a second time and substitutes values for all names from the
symbol table. Such an assembler is called a two-pass assembler.

The assembler stores the object program on a magnetic disk. The object program
must be loaded into the memory of the computer before it is executed. For this to happen,
another utility program called a loader must already be in the memory.

When the object program begins executing, it proceeds to completion unless there are
logical errors in the program. The user must be able to find errors easily. The assembler can
detect and report syntax errors. To help the user find other programming errors, the system
software usually includes a debugger program. This program enables the user to stop
execution of the object program at some points of interest and to examine the contents of
various processor registers and memory locations.

NUMBER NOTATION:-
When dealing with numerical values, it is often convenient to use the familiar
decimal notation. Of course, these values are stored in the computer as binary numbers. In
some situations, it is more convenient to specify the binary patterns directly. Most assemblers
allow numerical values to be specified in different ways, using conventions that are defined
by the assembly language syntax. Consider, for example, the number 93, which is represented
by the 8-bit binary number 01011101. If this value is to be used an immediate operand, it can
be given as a decimal number, as in the instructions.

ADD #93, R1

Or as a binary number identified by a prefix symbol such as a percent sign, as in

ADD #%01011101, R1

Binary numbers can be written more compactly as hexadecimal, or hex, numbers, in

which four bits are represented by a single hex digit. In hexadecimal representation, the
decimal value 93 becomes 5D. In assembly language, a hex representation is often identified
by a dollar sign prefix. Thus, we would write

ADD #$5D, R1