Simplified Explanation:

Static memories use positive feedback to form a bistable circuit, which means the circuit has
two stable states — representing logic 0 and 1.

This is made by connecting two inverters in a loop (the output of the second inverter goes back to
the input of the first).
When you plot the voltage transfer characteristics (VTC) of both inverters together, you find three
possible operating points — labeled A, B, and C.

 A and B are stable points (represent logic 0 and 1).

 C is a metastable point (unstable).

Why C is unstable (metastable):

At point C, if there is even a small disturbance (like noise), it gets amplified because the loop gain
(G) > 1.
This causes the operating point to move away from C and settle into either A or B.
So, C is metastable, meaning it can’t stay there for long.

Why A and B are stable:

At points A and B, the loop gain G < 1.

Even if a small change happens, it gets reduced and disappears, keeping the circuit steady.
Thus, the circuit can store one bit of data — either logic 0 (A) or logic 1 (B).

Changing the stored state:

To switch from A → B or B → A, the circuit must be made temporarily unstable.

This is done by increasing the loop gain G > 1 using a trigger pulse applied at Vi1 or Vi2.

For example,
if the circuit is at A (Vi1 = 0, Vi2 = 1),
forcing Vi1 = 1 momentarily turns both inverters ON, increasing the gain and shifting the circuit to B.
Once the pulse is gone, the circuit stays at the new stable point.

The pulse width only needs to be slightly longer than twice the inverter’s propagation delay (the
total delay around the loop).

In summary:

 Two cross-coupled inverters form a bistable circuit.

 A and B are stable states → store 1 or 0.

 C is metastable → unstable due to gain > 1.

  Positive feedback helps store data.

 A trigger pulse switches the stored state by temporarily increasing gain.

S-R FLIP FLOP

Simplified Explanation:
The cross-coupled inverter pair (from the previous section) can store one
binary variable (0 or 1) in a stable way.
However, to control or change the stored state, we need extra circuitry.
The simplest circuit that does this is the SR (Set–Reset) flip-flop.

Structure:
The SR flip-flop is similar to the cross-coupled inverter circuit,
but here the inverters are replaced with NOR gates.
Each NOR gate has:
 One input connected to the trigger inputs (S for Set and R for Reset).
 The other input connected to the output of the opposite NOR gate,
forming a feedback loop.
This cross-connection creates two outputs:
 Q
 Q̅ (Q bar)
These outputs are complementary (opposite logic values), except when both S
and R = 1.

Operation:
1. When S = 0 and R = 0:
o The flip-flop is in a quiescent (resting) state.
o Both outputs retain their previous values.
o In this condition, each NOR gate behaves like an inverter, just like
in the earlier bistable circuit.
 2. When S = 1 and R = 0:
o The Set input activates.
o The output Q becomes 1 and Q̅ becomes 0.
3. When S = 0 and R = 1:
o The Reset input activates.
o The output Q becomes 0 and Q̅ becomes 1.
4. When S = 1 and R = 1:
o Both outputs Q and Q̅ become 0.
o This violates the rule that Q and Q̅ must be complementary, so this
state is called the forbidden or invalid state.
o Also, when the inputs return to 0 afterward, the final output is
unpredictable — it depends on which input (S or R) returns to 0
first.

Summary:
 The SR flip-flop uses cross-coupled NOR gates to store one bit (0 or 1).
 The S input sets the output (Q = 1).
 The R input resets the output (Q = 0).
 When S = R = 0, it holds the previous value.
 When S = R = 1, it’s a forbidden state (outputs not complementary).
 The characteristic table shows all possible input combinations and their
corresponding output states.
 The symbol of the SR flip-flop is usually a rectangle with S, R inputs and
Q, Q̅ outputs.

1. Positive and Negative Latches using Multiplexers:

Figure 4 shows static positive and negative latches made using multiplexers.
For a Negative Latch:
 When the clock signal (CLK) is low, the input 0 of the multiplexer is
selected.
→ The D input is directly passed to the output.
 When the clock signal is high, the input 1 (connected to the output of
the latch) is selected.
→ This creates feedback, which holds the output stable while the clock
is high.
So, in a negative latch, data passes through when the clock is LOW, and the
output is held when the clock is HIGH.
For a Positive Latch:
 When the clock is high, the D input is selected and transferred to the
output.
 When the clock is low, feedback is enabled to hold the output stable.
So, in a positive latch, data passes through when the clock is HIGH, and the
output is held when the clock is LOW.

2. Transistor-Level Positive Latch (Figure 5):

A transistor-level implementation of a positive latch using multiplexers works
like this:
 When CLK = high:
o The bottom transmission gate is ON.
o The latch becomes transparent, meaning the D input is copied to
the Q output.
o The feedback path is open because the top transmission gate is
OFF.
 When CLK = low:
o The bottom gate is OFF, and the top gate is ON.
o The feedback path closes, holding the output Q constant.
Unlike the SR flip-flop, this latch does not need to override feedback to write
data,
so the transistor sizing is not critical for proper operation.
However, note that the clock (CLK) signal controls four transistors here —
this increases the clock load, since the clock has an activity factor of 1 (it
switches every cycle).
Hence, this latch is not very efficient in terms of clock loading.

3. NMOS-Only Pass Transistor Latch (Figure 6):

To make the latch more efficient, it’s possible to reduce the clock load by using
NMOS-only pass transistors instead of full transmission gates.
 In this design, the clock controls only two NMOS transistors,
so the clock load is reduced from 4 to 2 transistors.
Operation:
 When CLK = high, the latch samples the D input (input passes through).
 When CLK = low, the feedback loop is enabled, and the latch holds the
output.
Disadvantages:
While this design is simpler and reduces clock loading,
it has some drawbacks because NMOS-only transistors cannot pass a full high
voltage.
 The output high level is only VDD – VTn (a degraded voltage).
 This reduces the noise margin and slows down switching performance,
especially when:
o VDD is low
o VTn (threshold voltage) is high.
Another issue is static power dissipation:
 Since the maximum voltage reaching the first inverter is VDD – VTn,
the PMOS transistor inside that inverter never completely turns off.
 As a result, a small continuous current flows → static power loss occurs.
In summary:
 Multiplexer-based latches use transmission gates for data storage and
control.
 Positive latch: transparent when CLK = high.
 Negative latch: transparent when CLK = low.
 Transmission gate design: reliable but has higher clock load (4
transistors).
 NMOS-only design: reduces clock load (2 transistors) but causes
o degraded high voltage,
o lower noise margin,
o and static power dissipation.

What is a Master–Slave Flip-Flop?

A Master–Slave flip-flop is made by connecting two latches —
👉 one Master latch and
👉 one Slave latch — in series.
It is designed to eliminate timing problems like unwanted changes (called race-
around condition) that happen in level-sensitive latches.

⚙️Structure:
 The Master latch is active (transparent) when the clock = HIGH.
 The Slave latch is active when the clock = LOW.
 The output of the Master goes into the input of the Slave.
When combined, the output (Q) changes only once per clock cycle, making it
edge-triggered.

🕓 Working Principle:
Let’s say it’s a positive-edge-triggered master–slave flip-flop.
 1. When Clock = LOW
o The Master latch is OFF (holds data).
o The Slave latch is ON, passing the previous output to Q.
2. When Clock = HIGH
o The Master latch is ON (captures input D).
o The Slave latch is OFF (holds its previous output).
o So, changes in D during this time do not immediately affect Q.
3. When Clock goes from HIGH → LOW (falling edge)
o The data stored in Master is passed to the Slave, updating Q.
o Therefore, the flip-flop acts on the edge of the clock signal —
specifically, the falling edge for this type.
📌 Similarly, if the latches are reversed, you get a positive-edge-triggered flip-
flop (updates on rising edge).

🧩 Why it’s called “Edge-Triggered”

Because the output (Q) changes only at the transition (edge) of the clock —
either rising edge (↑) or falling edge (↓) —
and not while the clock level remains high or low.
This prevents unwanted multiple changes within one clock pulse.

⚡ Timing Properties (Important Terms)

Property Meaning Effect
The minimum time before the If D changes too close to the
Setup Time (tₛ) clock edge that input D must clock edge → incorrect data
be stable. stored.
The minimum time after the
If D changes too soon after
Hold Time (tₕ) clock edge that D must remain
the edge → data corruption.
stable.
Propagation Time between clock edge and Determines how fast the flip-
Property Meaning Effect
Delay (tₚd) change at output Q. flop can operate.
Minimum HIGH or LOW
Clock Pulse Too narrow → Master or Slave
duration of the clock needed
Width may not latch properly.
for correct operation.
Setup + Hold When D changes too close to Causes metastability (output
Violation clock edge. uncertain for a short time).

🧭 Summary of Behavior
Clock Master Slave Output (Q)
LOW Holds Transparent Previous output visible
HIGH Transparent Holds No output change
Edge (Transition) Master → Slave Updates New value appears at Q

✅ Advantages:
 Avoids race-around problem (common in SR latches).
 Output changes only once per clock cycle.
 Reliable edge-triggered operation.
❌ Disadvantages:
 Two latches = more delay and power usage.
 Propagation delay is roughly double that of a single latch.

Perfect 👍 — let’s go through Dynamic Transmission-Gate Edge-Triggered

Registers in a neat, step-by-step, and easy-to-understand way, while keeping
all the important technical terms and concept clarity intact.
I’ll also describe what the diagram looks like clearly, so you can easily sketch or
visualize it.
A Dynamic Transmission-Gate Edge-Triggered Register is a high-speed
storage element used in digital systems.
It stores one bit of data and updates its output only on the clock edge (rising or
falling).
It is called:
 Dynamic → because it uses temporary charge storage (in capacitances),
 Transmission-Gate based → because it uses transmission gates (TG) to
control data flow,
 Edge-Triggered → because it changes output only on the edge of the
clock, not during the level.

⚙️2. Structure Overview

It is made of two latches connected in series:
 A Master latch (first stage)
 A Slave latch (second stage)
Each latch uses Transmission Gates (TG) as controlled switches and inverters to
hold data.

Diagram Description (you can draw this easily):

+---------------------+
D ──TG1────>│ INV1 INV2 │───TG2──>│ INV3 INV4 │──> Q
↑ (Master Latch) ↑ (Slave Latch)
│ CLK │ CLK'
Explanation:
 TG1 (Transmission Gate 1) passes input D into Master latch when CLK =
HIGH.
 TG2 passes data from Master latch → Slave latch when CLK' (inverted
clock) is HIGH.
  Each latch has two inverters connected back-to-back to store a logic
level (like static memory).
 Output Q comes from the Slave latch.
So, when CLK toggles, data first enters Master, then transfers to Slave at the
next edge.

🔄 3. Operation (Step-by-Step)
Let’s assume a positive edge-triggered register.
(a) When CLK = LOW
 TG1 = OFF, TG2 = ON (since TG2 is controlled by CLK’).
 The Slave latch is transparent → output Q follows Master output.
 The Master latch holds its previous value.
(b) When CLK = HIGH
 TG1 = ON, TG2 = OFF.
 The Master latch becomes transparent and captures the input D.
 The Slave latch now holds its previous value (since TG2 is OFF).
 So, changes at D don’t reach Q immediately.
(c) On the Falling Edge (CLK ↓)
 TG1 turns OFF and TG2 turns ON.
 The data stored in Master latch is transferred to Slave latch,
and hence the output Q updates.
✅ Hence, the register is edge-triggered — it updates only on the falling edge of
CLK (for this configuration).
For a positive-edge-triggered version, the control polarities are swapped.

⚡ 4. Dynamic Nature
Why it’s called dynamic:
  When a transmission gate turns OFF, the node inside the latch holds its
voltage using the parasitic capacitance of transistors.
 This stored charge represents the logic ‘1’ or ‘0’ temporarily.
 However, this charge can leak away over time, so the latch needs
periodic refreshing (or clock toggling) to retain data.
✅ Advantage: fewer transistors and faster operation.
❌ Disadvantage: charge leakage → can’t hold data for long without clock
activity.

🧩 5. Advantages
Feature Description
High Speed No long feedback loops; TGs switch quickly.
Low Power Clock controls few transistors → less load.
Compact Fewer devices than static edge-triggered flip-flops.
Edge-Triggered Output changes only on clock edge → no glitches.

⚠️6. Disadvantages
Problem Explanation
Dynamic Storage Data is stored as charge; leaks over time.
Clock Overlap If both TGs (master & slave) are ON together, data
Issue corruption occurs.
Noise Sensitivity Small leakage or noise may change stored voltage.
Needs Clock
Works properly only when clock keeps toggling.
Activity

🕒 7. Timing Properties
Parameter Meaning
Setup Time (tₛ) Input D must be stable before clock edge.
Parameter Meaning
Hold Time (tₕ) Input D must remain stable after clock edge.
Propagation Delay (tₚ) Time taken for output Q to update after clock edge.
Clock Skew Sensitivity If CLK and CLK’ overlap incorrectly, it can cause errors.

🧾 8. Summary
Characteristic Description
Type Dynamic Edge-Triggered Register
Main Components 2 Transmission Gates + 4 Inverters
Trigger Type Edge-Triggered (usually falling edge)
Storage Type Dynamic (charge-based)
Advantage Fast, low power, compact
Disadvantage Needs clock refresh; sensitive to leakage and overlap

🧩 In Simple Words:
A Dynamic Transmission-Gate Edge-Triggered Register is a fast, small, edge-
sensitive memory cell.
It uses transmission gates to control data flow and temporary charge storage
to remember one bit.
The output changes only on the clock edge, ensuring stable operation in
synchronous systems.

Would you like me to draw and show the diagram (so you can visualize the
master–slave and TG switching clearly)?
It’ll make the concept instantly clear.

1️⃣ Latches in Digital Electronics

Definition:
A latch is a bistable device that stores 1 bit of data. It has two stable states,
and can maintain its output indefinitely until an input changes it.
Level-Sensitive:
 Latches respond to input levels (not edges).
 Common types: SR latch, D latch, NORA latch, CMOS latch.
Purpose:
 Memory elements in registers, flip-flops, and sequential circuits.

2️⃣ NORA Latch (NMOS Only)

🔹 Definition
 NORA (NOR-Rich Architecture) latch uses NMOS transistors and resistive
loads.
 It implements a SR latch with cross-coupled NOR gates.
 Optimized for low-power and high-speed NMOS circuits.

🔹 Circuit Diagram
Cross-Coupled NMOS NOR Gates:
+Vdd
|
R_pull-up
|
|------ Q
| |
| NMOS
S ---> | |
| |
 +-------+
|
NMOS
R --->|
|
GND
 Two NMOS transistors form a cross-coupled latch.
 Pull-up resistors are used to maintain logic high when NMOS is off.

🔹 Working Principle
Inputs Operation
S=0, R=0 Hold previous state (memory)
S=1, R=0 Set Q=1, Q̅=0
S=0, R=1 Reset Q=0, Q̅=1
S=1, R=1 Invalid (both outputs 0)
Explanation:
1. Set: S turns on NMOS connected to Q̅, pulling Q low → cross-coupled
gates force Q high.
2. Reset: R turns on NMOS connected to Q, pulling Q̅ low → Q becomes 0.
3. Hold: Both S and R low → no NMOS conducts → outputs remain the
same.

🔹 Advantages
✅ Fast switching (NMOS only)
✅ Small area
✅ Good for high-density NMOS logic circuits
🔹 Disadvantages
❌ Requires careful voltage scaling
❌ Cannot drive large fan-out
❌ Invalid S=R=1 state
🔹 Applications
 NMOS memory cells
 Digital registers in NMOS technology
 High-speed sequential circuits

3️⃣ CMOS Latch

🔹 Definition
 A CMOS latch uses complementary NMOS and PMOS transistors.
 Low static power consumption and high noise immunity.
 Can implement SR latch, D latch, or transmission-gate latch.

🔹 Circuit Diagram (CMOS SR Latch)

Vdd
|
PMOS
S ----|>|----+
| |
| +----> Q
| |
PMOS PMOS
R ----|>|----+
|
NMOS
 |
+----> Q̅
|
GND
Explanation:
 PMOS transistors pull output high when input is 0.
 NMOS transistors pull output low when input is 1.
 Cross-coupling maintains bistable state.

🔹 Working Principle
Inputs Q Q̅ Operation
S=0, R=0 Q(t) Q̅(t) Hold previous state
S=1, R=0 1 0 Set
S=0, R=1 0 1 Reset
S=1, R=1 Invalid Invalid Forbidden
Step-by-step:
1. Set: S=1, R=0 → NMOS at Q̅ conducts → Q̅ pulled low → cross-coupled
PMOS at Q drives Q high.
2. Reset: S=0, R=1 → NMOS at Q conducts → Q pulled low → cross-coupled
PMOS at Q̅ drives Q̅ high.
3. Hold: S=0, R=0 → Both NMOS off → outputs maintain previous state.
4. Forbidden: S=R=1 → Both NMOS on → outputs undefined.

🔹 Advantages
✅ Very low static power
✅ High noise immunity
✅ Can drive large fan-out
✅ Compatible with CMOS ICs
🔹 Disadvantages
❌ Larger area than NMOS latch
❌ Slightly more complex circuitry
🔹 Applications
 Memory elements in CMOS microprocessors
 Flip-flops and registers
 Sequential CMOS circuits

4️⃣ Comparison Table: NORA vs CMOS Latch

Feature NORA Latch CMOS Latch
Transistors NMOS only NMOS + PMOS
Power Low (dynamic) Very low (static)
Noise Immunity Moderate High
Area Small Slightly larger
Speed Fast Moderate
Fan-out Limited Large
Applications NMOS memory CMOS sequential circuits

5️⃣ Additional Notes

 Both latches are bistable, with hold, set, and reset states.
 CMOS latches are preferred in modern ICs due to power efficiency and
robustness.
 NORA is mainly historical or used in high-speed NMOS circuits.
 S=R=1 is invalid in basic SR latch.

6️⃣ Diagrams Summary (Visual for Exams)

NORA Latch
 S ----|NMOS|----+
|
+----> Q
|
R ----|NMOS|----+
|
Q̅
 Cross-coupled NMOS NOR gates with resistive loads.

CMOS SR Latch
Vdd
|
PMOS
S --->|>|---+
|
+----> Q
|
PMOS
R --->|>|---+
|
NMOS
|
+----> Q̅
|
GND
 Complementary PMOS/NMOS configuration for low static power.
This content is detailed enough for a full 16-mark answer, covering:
 Definition
 Circuit diagram
 Working
 Truth table
 Advantages/Disadvantages