Basic Structure of Computer: Structure of Desktop Computers

Basic Structure of Computer

the basic structure of a computer involves looking at the primary components that make up a
computer system and how they interact with each other. Here's a breakdown of the key
components and their roles:

1. Central Processing Unit (CPU)

 Role: The CPU, often referred to as the brain of the computer, performs most of the processing
inside a computer.
 Components:
o Control Unit (CU): Directs the operation of the processor.
o Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
o Registers: Small, fast storage locations that hold data and instructions.
2. Memory
 Primary Memory (RAM): Volatile memory used by the CPU to store data and instructions that
are currently in use.
 Secondary Memory (Storage): Non-volatile memory used for long-term storage of data.
Examples include Hard Disk Drives (HDDs) and Solid State Drives (SSDs).
3. Motherboard
 Role: The main circuit board that houses the CPU, memory, and other essential components. It
allows communication between all parts of the computer.
 Components:
o Chipset: Manages data flow between the CPU, memory, and peripherals.
o BIOS/UEFI: Firmware that initializes hardware during the booting process.
4. Input and Output Devices (I/O)
 Input Devices: Allow users to input data into the computer (e.g., keyboard, mouse, scanner).
 Output Devices: Allow users to receive data from the computer (e.g., monitor, printer,
speakers).
5. Storage Devices
 Hard Disk Drives (HDD): Traditional magnetic storage with moving parts.
 Solid State Drives (SSD): Faster, flash-based storage with no moving parts.
 Optical Drives: Use lasers to read/write data on CDs, DVDs, or Blu-ray discs.
6. Power Supply Unit (PSU)
 Role: Converts electrical power from an outlet into usable power for the internal components of
the computer.
7. Graphics Processing Unit (GPU)
 Role: Renders images, video, and animations for display. Essential for gaming, video editing, and
graphic design.
 Types: Integrated (built into the CPU) and dedicated (separate card installed on the
motherboard).
8. Network Interface Card (NIC)
 Role: Connects the computer to a network. Can be wired (Ethernet) or wireless (Wi-Fi).
9. Cooling System
 Role: Maintains optimal temperature for the CPU and other components to prevent
overheating.
 Components: Fans, heat sinks, liquid cooling systems.
10. Expansion Slots and Cards
 Role: Allow additional components to be added to the computer (e.g., additional GPUs, sound
cards, network cards).
 Types: PCI, PCIe, AGP.
Interactions Between Components
 Bus System: A set of physical connections like wires and fiber optics that carry data between
components.
o Data Bus: Transfers actual data.
o Address Bus: Transfers information about where data should go.
o Control Bus: Transfers commands and control signals.
Summary Diagram

+---------------------+
| Input Devices |
+---------------------+
|
v
+---------------------+
| CPU |
| - ALU |
| - CU |
| - Registers |
+---------------------+
|
v
+---------------------+ +---------------------+
| Primary Memory (RAM)| <------>| Storage |
+---------------------+ | - HDD |
| | - SSD |
v +---------------------+
+---------------------+
| Motherboard |
| - Chipset |
| - BIOS/UEFI |
+---------------------+
|
v
+---------------------+ +---------------------+
| Output Devices |<------>| Network Interface |
+---------------------+ | - Wired (Ethernet) |
| | - Wireless (Wi-Fi) |
v +---------------------+
+---------------------+
| Power Supply Unit |
+---------------------+
|
v
+---------------------+
| Cooling System |
+---------------------+
|
v
+---------------------+
| Expansion Slots |
| and Cards |
+---------------------+
This basic structure outlines the key components and their interactions within a computer system.
Each part plays a crucial role in ensuring the computer operates efficiently and effectively.

CPU:
The Central Processing Unit (CPU), often referred to as the brain of the computer, is the primary
component that executes instructions and processes data. Here's an in-depth look at the CPU's
structure, components, and functions:
Structure and Components of the CPU
1. Control Unit (CU)
o Function: Directs the operation of the processor. It tells the computer's memory,
arithmetic/logic unit, and input and output devices how to respond to the instructions
that have been sent to the processor.
o Components:
 Instruction Register (IR): Holds the current instruction being executed.
 Program Counter (PC): Keeps track of the address of the next instruction to be
executed.
2. Arithmetic Logic Unit (ALU)
 o Function: Performs all arithmetic and logical operations. This includes basic operations
like addition, subtraction, multiplication, division, and logical operations like AND, OR,
NOT.
o Components:
 Arithmetic Unit: Handles arithmetic operations.
 Logic Unit: Handles logical operations.
3. Registers
o Function: Small, fast storage locations within the CPU used to hold temporary data and
instructions.
o Types:
 General Purpose Registers: Used for various functions by the CPU.
 Special Purpose Registers: Specific registers with dedicated tasks, such as the
Program Counter (PC), Stack Pointer (SP), and Status Register (SR).
4. Cache Memory
oFunction: Provides high-speed data storage that the CPU can access more quickly than
the main memory (RAM). There are typically multiple levels of cache (L1, L2, and
sometimes L3).
CPU Operation
The CPU operates by following a cycle called the Fetch-Decode-Execute Cycle. Here’s a
breakdown of each stage:
1. Fetch
o The CPU fetches the next instruction from the main memory (RAM) into the instruction
register (IR).
2. Decode
o The control unit decodes the fetched instruction to determine what action is required.
This involves interpreting the opcode (operation code) and any necessary operands.
3. Execute
o The decoded instruction is then executed by the appropriate part of the CPU. This might
involve performing an arithmetic operation in the ALU, moving data between registers,
or interacting with memory.

Memory or Storage Unit

The memory or storage unit in a computer system includes primary memory (RAM and ROM) and
secondary storage (HDDs, SSDs). Primary memory is volatile and fast, used for active processing
and immediate access by the CPU. RAM stores data and instructions currently in use, while ROM
holds essential system firmware. Secondary storage is non-volatile, providing long-term data
retention with larger capacity but slower access. Examples include hard drives, solid-state drives,
and optical discs. Efficient memory management by the operating system ensures optimal
allocation and protection of these resources, enabling smooth and effective computer operation.
Control Unit
The Control Unit (CU) is a crucial component of the CPU responsible for directing the operation of the
processor. It manages and coordinates all activities within the CPU by fetching instructions from
memory, decoding them to determine required actions, and executing them. The CU controls the flow
of data between the CPU, memory, and peripherals, using control signals to manage the execution of
instructions in the correct sequence. It ensures that the ALU performs the necessary operations and that
data is stored and retrieved correctly, facilitating efficient and accurate processing within the computer
system.
ALU (Arithmetic Logic Unit)
ALU (Arithmetic Logic Unit) is responsible for performing arithmetic and logical
functions or operations. It consists of two subsections, which are:
 Arithmetic Section
 Logic Section
Now, let us know about these subsections:
Arithmetic Section: By arithmetic operations, we mean operations like
addition, subtraction, multiplication, and division, and all these operation and
functions are performed by ALU. Also, all the complex operations are done by
making repetitive use of the mentioned operations by ALU.
Logic Section: By Logical operations, we mean operations or functions like
selecting, comparing, matching, and merging the data, and all these are
performed by ALU.

General Register Organization-

In computer architecture, the General Register Organization comprises various registers within the CPU
used for temporary data storage and processing. It typically includes several types of registers: data
registers, address registers, and status registers. Data registers hold operands and intermediate results
during arithmetic and logical operations, while address registers store memory addresses for data
access. Status registers contain flags that indicate the outcome of arithmetic operations or control the
CPU's behavior. The efficient organization and utilization of these registers optimize the CPU's
performance by reducing memory accesses and facilitating fast data manipulation, enabling efficient
execution of instructions.
Memory Register
 Memory Address Registers (MAR):
It holds the address of the location to be accessed from memory. MAR
and MDR (Memory Data Register) together facilitate the communication
of the CPU and the main memory.

 Memory Data Registers (MDR):

It contains data to be written into or to be read out from the addressed
location.

Instruction Register,
Instruction Register (IR):
The IR holds the instruction which is just about to be executed. The
instruction from PC is fetched and stored in IR. As soon as the instruction in
placed in IR, the CPU starts executing the instruction and the PC points to
the next instruction to be executed.
Control Word,
Control word is defined as a word whose individual bits represent the various control
signal. The control words related to an instruction that is stored in microprogram
memory. It is a set of micro-instructions in a micro-routine.
 In control words, microoperations are specified, they are known as
microinstructions.
 Each microinstruction specifies one or more microoperations that are performed.
 The Control Word consists of bits, and each bit corresponds to a function or
commands such as Pause, Stop, Enable, Start, Stop, Move, Jog, etc.

Stack Organization,
Stack Organization
The stack can be used for various purposes like procedure call and return, evaluation of arithmetic
expressions discussed later in further sections, storing local variables, etc. Thus, its implementation
depends on the purposes for which it is required.
If the programmer intends to use the stack for various operations, then the instruction set will
include stack operations, such as Push and Pop. Whereas, if the stack is to be used only by the
processor, for purposes such as procedure call and return, then it is not required to include explicit
stack-oriented instructions in the instruction set.
Figure illustrates that irrespective of the use of the stack, some set of memory locations are
reserved to store the stack elements. These locations can either be reserved in terms of processor’s
registers or the physical memory locations as discussed later.

Instruction Format,
1. Memory Reference – Memory reference instructions enable CPU to read/write data in
memory. Includes load (LDR), store (STR), and control transfer. Crucial for program execution, data
manipulation, and communication with peripherals.
These instructions refer to memory address as an operand. The other
operand is always accumulator. Specifies 12-bit address, 3-bit opcode
(other than 111) and 1-bit addressing mode for direct and indirect

addressing.
Example – IR register contains = 0001XXXXXXXXXXXX, i.e. ADD after
fetching and decoding of instruction we find out that it is a memory
reference instruction for ADD operation.
2. Register Reference – .

[Link]/Output – These instructions are for communication between

computer and outside environment. The IR(14 – 12) is 111 (differentiates
it from memory reference) and IR(15) is 1 (differentiates it from register
 reference instructions)..

ALU
The Arithmetic Logic Unit (ALU) performs arithmetic and logical operations on data received
from registers. It's a key component of the CPU, essential for executing computational tasks in
computer systems.

I/O System,
The I/O subsystem of a computer provides an efficient mode
of communication between the central system and the
outside environment. It handles all the input-output
operations of the computer system.
There are three types of peripherals:
1. Input peripherals : Allows user input, from the outside
world to the computer. Example: Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from
the computer to the outside world. Example: Printer,
Monitor etc
3. Input-Output peripherals: Allows both input(from
outised world to computer) as well as, output(from
computer to the outside world). Example: Touch screen
etc.
Bus,
A bus is a communication system that transfers data between components within a computer or
between different computers. It consists of parallel wires or traces that carry binary information,
address signals, control signals, and power between components such as CPU, memory, and peripherals.
Buses are categorized based on their functions, including data bus, address bus, and control bus.
CPU and Memory Program Counter,
There is a register in a PC (program counter) processor that
contains the address of the next instruction to be executed from
memory.
It is a 16-bit register and is also called instruction counter,
instruction pointer, and instruction address register (IAR). PC
(program counter) is a digital counter that is needed to execute
tasks quickly and track the current execution point.

Bus Structure,
The system bus is a pathway composed of cables and connectors used to carry data between a
computer microprocessor and the main memory. The bus provides a communication path for the data
and control signals moving between the major components of the computer system. The system bus
works by combining the functions of the three main buses: namely, the data, address and control buses.
Each of the three buses has its separate characteristics and responsibilities

Register Transfer Language-Bus and Memory Transfer,

Register Transfer Language (RTL) describes microoperations at a hardware level, specifying data
transfers between registers and arithmetic/logic operations. It's fundamental in digital design and
computer architecture for designing and understanding CPU functionality.
// Example: Addition operation in RTL RegisterA <= RegisterA + RegisterB
P: R2 ← R1

Basic symbols of RTL :

Symbol Description Example

Letters and MAR, R1,

Denotes a Register
Numbers R2

R1(8-bit)
() Denotes a part of register
R1(0-7)

<- Denotes a transfer of information R2 <- R1

R1 <- R2
, Specify two micro-operations of Register Transfer
R2 <- R1

P : R2 <- R1
: Denotes conditional operations
if P=1

Naming Operator Denotes another name for an already existing

Ra := R1
(:=) register/alias

addressing modes.
Addressing modes define how CPU instructions specify the memory addresses of operands. Common
modes include direct, indirect, register, and immediate, each determining how operands are accessed or
interpreted during instruction execution.
The term addressing modes refers to the way in which the operand of an
instruction is specified. The addressing mode specifies a rule for interpreting
or modifying the address field of the instruction before the operand is
actually executed.
Common types include:
1. Immediate: Operand value is directly encoded within the instruction.
2. Direct: Operand address is specified directly within the instruction.
3. Indirect: Instruction refers to the address of another memory location, which holds the
operand.
4. Register: Operand is located within a register specified in the instruction.
5. Register Indirect- any selected register would include the address of an operand
6. Auto Increment and decrement -The register whose number is included in the
instruction code, contains the address of the operand. Autoincrement Mode = after
operand addressing , the contents of the register is incremented. Decrement Mode =
before operand addressing, the contents of the register is decrement .
7. Indexed: the content of an index register is added to the address part of an instruction to
derive the effective address.
8. Base- In this mode effective address is obtained by adding base register value to
address field value. EA= Base register + Address field value(OPERAND)
9. Relative: In this mode effective address is obtained by adding base register value to
address field value. EA= OPERAND + PC

Control Unit Organization:

The control unit performs instruction decoding, interpreting fetched instructions to determine the
operation and operands involved. This process enables the generation of appropriate control
signals to coordinate CPU components for efficient execution of instructions.

The control unit fetches internal program instructions from the main memory to the processor
instruction register, and it generates a control signal based on the contents of this register to
supervise the execution of these instructions.
A control unit receives data from the user and translates it into control signals that are
subsequently delivered to the central processor. The processor of the computer then instructs
the associated hardware on what operations to do. Because CPU architecture differs from
manufacturer to manufacturer, the functions performed by a control unit in a computer are
dependent on the CPU type. The following are some examples of devices requiring a control
unit:
+-------------------------+
| Instruction |
| Fetch |
+------------+------------+
|
v
+------------+------------+
| Decode |
| Unit |
+------------+------------+
|
v
+------------+------------+
| Control |
| Signals |
+------------+------------+
|
v
+------------+------------+
| Execution |
| Unit |
+------------+------------+

Basic Concept of Instruction, Instruction Types,

An instruction code is a group of bits that instruct the computer to
perform a specific operation. It is usually divided into parts, each
having its own particular interpretation. The most basic part of an
instruction code is its operation part. The operation code of an
instruction is a group of bits that define such operations as add,
subtract, multiply, shift, and complement. The number of bits
required for the operation code of an instruction depends on
the total number of operations available in the computer. The
operation code must consist of at least n bits for a given 2" (or
less) distinct operations. As an illustration, consider a computer
with 64 distinct operations, one of them being an ADD operation.
Types of Instructions
Zero Address Instructions
These instructions do not specify any operands or addresses. Instead, they
operate on data stored in registers or memory locations implicitly defined by
the instruction.
One Address Instructions
These instructions specify one operand or address, which typically refers to
a memory location or register. The instruction operates on the contents of
that operand, and the result may be stored in the same or a different
location.
Two Address Instructions
These instructions specify two operands or addresses, which may be memory
locations or registers. The instruction operates on the contents of both
operands, and the result may be stored in the same or a different location.

Memory Reference Instructions

These instructions refer to memory address as an operand. The other
operand is always accumulator .Specifies 12-bit address, 3-bit opcode (other
than 111) and 1-bit addressing mode for direct and indirect addressing.

Direct Memory Reference Instructions

In Direct Memory Reference Instructions the operand part specifies the
Effective address of data

InDirect Memory Reference Instructions

In Direct Memory Reference Instructions the operand part specifies the
address of Effective address of data
In above diagram no1 specifying direct memory reference instruction, the
operand part carrying the value 457 specifies the Effective address of data or
operand
Whereas in diagram no2 specifying Indirect memory reference instruction,
the operand part carrying the value 300 specifies the address of Effective
address ,i.e at 300 we found 1350 effective address of operand and then at
1350 we found the data or operand

Register Reference – These instructions perform operations on registers

rather than memory addresses. The IR(14 – 12) is 111 (differentiates it from
memory reference) and IR(15) is 0 (differentiates it from input/output
instructions). The rest 12 bits specify register operation.
Input/Output – These instructions are for communication between computer
and outside environment. The IR(14 – 12) is 111 (differentiates it from
memory reference) and IR(15) is 1 (differentiates it from register reference
instructions). The rest 12 bits specify I/O operation.

Micro Instruction Formats,

A microinstruction format includes 20 bits in total. They are divided into four
elements as displayed in the figure.

F1, F2, F3 are the micro-operation fields. They determine micro-operations for
the computer.
CD is the condition for branching. They choose the status bit conditions.
BR is the branch field. It determines the type of branch.
AD is the address field. It includes the address field whose length is 7 bits.
Symbols with their Binary Code for Microinstruction Fields
Name: Code Symbol

F1 000 None NOP

001 AC ← AC + DR ADD

010 AC ← 0 CLRAC

011 AC ← AC + 1 INCAC

100 AC ← DR DRTAC

101 AR ← DR(0 − 10) DRTAR

110 AR ← PC PCTAR

111 AC ← AC + DR WRITE

F2 000 None NOP

 Name: Code Symbol

001 AC ← AC + DR SUB

010 AC ← AC ∨ DR OR

011 AC ← AC ∧ DR AND

100 DR ← M[AR] READ

101 DR ← AC ACTDR

110 DR ← DR + 1 INCDR

111 DR(0 − 10) ← PC PCTDR

F3 000 None NOP

001 AC ← AC ⊕ DR XOR

010 AC ← AC′ COM

011 AC ← shl AC SHL

100 AC ← shr AC SHR

101 PC ← PC + 1 INCPC

110 PC ← AR ARTPC

111 DR(0 − 10) ← PC Reserved

Condition Field
A condition field includes 2 bits. They are encoded to define four status bit
conditions. As stated in the table, the first condition is always a 1, with CD = 0.
The symbol that can indicate this condition is ‘U’. The table displays the multiple
condition fields and their summary in an easy manner.
Condition Field Symbols and Descriptions
Condition Symbol Comments

00 Always = 1 U Unconditional Branch

 Condition Symbol Comments

01 DR (15) I Indirect address bit

10 AC (15) S Sign bit of AC

11 AC = 0 Z Zero value in AC
As shown in the table, when condition 00 is connected with BR (branch) field, it
results in an unconditional branch operation.

when condition 01 is connected with BR (branch) field, it results in an

unconditional branch [Link] the execution is read from memory the
indirect bit I is accessible from bit 15 of DR.

when condition 10 is connected with BR (branch) field, it results in an

unconditional branch operation if AC sign bit is=1

when condition 11 is connected with BR (branch) field, it results in an

unconditional branch operation if AC all bits are =0 and sign flags set to 1

If all the bits in AC are 1, then it is indicated as Z (its binary variable whose
value is 1). The symbols U, I, S, and Z can indicate status bits while writing
microprograms.
Branch Field
The BR (branch) field includes 2 bits. It can be used by connecting with the AD
(address) field. The reason for connecting with the AD field is to select the address
for the next microinstruction. The table illustrates the various branch fields and
their functions
Branch Field Symbols and Descriptions

BR Symbol Comments

00 JMP CAR ←AD if condition = 1

CAR←CAR + 1 if condition = 0

01 CALL CAR ←AD , SBR ← CAR +1, if condition = 1

CAR←CAR + 1 if condition = 0

10 RET CAR ←SBR (Return from subroutine)

 11 MAP CAR(2-5) ←DR(11-14), CAR(0,1,6) ←0
As shown in the table, when BR = 00, a JMP operation is implemented
and

when BR = 01, a subroutine is called.

The only difference between the two instructions is that when the
microinstruction is saved, the return address is saved in the Subroutine
Register (SBR).

These two operations are dependent on the CD field values. When the status bit
condition of the CD field is defined as 1, the address that is next in order is
transferred to CAR. Else, it gets incremented.

If the instruction needs to return from the subroutine, its BR field is

determined as [Link] results in the transfer of the return address
from SBR to CAR.

The opcode bits of instruction can be mapped with an address for CAR if
the BR field is 11.
They are present in DR (11 - 14) after instruction is read from memory. The
last two conditions in the BR fields are not dependent on the CD and AD field
values.

Fetch and Execution cycle,

Hardwired control unit,
There are two major types of control organization: hardwired control and
microprogrammed control. In the hardwired organization, the control logic is
implemented with gates, flip-flops, decoders, and other digital circuits. It has
the advantage that it can be optimized to produce a fast mode of operation.
In the microprogrammed organization, the control information is stored in a
control memory. The control memory is programmed to initiate the required
sequence of microoperations. A hardwired control, as the name implies, requires
changes in the wiring among the various components if the design has
to be modified or changed. In the microprogrammed control, any required
changes or modifications can be done by updating the microprogram in control
memory.
+-------------------+
| Instruction |
| Fetch |
+---------+---------+
|
v
+---------+---------+
 | Decode |
| Logic |
+---------+---------+
|
v
+---------+---------+
| Control |
| Signals |
| D0 to D7 |
+---------+---------+
|
v
+---------+---------+
| Execution |
| Unit |
+---------+---------+
The block diagram of the control unit is shown in Fig. It consists of
two decoders, a sequence counter, and a number of control logic gates. An
instruction read from memory is placed in the instruction register (IR). The
position of this register in the common bus system is indicated in Fig. The
instruction register is shown again in Fig. , where it is divided into three
parts: the I bit, the operation code, and bits 0 through 1 1 . The operation
code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight
outputs of the decoder are designated by the symbols D0 through D7• The
subscripted decimal number is equivalent to the binary value of the
corresponding operation code. Bit 15 of the instruction is transferred to a
flip-flop designated by the symbol I. Bits 0 through 11 are applied to the
control logic gates
Microprogrammed Control unit
A control unit whose binary control variables are stored in memory is called
a microprogrammed control unit
Each word in control memory contains within it a microinstruction .
The microinstruction specifies one or more microoperations
for the system.
A sequence of microinstructions constitutes a microprogram
.
A computer that employs a microprogrammed control unit will have two
separate memories: a main memory and a control memory. The main
memory is available to the user for storing the programs. The contents of
main memory may alter when the data are manipulated and every time that
the program is changed. The user's program in main memory consists of
machine instructions and data. In contrast, the control memory holds a
fixed microprogram that cannot be altered by the occasional user. The
microprogram consists of microinstructions that specify various internal
control signals for execution of register microoperations. Each machine
instruction initiates a series of microinstructions in control memory. These
microinstructions generate the microoperations to fetch the instruction from
main memory; to evaluate the effective address, to execute the operation
specified by the instruction, and to return control to the fetch phase in order
to repeat the cycle for the next instruction.
control memory

microprogram sequencer
the address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit
conditions.
3. A mapping process from the bits of the instruction to an address for
control memory.
4. A facility for subroutine call and return.
 5.

Control Memory,
The control memory, also known as the control store or microstore, is a crucial component within a
microprogrammed control unit. It stores microinstructions, which are low-level instructions that control
the operation of the CPU's various components during the execution of machine instructions.

Sequencing and Execution of Micro Instruction.

Microinstructions are stored in control memory in groups, with each group
specifying a routine. Each computer instruction has its own microprogram
routine in control memory to generate the microoperations that execute the
instruction. The hardware that controls the address sequencing of the control
memory must be capable of sequencing the microinstructions within a routine and
be able to branch from one routine to another. To appreciate the address
sequencing in a microprogram control unit, let us enumerate the steps that the
control must undergo during the execution of a single computer instruction. An
initial address is loaded into the control address register when power is turned on
in the computer. This address is usually the address of the first microinstruction
that activates the instruction fetch routine. The fetch routine may be sequenced by
incrementing the control address register through the rest of its microinstructions.
At the end of the fetch routine, the instruction is in the instruction register of the
computer.
The control memory next must go through the routine that determines
the effective address of the operand. A machine instruction may have bits that
specify various addressing modes, such as indirect address and index registers. The
effective address computation routine in control memory can be reached through a
branch microinstruction, which is conditioned on the status of the mode bits of the
instruction. When the effective address computation routine is completed, the
address of the operand is available in the memory address register. The next step is
to generate the microoperations that execute the instruction fetched from memory.
The microoperation steps to be generated in processor registers depend on the
operation code part of the instruction. Each instruction has its own microprogram
routine stored in a given location of control memory. The transformation from the
instruction code bits to an address in control memory where the routine is located
is referred to as a mapping process. A mapping procedure is a rule that transforms
the instruction
code into a control memory address. Once the required routine is reached, the
microinstructions that execute the instruction may be sequenced by incrementing
the control address register, but sometimes the sequence of microopera lions will
depend on values of certain status bits in processor registers . Microprograms that
employ subroutines will require an external register for storing the return address.
Return addresses cannot be stored in ROM because the unit has no writing
capability

Computer Arithmetic:
Arithmetic instructions in digital computer$ manipulate data to produce re
sults necessary for the solution of computational problems. These
instructions perform arithmetic calculations and are responsible for the bulk
of activity involved in processing data in a computer. The four basic
arithmetic operations are addition, subtraction, multipllcatio"' and division.
From these four bulk operations, it is possible to formulate other arithmetic
functions and solve scientific problems by means of numerical analysis
methods.
Addition and Subtraction,
Addition (subtraction) algorithm: when the signs of A and B are identical
(different), add the two magnitudes and attach the sign of A to the result.
When the signs of A and B are different (identical), compare the
magnitudes and subtract the smaller number from the larger. Choose the
sign of the result to be the same as A if A > B or the complement of the
sign of A if A < B. If the two magnitudes are equal, subtract B from A and
make the sign of the result positive.
The two algorithms are similar except for the sign comparison. The
procedure to be followed for identical signs in the addition algorithm is the
same as for different signs in the subtraction algorithm, and vice versa.
Addition and Subtraction of Signed·Magnitude Numbers
Add Subtract Magnitudes
Operation Magnitudes When A > B When A < B When A = B
(+A ) + (+ B) + (A + B)
(+A ) + ( - B) + (A - B) - (B - A) + (A - B)
( -A ) + (+ B) - (A - B) + (B - A) + (A - B)
( -A ) + ( - B) - (A + B)
( +A ) - (+ B) + (A - B) - (B - A) + (A - B)
( +A ) - ( - B) + (A + B)
( -A ) - (+ B) - (A + B)
( -A ) - ( - B) - (A - B) + (B - A) + (A -
B)

Tools Compliment Representation,

One’s Complement:
In simple words, if we want to understand the One’s complement, so one’s
complement is toggling or exchanging all the 0’s into 1 and all the 1’s into 0 of
any number. Suppose there is a binary number 11001001, then its one’s
complement will be 00110110.
In actuality, the one’s complement means the addition of a negative integer to
the number, and this eliminates the requirement of a separate subtraction
processor.
Examples:
1. Evaluate the 1’s complement of the 11010011.
Solution: Simply invert each bit of the number, and hence the 1’s complement
for the above binary number is – 00101100
 Two’s Complement
Binary Number System is one the type of most popular Number Representation
techniques that used in digital systems. In the Binary System, there are only two
symbols or possible digit values, i.e., 0 (off) and 1 (on). Represented by any
device that only 2 operating states or possible conditions.
Generally, there are two types of complement of Binary number: 1's
complement and 2’s complement. To get 1’s complement of a binary number,
simply invert the given number. For example, 1’s complement of binary number
110010 is 001101. To get 2’s complement of binary number is 1’s complement
of given number plus 1 to the least significant bit (LSB). For example 2’s
complement of binary number 10010 is (01101) + 1 = 01110

Signed Addition and Subtraction,

Multiplication
Flowchart for the Hardware Multiply Algorithm
Here is a detailed flowchart for the hardware multiply algorithm as described:
1. Start: Begin the process.
2. Initialize:
o Load the multiplicand into register B.
o Load the multiplier into register Q.
o Set the sign of the result based on the signs of B and Q.
o Clear registers A and E.
o Set sequence counter SC to the number of bits of the multiplier.
3. Check Multiplier Qn:
o If Qn of Q is 1, add the multiplicand B to A.
o If the LSB of Q is 0, do nothing.
4. Shift Right:
 o Shift the combined registers EAQ right by 1 bit.
5. Decrement SC:
o Decrement the sequence counter SC by 1.
o Check if SC is zero.
 If SC is not zero, repeat from Step 3.
 If SC is zero, proceed to the next step.
6. Output Result:
o The final product is available in registers A and Q.
7. End: Terminate the process.

Booths Algorithm,
Steps of the Algorithm
1. Start: Begin the process.
2. Initialize:
o Load the multiplicand into register BR.
o Load the multiplier into register QR.
o Set the sign of the result based on the signs of BR and QR.
o Clear registers AC and the appended bit Qn+1Q_{n+1}Qn+1.
o Set sequence counter SC to the number of bits in the multiplier, n.
3. Inspect Bits:
o Check the two bits QnQ_{n}Qn and Qn+1Q_{n+1}Qn+1.
 If Qn+1Qn=10Q_{n+1}Q_{n} = 10Qn+1Qn=10, subtract BR from AC.
 If Qn+1Qn=01Q_{n+1}Q_{n} = 01Qn+1Qn=01, add BR to AC.
 If Qn+1Qn=00Q_{n+1}Q_{n} = 00Qn+1Qn=00 or Qn+1Qn=11Q_{n+1}Q_{n} =
11Qn+1Qn=11, do nothing.
4. Arithmetic Shift Right (ashr):
o Perform an arithmetic shift right on the combined registers
ACQRQn+1ACQRQ_{n+1}ACQRQn+1.
5. Decrement SC:
o Decrement the sequence counter SC by 1.
o Check if SC is zero.
 If SC is not zero, repeat from Step 3.
 If SC is zero, proceed to the next step.
6. Output Result:
o The final product is available in registers AC and QR.
7. End: Terminate the process.
Division Operation,
Division of two fixed-point binary numbers in signed-magnitude representa
tion is done with paper and pencil by a process of successive compare,
shift,and subtract operations.
Binary division is simpler than decimal division be- cause the quotient digits
are either 0 or 1 and there is no need to estimate how many times the
dividend or partial remainder fits into the divisor.

The division process is illustrated by a numerical example in Fig.

The divisor B consists of five bits and the dividend A, of ten bits.
The five most significan tbits of the dividend are compared with the divisor.
Since the 5-bit number is smaller than B, we try again by taking the six
most significant bits of A and compare this number with B. The 6-bit
number is greater than B, so we place a 1 for the quotient bit in the sixth
position above the dividend. The divisor is then shifted once to the right and
subtracted from the dividend. The difference is called a partial remainder
because the division could have stopped here to obtain a quotient of 1 and
a remainder equal to the partial remainder. The process is continued by
comparing a partial remainder with the divisor. If the partial remainder is
greater than or equal to the divisor, the quotient bit is equal to 1 . The
divisor is then shifted right and subtracted from the partial remainder. If the
partial remainder is smaller than the divisor, the quotient bit is 0 and no
subtraction is needed. The divisor is shifted once to the right in any case.
Notethat the result gives both a quotient and a remainder.
Floating Point Arithmetic Operation.
During addition or subtraction, the two floating-point operands are in AC
andm BR . The sum or difference is formed in the AC . The algorithm can
be divided into four consecutive parts:
1. Check for zeros.
2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
Multiplication
The multiplication algorithm can be subdivided into four parts:
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product.

Division
The division algorithm can be subdivided into five parts:
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend.
4. Subtract the exponents.
5. Divide the mantissas
Design of Arithmetic
A BCD adder is a circuit that adds two BCD digits in parallel and produces
a sum digit also in BCD. A BCD adder must include the correction logic in
its internal construction. To add 0110 to the binary sum, we use a second
4-bit binary adder as shown in Fig. . The two decimal digits, together with
the input-carry, are first added in the top 4-bit binary adder to produce the
binary sum. When the output-carry is equal to 0, nothing is added to the
binary sum. When it is equal to 1, binary 0110 is added to the binary sum
through the bottom 4-bit binary adder. The output-carry generated from the
bottom binary adder may be ignored, since it supplies information already
available in the output-carry terminal.

I/O Organization:
Peripheral
Devices that are under the direct control of the computer are said
to be connected on-line. These devices are designed to read
information into or out of the memory unit upon command from
the CPU and are considered to be part of the total computer
system. Input or output devices attached to the computer are also
called peripherals . Among the most common peripherals are
keyboards, display units, and printers
I/O Interface –
Input-output interface provides a method for transferring
information between internal storage and external I/0 devices.
Peripherals connected to a computer need special communication
links for interfacing them with the central processing unit. The
purpose of the communication link is to resolve the differences
that exist between the central computer and each peripheral.
The major differences are:
1. Peripherals are electromechanical and electromagnetic devices
and their manner of operation is different from the operation of the
CPU and memory, which are electronic devices. Therefore, a
conversion of signal values may be required.
2. The data transfer rate of peripherals is usually slower than the
transfer rate of the CPU, and consequently, a synchronization
mechanism may be needed.
3. Data codes and formats in peripherals differ from the word
format in the CPU and memory.
4. The operating modes of peripherals are different from each
other and each must be controlled so as not to disturb the
operation of other peripherals connected to the CPU.

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions
Memory-mapped I/O
- A single set of read/write control lines (no distinction between memory and I/O transfer
) - Memory and I/O addresses share the common address space
-> reduces memory address range available –
No specific input or output instruction
-> The same memory reference instructions can be used for I/O transfers - Considerable
flexibility in handling I/O operations

PCI Bus,
A Peripheral Component Interconnect Bus (PCI bus) connects the CPU and expansion boards
such as modem cards, network cards and sound cards. These expansion boards are normally
plugged into expansion slots on the motherboard.

The PCI local bus is the general standard for a PC expansion bus, having replaced the Video
Electronics Standards Association (VESA) local bus and the Industry Standard Architecture
(ISA) bus. PCI has largely been replaced by USB

SCSI Bus,
SCSI (pronounced SKUH-zee and sometimes colloquially known as "scuzzy"), the Small
Computer System Interface, is a set of American National Standards Institute (ANSI) standard
electronic interfaces that allow personal computers (PCs) to communicate
with peripheral hardware such as disk drives, tape drives, CD
ROM drives, printers and scanners faster and more flexibly than previous parallel data transfer
interfaces.
USB,
Universal Serial Bus, USB (pronounced yoo-es-bee) is a plug-and-play interface that allows a
computer to communicate with peripheral and other devices. USB-connected devices cover a
broad range; anything from keyboards and mice, to music players and flash drives. For more
information on these devices, see our USB devices section.
USB may also be used to send power to certain devices, such as smartphones and tablets, as well
as charge their batteries

Data Transfer:
Data transfer refers to the secure exchange of large files between
systems
There are two methods used for transferring data between computers which
are given below: Serial Transmission and Parallel Transmission.
Serial, Parallel,
Serial Transmission:
In Serial Transmission, data-bit flows from one computer to another
computer in bi-direction. In this transmission, one bit flows at one clock
pulse.
Parallel Transmission:
In Parallel Transmission, many bits are flow together simultaneously from
one computer to another computer. Parallel Transmission is faster than
serial transmission to transmit the bits. Parallel transmission is used for short
distance.
[Link] Serial Transmission Parallel Transmission

In this type, a single communication

In this type, multiple parallels
1. link is used to transfer data from one
links used to transmit the data
end to another

In serial transmission, data(bit) flows in In Parallel Transmission, data

2.
bi-direction. flows in multiple lines.

Parallel Transmission is not

3. Serial Transmission is cost-efficient.
cost-efficient.

In Parallel Transmission, eight

In serial transmission, one bit
4. bits transferred at one clock
transferred at one clock pulse.
pulse.

Parallel Transmission is fast in

Serial Transmission is slow in
5. comparison of Serial
comparison of Parallel Transmission.
Transmission.

Generally, Parallel
Generally, Serial Transmission is used
6. Transmission is used for short
for long-distance.
distance.
 [Link] Serial Transmission Parallel Transmission

The circuit used in Parallel

The circuit used in Serial Transmission
7. Transmission is relatively
is simple.
complex.

Synchronous,

Synchronous data transmission is a data transfer method in which a continuous stream

of data signals is accompanied by timing signals (generated by an electronic clock) to
ensure that the transmitter and the receiver are in step (synchronized) with one another.
The data is sent in blocks (called frames or packets) spaced by fixed time intervals.
Synchronous transmission modes are used when large amounts of data must be
transferred very quickly from one location to the other. The speed of the synchronous
connection is attained by transferring data in large blocks instead of individual
characters.
Synchronous transmission synchronizes transmission speeds at both the receiving and
sending end of the transmission using clock signals built into each component. A
continual stream of data is then sent between the two nodes.
The following is a list of characteristics specific to synchronous communication:
 There are no gaps between characters being transmitted.
 Timing is supplied by modems or other devices at each end of the connection.
 Special syn characters precede the data being transmitted.

Asynchronous Modes of Data Transfer,

asynchronous transmission works in spurts and must insert a start bit before each data
character and a stop bit at its termination to inform the receiver where it begins and
ends.
The term asynchronous is used to describe the process where transmitted data is
encoded with start and stop bits, specifying the beginning and end of each character.
 The following is a list of characteristics specific to asynchronous communication:
 Each character is preceded by a start bit and followed by one or more stop bits.
 Gaps or spaces between characters may exist.

Two Asynchronous Data Transfer Methods

Strobe pulse - A strobe pulse is supplied by one unit to indicate the other unit when the transfer
has to occur
Handshaking - A control signal is accompanied with each data being transmitted to indicate the
presence of data - The receiving unit responds with another control signal to acknowledge receipt
of the data
STROBE CONTROL

HANDSHAKING
Strobe Methods Source-Initiated The source unit that initiates the transfer has no way of
knowing whether the destination unit has actually received data Destination-Initiated The
destination unit that initiates the transfer no way of knowing whether the source has actually
placed the data on the bus To solve this problem, the HANDSHAKE method introduces a second
control signal to provide a Reply to the unit that initiates the transfer
SOURCE-INITIATED TRANSFER USING HANDSHAKE

* Allows arbitrary delays from one state to the next

* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
DESTINATION-INITIATED TRANSFER USING HANDSHAKE
* Handshaking provides a high degree of flexibility and reliability because the successful
completion of a data transfer relies on active participation by both units * If one unit is faulty,
data transfer will not be completed -> Can be detected by means of a timeout mechanism

Modes of transfer (techniques for I/O operations)

The possible data transfer between to and from peripherals are:
i. Programmed I/O
In programmed I/O, the processor executes a program that gives it direct control of
the I/O operation,® including sensing I/O device status, sending a read or write
command, and transferring the data.
The execution of I/O related instructions are performed by issuing a command to
the appropriate I/O® module.
I/O module performs the requested action and set the appropriate bits in the I/O
status register.
® The processor periodically checks the status of the I/O module until it finds that
the operation is complete
.® In programmed I/O, CPU stays in programming loop until the I/O unit indicates
that it is ready for data® transfer. This is a time consuming process since it keeps
the processor busy needlessly.
[Link]-initiated I/O
To reduce the time spent on I/O operations for periodically checking the status of I/O device, the CPU
can® use an interrupt-driven I/O approach
In this method, CPU uses an interrupt and commands to inform the interface to issue an interrupt signal
® when the data are available from the device and CPU does other work. When I/O module determines
that the device is ready for data transfer, it interrupts the CPU. When CPU® detects the external
interrupt signal, it immediately stops the task it is processing, and jumps to a service routine to process
the I/O transfer and then returns to the task it was originally performing
Daisy-Chaining Priority The serial connection is called daisy chaining method. In daisy chaining method,
all the devices are connected in serial. The device with the highest priority is placed in the first position,
followed by lower priority devices.

The daisy-chaining method of establishing priority involves serially connecting all devices requesting an
interrupt, with the highest priority device placed first in the chain, followed by lower-priority devices.
This connection enables interrupt recognition based on a wired logic connection, where a low-level
interrupt signal triggers the interrupt line, prompting the CPU to respond. When no interrupts are
pending, the interrupt line remains in a high-level state. The CPU acknowledges an interrupt request by
enabling the interrupt acknowledge line, which passes through each device in the chain unless blocked
by a higher-priority device with a pending interrupt. Each device communicates its interrupt status and
passes on the acknowledge signal accordingly, ensuring that the device closest to the CPU with the
highest priority receives priority for interrupt handling.

The parallel priority interrupt method utilizes a register where interrupt signals from each device
independently set corresponding bits, establishing priority based on the position of these bits in
the register. Alongside the interrupt register, a mask register controls the status of each interrupt
request, allowing for the disabling of lower-priority interrupts during higher-priority device
servicing and enabling high-priority interrupts to interrupt the CPU during lower-priority device
servicing. The priority logic for a system with four interrupt sources involves an interrupt
register and a mask register, each with the same number of bits. These bits are applied to an
AND gate, along with their corresponding mask bits, to produce inputs for a priority encoder,
ensuring interrupts are recognized only if their corresponding mask bit is set to 1. The priority
encoder generates vector address bits for transfer to the CPU and sets an interrupt status flip-flop
(IST) when an unmasked interrupt occurs. The interrupt enable flip-flop (IEN) provides overall
control over the interrupt system, with its outputs ANDed to produce a common interrupt signal
for the CPU. The interrupt acknowledge (INTACK) signal from the CPU enables the output
register, allowing the placement of the vector address (VAD) into the data bus. The interaction
between the priority interrupt controller and the CPU is facilitated by this setup, ensuring
efficient handling of interrupts based on their priority levels.
[Link]
Direct Memory Access (DMA) is a feature in computer systems that allows certain hardware subsystems
to access the main system memory (RAM) independently of the central processing unit (CPU).
DMA is a method that lets an input/output (I/O) device send or receive data directly to or from the main
memory, bypassing the CPU to speed up memory operations
DMA SIGNALS
1. DMAREQ: Peripheral requests DMA transfer from the DMA controller.
2. DACK: DMA controller acknowledges the peripheral's DMA request.
3. HOLD: DMA controller requests control of the system bus from the CPU.
4. HLDA: CPU acknowledges the DMA controller's bus request and releases the bus.
5. BR: DMA controller requests the bus from the CPU (similar to HOLD).
6. BG: CPU grants control of the bus to the DMA controller (similar to HLDA).

7. INT: DMA controller signals to the CPU that the DMA transfer is complete.
During a typical DMA operation, the sequence of signals is as follows: The peripheral device first asserts
the DMAREQ signal to request a DMA transfer from the DMA controller. The DMA controller then
requests control of the system bus by asserting the HOLD (or BR) signal to the CPU. The CPU
acknowledges this request and releases the bus by asserting the HLDA (or BG) signal. The DMA
controller, upon gaining control of the bus, acknowledges the peripheral's request with the DACK signal.
Once the DMA transfer is complete, the DMA controller signals the CPU by asserting the INT signal.
I/O Processor.
An I/O Processor (IOP) is a specialized processor designed to handle input/output operations, freeing
the main CPU from these tasks and improving overall system efficiency. Here’s a concise explanation of
its key aspects:
An I/O Processor is a dedicated processor that manages data transfer between peripheral devices (such
as disk drives, network cards, and printers) and the main system memory. It performs I/O operations
independently of the CPU.
Functions of an I/O Processor
1. Data Transfer Management: Handles the transfer of data to and from peripheral devices.
2. Offloading CPU: Frees the CPU from I/O processing tasks, allowing it to focus on executing
application and system code.
3. Interrupt Handling: Manages interrupts from I/O devices, ensuring timely processing without
burdening the CPU.
4. Data Formatting: Converts data formats as needed between the peripheral devices and the
main memory.
An I/O Processor significantly enhances system performance by managing I/O tasks independently of the
CPU. This allows the CPU to focus on processing tasks while the IOP efficiently handles data transfer and
communication with peripheral devices.
Each IOP takes care of I/O task keeping CPU free from involvement of I/O transfer.
® IOP has ability to execute I/O instruction which gives it complete control over I/O operation. It has its
own® instruction set with I/O instructions and a local memory in its own right. IOP accesses memory by
cycle stealing.
® CPU directs IOP to execute an I/O programs in memory. The IOP fetches and executes these
instructions® without CPU intervention. IOP interrupts CPU when entire operation has been performed.
The major difference between DMA and IOP is that IOP can fetch and execute I/O instruction from
memory® but DMA cannot fetch and execute the I/O instruction.
Memory Hierarchy
+---------------------+
| Registers |
+---------------------+
|
+---------------------+
| Cache |
+---------------------+
|
+---------------------+
| RAM |
+---------------------+
|
+---------------------+
| Secondary Storage |
+---------------------+
 |

 Registers: The fastest and smallest memory located within the CPU, used for temporary
storage of data and instructions.

 Cache: A high-speed memory located on the CPU, combining multiple levels (L1, L2, L3) to
store frequently accessed data and instructions.

 RAM (Random Access Memory): Main system memory that is fast and volatile, used for
active processes and data.

 Secondary Storage: Non-volatile storage such as HDDs and SSDs, used for long-term
storage of data and programs.


Memory Organization:
Memory organization refers to how data is stored and accessed within a computer's memory
system. There are several levels of memory organization in a typical computer system:
1. Registers: These are the smallest units of memory and are located within the CPU.
Registers hold data that are currently being processed by the CPU. They have the fastest
access time but are limited in capacity.
2. Cache Memory: Cache memory is a small amount of high-speed static RAM (SRAM)
that is located within or very close to the CPU. Its purpose is to temporarily store
frequently accessed data and instructions to speed up processing. Cache memory is
organized into several levels (L1, L2, L3) based on proximity to the CPU and size, with
L1 being the closest and smallest, and L3 being the farthest and largest.
3. Main Memory (RAM): This is the primary memory in a computer system where data
and programs that are actively being used by the CPU are stored. Main memory is
typically dynamic random-access memory (DRAM) and is organized into memory cells,
each with its own unique address. Accessing data from main memory is slower than
accessing data from cache memory but faster than accessing data from secondary storage
devices.
4. Secondary Storage: This includes devices like hard disk drives (HDDs), solid-state
drives (SSDs), and optical drives. Secondary storage devices have much larger storage
capacities compared to main memory but are slower to access. Data stored in secondary
storage is typically transferred to main memory when it needs to be processed by the
CPU.
5. Virtual Memory: Virtual memory is a memory management technique that uses
secondary storage to simulate additional main memory. When the available physical
memory (RAM) is insufficient to hold all the data and programs that are actively being
used, virtual memory allows the operating system to swap data between RAM and disk
storage as needed.
Memory organization plays a crucial role in the performance of a computer system, with faster
and more efficient access to data and instructions resulting in better overall performance.
Optimizing memory organization involves techniques such as cache management, memory
allocation strategies, and virtual memory management.

Main memory-RAM,
Main memory, also known as RAM (Random Access Memory), is a type of computer memory
that stores data and instructions that are actively being used by the CPU (Central Processing
Unit) or programs running on the computer. RAM is volatile memory, meaning that its contents
are lost when the power is turned off.
Here are some key characteristics of main memory (RAM):
1. Volatile: RAM is volatile memory, which means that its contents are lost when the
power is turned off. This is in contrast to non-volatile memory like hard disk drives
(HDDs) and solid-state drives (SSDs), which retain data even when the power is off.
2. Random Access: RAM is called "random access" because any storage location in RAM
can be accessed directly and in any order, unlike sequential access memory devices like
magnetic tape.
3. Speed: RAM provides fast access to data and instructions compared to secondary storage
devices like HDDs and SSDs. This fast access speed allows the CPU to retrieve and store
data quickly during program execution.
4. Capacity: The capacity of RAM determines how much data and program instructions
can be stored in main memory at any given time. RAM capacities vary widely, ranging
from a few gigabytes (GB) in consumer-grade computers to terabytes (TB) in high-end
servers.
5. Types: There are different types of RAM, including DDR (Double Data Rate), DDR2,
DDR3, DDR4, and DDR5, each offering improvements in speed and efficiency over
previous generations. Other types of RAM include SRAM (Static RAM) and DRAM
(Dynamic RAM).
6. Access Time: RAM typically has much faster access times compared to secondary
storage devices. Access times are measured in nanoseconds (ns) or milliseconds (ms),
with RAM access times typically in the range of nanoseconds.
7. Addressable: Each byte of data in RAM is assigned a unique address, allowing the CPU
to locate and access specific data quickly.
Main memory (RAM) is a critical component of computer systems, and its performance directly
impacts overall system performance. The amount and speed of RAM in a computer system affect
its ability to run multiple programs simultaneously, handle large datasets, and execute tasks
efficiently. Therefore, upgrading RAM is often a cost-effective way to improve the performance
of a computer system.

ROM,
ROM (Read-Only Memory) is a type of non-volatile memory that stores data and instructions
that are permanently written during manufacturing and cannot be easily modified or erased by
normal computer operations. Unlike RAM (Random Access Memory), which is volatile and
loses its contents when power is turned off, ROM retains its data even when power is removed.
Here are some key characteristics of ROM:
 1. Non-Volatile: ROM is non-volatile memory, meaning it retains its contents even when
the power is turned off. This characteristic makes ROM suitable for storing essential
system software and firmware that must be preserved between power cycles.
2. Read-Only: The term "read-only" indicates that the data stored in ROM can typically
only be read and accessed; it cannot be easily modified or overwritten by the user or the
computer's operating system. This read-only nature provides stability and security for
critical system software.
3. Permanent Storage: ROM is used to store firmware, BIOS (Basic Input/Output
System), boot loaders, and other essential system software that is necessary for the
computer to start up and operate. These programs are permanently written during
manufacturing and are not intended to be modified during normal use.

Secondary Memory –
Secondary memory, also known as auxiliary memory or external memory, refers to storage
devices that supplement the primary memory (RAM) of a computer system. Unlike primary
memory, which provides fast access to data and instructions but is volatile, secondary memory
offers larger storage capacities and retains data even when the power is turned off. Secondary
memory is essential for storing data and programs that are not actively being used by the CPU
but need to be preserved for future use. Here are some common types of secondary memory:
1. Hard Disk Drives (HDDs): HDDs are one of the most common types of secondary
storage devices. They use magnetic storage to store data on spinning disks called platters.
HDDs offer large storage capacities at relatively low cost but are slower than solid-state
drives (SSDs) in terms of access speed.
2. Solid-State Drives (SSDs): SSDs use flash memory to store data, providing faster access
speeds and better durability compared to HDDs. SSDs are becoming increasingly popular
in both consumer and enterprise environments due to their superior performance, lower
power consumption, and smaller form factor.
3. Flash Drives (USB Drives): Flash drives, also known as USB drives or thumb drives,
are portable storage devices that use flash memory to store data. They are small,
lightweight, and easy to use, making them popular for transferring files between
computers and storing data on the go.
4. Memory Cards: Memory cards, such as Secure Digital (SD) cards and CompactFlash
(CF) cards, are used primarily in digital cameras, smartphones, and other portable devices
to store photos, videos, music, and other data. They offer high storage capacities in a
compact form factor and can be easily inserted and removed from compatible devices.
5. Optical Discs: Optical discs, such as CDs, DVDs, and Blu-ray discs, use laser
technology to store data. They are commonly used for distributing software, movies,
music, and other multimedia content. Optical discs offer relatively large storage
capacities and are read-only (ROM) or read-write (R/W) depending on the type.
Secondary memory plays a crucial role in computer systems by providing long-term storage for
data and programs, enabling users to store large amounts of information and access it as needed.
The choice of secondary memory device depends on factors such as cost, performance, capacity,
and portability, as well as the specific requirements of the application or use case

Magnetic Tape,
Magnetic tape is a form of secondary storage medium that uses a long, narrow strip of plastic
film coated with a magnetic material to store digital data. It is one of the oldest and most
traditional forms of data storage, dating back to the mid-20th century. Magnetic tape is still used
today in various applications where large volumes of data need to be stored economically and
accessed sequentially. Here are some key characteristics of magnetic tape:
1. Storage Capacity: Magnetic tape offers high storage capacities, making it suitable for
archiving and backup purposes. Modern magnetic tape cartridges can store terabytes (TB)
or even petabytes (PB) of data.
2. Sequential Access: Unlike random-access memory (RAM) or solid-state drives (SSDs),
which allow data to be accessed randomly, magnetic tape is a sequential access medium.
This means that data is read or written to the tape in a linear fashion from one end to the
other. Accessing specific data requires fast-forwarding or rewinding the tape to the
appropriate position, which can be time-consuming compared to random access media.
3. Reliability: Magnetic tape is known for its durability and reliability. Unlike optical discs
or flash drives, which can degrade over time or be affected by environmental factors such
as temperature and humidity, magnetic tape is relatively robust and can withstand harsh
conditions.
4. Cost-Effectiveness: Magnetic tape is often more cost-effective than other storage media,
particularly for large-scale data storage. The cost per gigabyte of storage is typically
lower compared to hard disk drives (HDDs) or solid-state drives (SSDs), making
magnetic tape a preferred choice for long-term archival storage of massive datasets.
5. Backup and Archiving: Magnetic tape is commonly used for backup and archival
purposes in enterprise environments, government agencies, research institutions, and
other organizations that need to store large volumes of data securely and cost-effectively.
Tape backups are often stored offsite in secure facilities to protect against data loss due to
disasters such as fires, floods, or cyberattacks.

Disk,
1.  Hard Disk Drives (HDDs): Magnetic storage devices with rotating disks coated in
magnetic material, used for long-term storage in computers, with capacities from
gigabytes to terabytes.

2. Solid-State Drives (SSDs): Flash memory-based storage with no moving parts, offering
faster access times, lower power consumption, and greater durability than HDDs, ideal
for high-performance applications.
3. External Hard Drives: Portable storage devices connecting via USB, Thunderbolt, or
other interfaces, containing either HDDs or SSDs, used for backups, file storage, and data
transfer.
4. Optical Discs: Use laser technology for data storage and retrieval, including CDs, DVDs,
and Blu-ray discs, commonly used for software distribution, music, movies, and archival
data.
5. Comparison: HDDs and SSDs are primary internal storage options, with SSDs offering
better performance, while external hard drives and optical discs provide additional or
portable storage solutions.
Optical Storage,
 Definition and Technology: Optical storage uses laser technology to read and write data
onto optical discs, which are flat, circular discs made of plastic or glass with a reflective coating.

 Types of Optical Discs: Common optical storage media include CDs (700 MB), DVDs (4.7
GB single-layer, 8.5 GB dual-layer), and Blu-ray discs (25 GB single-layer, 50 GB dual-layer).

 Data Encoding: Data is encoded as microscopic pits and lands on the disc's surface. A laser
beam reads these reflections as binary data (0s and 1s), allowing for sequential or random access.

 Read-Only Discs: Read-only discs, such as CD-ROMs, DVDs, and Blu-ray movies, are pre-
recorded and cannot be modified by the user.

 Recordable and Rewritable Discs: Recordable discs (CD-R, DVD-R, BD-R) can be written
to once, while rewritable discs (CD-RW, DVD-RW, BD-RE) can be written to, erased, and
rewritten multiple times.

Cache Memory: Cache Structure and Design,

Cache memory, often referred to simply as "cache," is a type of high-speed volatile memory
located between the CPU (Central Processing Unit) and the main memory (RAM) in a computer
system. Its primary purpose is to temporarily store frequently accessed data and instructions,
allowing the CPU to access them more quickly than if they were retrieved directly from the main
memory or other storage devices. Here are some key points about cache memory:
1. Speed: Cache memory is significantly faster than main memory and other types of
storage devices. It operates at speeds closely matched to the CPU's processing speed,
providing rapid access to data and instructions needed for program execution.
2. Proximity to the CPU: Cache memory is located on the CPU chip or very close to it,
minimizing the time required for data transfer between the CPU and the cache. This close
proximity ensures that frequently accessed data can be retrieved with minimal delay.
3. Hierarchy: Cache memory is organized into multiple levels, typically referred to as L1,
L2, and sometimes L3 cache. L1 cache is the smallest and fastest, located directly on the
CPU core. L2 cache is larger but slightly slower, and L3 cache, if present, is the largest
but slower still. The hierarchy allows for a balance between speed and capacity, with
frequently accessed data stored in the faster, smaller caches, and less frequently accessed
data stored in the larger, slower caches.
4. Cache Coherency: Cache coherence refers to the maintenance of consistency between
multiple caches that store copies of the same data. When one cache modifies a particular
memory location, it must ensure that the changes are reflected in all other caches holding
copies of that data. Cache coherence protocols, such as MESI (Modified, Exclusive,
Shared, Invalid), are used to manage cache coherence and ensure data integrity.
5. Cache Hits and Misses: When the CPU requests data or instructions, the cache checks
whether the requested data is already stored in the cache. If the data is found in the cache
 (cache hit), it can be quickly retrieved. If the data is not found in the cache (cache miss),
it must be fetched from the main memory, a process that takes longer and slows down
program execution.

Cache memory plays a crucial role in improving the overall performance of a computer system
by reducing the average memory access time and minimizing the impact of the slower main
memory. It is an essential component of modern computer architectures and is found in virtually
all CPUs, from desktops and laptops to servers and mobile devices.

Mapping Scheme,
a mapping scheme refers to the method used to determine how data from main memory is
mapped to specific locations in the cache. The mapping scheme governs how cache memory
addresses are translated to main memory addresses and determines how data is retrieved from
and stored in the cache. Common mapping schemes include:
1. Direct Mapping:
In the Direct Mapping using a random-access memory (RAM) for cache, the CPU
address is divided into two fields: the index field (9 bits) and the tag field (6 bits). The
index field determines the cache line to access, while the tag field uniquely identifies the
memory block within the cache line. Both the tag and index bits are used to access main
memory. The number of bits in the index field corresponds to the number of address bits
required to access the cache memory. This approach allows for a simpler cache
implementation using RAM, potentially reducing cost compared to associative memories,
which require additional logic for each cell.
 In a direct-mapped cache, each block of main memory is mapped to exactly one specific cache
line. Direct-mapped caches are simple and efficient but may suffer from cache conflicts, where
multiple memory blocks map to the same cache line.

In direct-mapped caches, memory addresses are divided into tags and indexes. Tags uniquely
identify memory blocks stored in cache lines, while indexes determine which cache line to
access based on a modulo function. This efficient mapping scheme allows for quick cache
lookups, ensuring that requested data can be retrieved swiftly when needed.

 Address: Refers to the location in memory where data is stored or retrieved.

 Tag: A portion of the memory address that uniquely identifies the memory block stored in
the cache line.
 Index: Specifies which cache line the data should be placed in or retrieved from, determined
by a modulo function based on a subset of the address bits.
 Direct-Mapped Cache: Each memory block is mapped to exactly one specific cache line
based on the index.
 Function: The combination of tag and index allows efficient cache lookup to determine if
the requested data is present in the cache and retrieve it if necessary.
Set-associative mapping
Set-associative mapping improves upon the limitations of direct mapping by allowing multiple
data words with different tag values to reside in the cache memory under the same index address.
In this organization, each cache word stores two or more data words along with their associated
tags, forming a set. For instance, with a set size of two, each index address refers to two data
words and their tags. With each tag requiring six bits and each data word having 12 bits, the
word length becomes 36 bits. With a nine-bit index address accommodating 512 words, the
cache memory size is 512 x 36 bits, capable of holding 1024 words of main memory, as each
word of cache contains two data words. Generally, a set-associative cache of set size k
accommodates k words of main memory in each word of cache.

Set-associative mapping is a cache organization scheme that combines aspects of direct mapping
and fully associative mapping. In set-associative caches, each block of main memory can be
mapped to a set of cache lines, rather than just one line as in direct-mapped caches. These cache
sets typically contain multiple cache lines, allowing for more flexibility in cache management.
Set-associative mapping helps reduce the likelihood of cache conflicts compared to direct
mapping while maintaining relatively low complexity.
In set-associative mapping, multiple cache lines are grouped into sets, and each memory block
can be mapped to a specific set. Within each set, multiple cache lines compete for storing data
from different memory blocks. This allows for multiple tags to be stored within the same index,
offering greater flexibility in caching and reducing the chance of cache conflicts compared to
direct mapping.
Associative Mapping
 In associative mapping, the cache is composed of associative memory, which allows any
memory block to be stored in any cache line without restrictions. This means that each cache
line can store data from any memory block, providing maximum flexibility in caching. Associative
memory enables efficient caching by quickly searching for data across all cache lines without the
need for explicit indexing, reducing the likelihood of cache conflicts compared to other mapping
schemes.

Replacement Algorithm,

In set-associative caches, when a miss occurs and the set is full, one of the tag-data items must be
replaced with a new value. The most common replacement algorithms used are:
 Random Replacement: The control randomly chooses one tag-data item for
replacement.
 First-In, First-Out (FIFO): This procedure selects the item that has been in the set the
longest for replacement.
 Least Recently Used (LRU): This algorithm selects the item that has been least recently
used by the CPU for replacement. Implementing FIFO and LRU requires adding a few
extra bits in each cache word to track usage information.

Virtual Memory,
Virtual memory is a crucial concept in modern computer systems that extends the available memory
beyond the physical RAM (Random Access Memory) installed in a computer.
Pages and frames are fundamental concepts in the context of virtual memory and memory
management. Here's an explanation:
1. Pages:
o In virtual memory systems, memory is divided into fixed-size blocks called pages.
These pages are the smallest units of data that can be managed by the virtual
memory system.
Frames:
 Frames are the corresponding units of memory in physical memory (RAM) that store the
contents of pages. Like pages, frames are also fixed-size blocks of memory.
Page address translation to frame address involves looking up the page table using the page number
extracted from the virtual address. The page table maps virtual pages to physical frames, providing the
corresponding frame number. This frame number, along with the offset within the page, forms the
physical address. Once computed, the CPU can access the data in the corresponding frame in physical
memory. This process enables programs to interact with a larger virtual address space than physically
available in RAM, facilitating efficient memory utilization and multitasking in virtual memory systems.
In above fig CPU requested page 5 line no: 0101010011 that coverted
into frame no 01 line no: 0101010011
memory management hardware
A memory management unit (MMU) is a computer hardware component that
handles all memory and caching operations associated with the processor. In
other words, the MMU is responsible for all aspects of memory management. It's
usually integrated into the processor, although, in some systems, it occupies a
separate integrated circuit (IC).
What does an MMU do?
The work of the MMU falls into three major categories:
 Hardware memory management oversees and regulates the processor's
use of random access memory and cache memory.
 OS memory management ensures adequate memory resources are
available for the objects and data structures of each running program.
 Application memory management allocates each individual program's
required memory, then recycles freed-up memory space when the operation
concludes.
How does the MMU work?
Next to the central processing unit (CPU), memory is the most important part of a
computer. It's where the work gets done and where instructions and other
computing functions are performed. Memory ensures a computer's utilities work
correctly and applications and input/output functions are performed.
An MMU is an essential part of memory subsystems, keeping all memory-related
functions operating efficiently. Memory management helps with the following
functions:
 Memory distribution. The MMU moves memory resources to where they can
best meet system requirements, typically before and after systems processes
are executed.
 Monitoring. It tracks all memory resources.
 Efficiency. It conserves main memory and other memory resources.
 System integrity. It reduces the likelihood of memory fragmentation and poor
memory allocation.
 Data integrity. It ensures data integrity is maintained.
 Data risk. It minimizes the risk of data corruption.
 Cost control. It keeps memory-related costs down

Multiprocessors:
Multiprocessors refer to computer systems with two or more central processing units (CPUs) that share
the same memory and work in tandem to execute tasks. The main goal of multiprocessor systems is to
increase processing power and performance, improve reliability, and allow for better scalability of
computing resources. Here are some key points about multiprocessors:
Types of Multiprocessors
1. Symmetric Multiprocessing (SMP):
2.  All processors share a single, common memory space and have equal access to I/O
devices.
3.  Each processor runs its own operating system copy and works on its own task.
Asymmetric Multiprocessing (AMP):
 A master processor controls the system and assigns tasks to subordinate processors.
 Other processors handle specific tasks or perform specific functions and do not share
memory in the same way as in SMP.
 Common in real-time systems and embedded systems.
Advantages
1. Increased Performance: By parallelizing tasks, multiprocessors can complete more work in less
time compared to a single processor.
2. Reliability and Fault Tolerance: If one processor fails, others can take over its tasks, ensuring
continued operation.
3. Efficiency in Handling Large Tasks: Suitable for applications requiring substantial computational
power, such as scientific simulations, data analysis, and large-scale transaction processing.

Characteristics of Multiprocessor,
Multiprocessor systems exhibit several key characteristics that distinguish them from single-
processor systems. Here are the main characteristics:
1. Shared Memory
 Central Memory: All processors in a multiprocessor system share a common main memory,
allowing them to access and communicate data quickly.
 Global Address Space: Each processor can address any memory location directly, facilitating
data sharing and coordination.
2. Interprocessor Communication
 Synchronization: Mechanisms like semaphores, locks, and barriers are used to synchronize tasks
and ensure proper sequencing.
 Communication: Processors can exchange data either through shared memory or through
explicit message-passing protocols.
3. Load Balancing
 Task Distribution: The system dynamically allocates tasks to processors to ensure an even
distribution of the workload.
 Dynamic Scheduling: Algorithms are used to assign and reassign tasks in real-time based on
processor load and availability.
4. Scalability
 Expandable Architecture: Multiprocessor systems are designed to allow the addition of more
processors to increase computational power.
 Performance Scaling: The system can handle increased workloads by adding more processors
without a proportional increase in complexity or performance overhead.
5. Cache Coherence
 Consistent Memory View: Mechanisms like MESI (Modified, Exclusive, Shared, Invalid) protocol
ensure that all processors have a consistent view of memory, even if they have their own
caches.
 Synchronization Protocols: Protocols are employed to maintain coherence between the caches
of different processors, ensuring data integrity.
6. Resource Sharing
 Shared Peripherals: I/O devices, storage, and other peripherals are shared among all processors,
which can lead to contention and necessitate efficient management.
 Bus Arbitration: Mechanisms to manage access to the shared bus to prevent conflicts and
ensure fair access to memory and I/O resources.
7. Fault Tolerance
 Redundancy: The system can continue functioning even if one or more processors fail,
enhancing reliability.
 Error Detection and Recovery: Mechanisms to detect faults and errors and to reassign tasks
from failed processors to operational ones.
8. High Throughput
 Parallel Processing: Multiple tasks are processed simultaneously, increasing the overall
throughput of the system.
 Concurrency: Support for concurrent execution of processes, leading to better utilization of
processing power.

Structure of Multiprocessor-Interprocessor Arbitration,

The structure of a multiprocessor system is designed to efficiently utilize multiple CPUs to work
in parallel. The structure can be broadly categorized into the following components:
1. Processor Units (CPUs)
 Multiple Processors: The system contains two or more processors, each capable of executing
instructions independently.
 Homogeneous vs. Heterogeneous: Processors can be identical (homogeneous) or different
(heterogeneous) in terms of their architecture and capabilities.
2. Memory Architecture
 Shared Memory: All processors have access to a common memory space.
o Uniform Memory Access (UMA): All processors access memory with the same latency
and bandwidth.
o Non-Uniform Memory Access (NUMA): Memory access time depends on the memory
location relative to a processor. This can improve scalability by reducing memory access
contention.
 Distributed Memory: Each processor has its own local memory, and processors communicate
via a high-speed interconnect.
3. Interconnection Network
 Bus-Based Systems: All processors are connected to a common bus.
o Single Bus: Simple and cost-effective but can become a bottleneck with many
processors.
o Multiple Buses: More complex but can alleviate the bottleneck.
 Network-Based Systems: Use sophisticated networks to connect processors.
o Crossbar Switch: Allows any processor to connect to any memory module, providing
high bandwidth and low latency.
o Mesh and Torus Networks: Processors are connected in grid-like structures, balancing
cost and performance.
o Ring and Hypercube Networks: Provide different trade-offs between complexity,
performance, and scalability.
4. Cache System
 Multi-Level Caches: Multiple levels of caches (L1, L2, L3) are used to reduce memory access
latency.
o Private Caches: Each processor has its own set of caches.
o Shared Caches: Some levels of cache are shared among processors to improve data
sharing and reduce redundancy.
 Cache Coherence Protocols: Ensure that all processors have a consistent view of memory.
o MESI Protocol: Commonly used to manage cache coherence.
5. Input/Output (I/O) Subsystem
 Shared I/O Devices: I/O devices are shared among processors.
 I/O Controllers: Manage access to shared I/O resources, often providing direct memory access
(DMA) capabilities to reduce processor involvement in I/O operations.
6. Synchronization Mechanisms
 Locks and Semaphores: Used to control access to shared resources and prevent race conditions.
 Barriers: Ensure that all processors reach a certain point in execution before any can proceed.
 Atomic Operations: Hardware support for atomic read-modify-write operations to facilitate
synchronization.
7. Operating System (OS) and Software Support
 Multiprocessing OS: The operating system must support multiprocessing with features like
process scheduling, inter-process communication, and synchronization.
 Parallel Programming Models: Software needs to be designed to exploit parallelism, using
models such as threads, message passing (MPI), and parallel libraries (OpenMP).
8. Control Unit
 Task Scheduling: Distributes tasks among processors to balance the load and optimize
performance.
 Fault Tolerance Management: Monitors processor health and reassigns tasks from failed
processors to operational ones.
9. Performance Monitoring and Optimization
 Performance Counters: Hardware and software tools to monitor system performance.
 Optimization Algorithms: Techniques to optimize load balancing, memory access patterns, and
cache utilization.
Structural Diagram
A simplified diagram of a multiprocessor system might look like this:
+-----------------------------------+
| Interconnection |
| Network/Bus |
+-----------------------------------+
/ | | | \
/ | | | \
+---------+ +---------+ +---------+ +---------+ +---------+
| CPU 1 | | CPU 2 | | CPU 3 | | CPU 4 | | CPU N |
| Cache | | Cache | | Cache | | Cache | | Cache |
+---------+ +---------+ +---------+ +---------+ +---------+
\ / / / / /
\ / / / / /
+-------------------------------------------+
| Shared Memory |
+-------------------------------------------+
+-------------------------------------------+
| I/O Subsystem |
+-------------------------------------------+
In this diagram:
 Each CPU has its own cache.
 All CPUs are connected via an interconnection network.
 Shared memory is accessible to all CPUs.
 The I/O subsystem is shared among all CPUs.
This structure allows multiple processors to work together efficiently, sharing memory and I/O
resources while maintaining high performance and scalability.

Inter-Processor Communication and Synchronization.

Inter-Processor Communication (IPC)
IPC mechanisms facilitate data exchange between processors. These mechanisms can be broadly
categorized into two types: shared memory communication and message passing.
Shared Memory Communication
 Shared Variables: Processors communicate by reading and writing to shared memory locations.
 Memory-Mapped Files: Sections of memory that can be accessed by multiple processors for
communication purposes.
 Atomic Operations: Hardware-supported operations that read, modify, and write a memory
location in a single, uninterruptible step. Examples include test-and-set, fetch-and-add, and
compare-and-swap.
Message Passing
 Direct Communication: Processors send messages directly to each other using send and receive
primitives. This method is often used in systems with distributed memory.
 Indirect Communication: Messages are sent to and received from a shared queue or mailbox.
This method decouples the sender and receiver, making the system more flexible.
Synchronization
Synchronization mechanisms ensure that processors can safely and correctly access shared
resources and coordinate their operations. Common synchronization techniques include:
Locks
Mutex (Mutual Exclusion): A lock that allows only one processor to access a resource at a time.
Mutexes prevent race conditions by ensuring that only one processor can execute a critical
section of code at any given time.
 Spinlocks: A type of lock where a processor repeatedly checks if the lock is available. While this
can waste CPU cycles, it is useful when the wait time is expected to be short.
Semaphores
 Binary Semaphores: Also known as mutexes, these semaphores can take only two values (0 or
1) and are used to manage access to a single resource.
 Counting Semaphores: These semaphores can take a range of values and are used to manage
access to multiple instances of a resource.

Memory in Multiprocessor System,

Memory architecture in a multiprocessor system is a critical component that influences the
performance, scalability, and complexity of the system. There are several key aspects to consider
when discussing memory in multiprocessor systems, including memory organization, access
patterns, and coherence protocols.
Types of Memory Architectures
1. Shared Memory Architecture
 Uniform Memory Access (UMA):
o All processors share the same physical memory and have equal access times to all
memory locations.
o Simple and cost-effective but can become a bottleneck as the number of processors
increases.
o Commonly used in symmetric multiprocessor (SMP) systems.
 Non-Uniform Memory Access (NUMA):
o Memory is divided into multiple regions, each associated with a specific processor or
group of processors.
o Access time varies depending on whether a processor is accessing its local memory or
remote memory.
o Scales better than UMA by reducing memory access contention and increasing memory
bandwidth.
o Commonly used in larger multiprocessor systems.
2. Distributed Memory Architecture
 No Shared Memory:
o Each processor has its own local memory, and processors communicate via message
passing.
o Requires explicit communication protocols like MPI (Message Passing Interface).
 o Highly scalable but more complex to program due to the need for explicit
communication management.
o Commonly used in massively parallel processing (MPP) systems and cluster computing.

Concept of Pipelining,
Pipelining is a technique used in computer architecture to increase the throughput of a processor
by overlapping the execution of multiple instructions. It breaks down the execution path of
instructions into discrete stages, allowing multiple instructions to be in different stages of
execution simultaneously. This concept is similar to an assembly line in a factory, where
different stages of production are performed in parallel.
Key Concepts of Pipelining
1. Pipeline Stages
A typical instruction execution is divided into several stages, each performing a part of the
instruction's work. Common stages include:
 Fetch (F): Retrieving the instruction from memory.
 Decode (D): Interpreting the instruction and preparing the necessary data paths.
 Execute (E): Performing the operation specified by the instruction.
 Memory (M): Accessing memory for load or store operations.
 Write-back (W): Writing the result back to the register file.


Example: 5-Stage Pipeline
Here’s an example of a simple 5-stage pipeline:
1. Instruction Fetch (IF)
2. Instruction Decode (ID)
3. Execution (EX)
4. Memory Access (MEM)
5. Write Back (WB)
Pipeline Diagram
To visualize this, consider the following sequence of instructions and how they flow through a 5-
stage pipeline over time (cycles):
Cycle Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5
1 IF
2 ID IF
3 EX ID IF
4 MEM EX ID IF
5 WB MEM EX ID IF
6 WB MEM EX ID
7 WB MEM EX
Cycle Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5
8 WB MEM
9 WB
Each instruction moves to the next stage in each clock cycle, allowing multiple instructions to be
processed simultaneously at different stages.

Vector Processing,
Vector processing is a computing paradigm that enables the processing of entire vectors of data
in a single operation, significantly accelerating performance for specific types of computations. It
is particularly useful in applications involving large datasets and repetitive calculations, such as
scientific computing, engineering simulations, and graphics processing.
Key Concepts of Vector Processing
1. Vector vs. Scalar Processing
 Scalar Processing: Traditional CPUs perform operations on single data elements at a time.
 Vector Processing: Operations are performed on entire vectors (arrays) of data simultaneously.
This is achieved using special hardware called vector processors.

Array Processing,
Array processing is a computational technique that involves performing operations on entire
arrays of data simultaneously. This approach is highly efficient for tasks that involve large
datasets and repetitive operations, such as matrix computations, image processing, and scientific
simulations. Array processors, also known as SIMD (Single Instruction, Multiple Data)
machines, are designed to exploit data parallelism by applying the same operation to multiple
data points in parallel.
Key Concepts of Array Processing
1. Data Parallelism
 Data Parallelism: Involves distributing data across multiple processing elements and performing
the same operation on each data element simultaneously. This is the core principle of array
processing.
2. SIMD Architecture
 Single Instruction, Multiple Data (SIMD): A type of parallel computing where a single instruction
operates on multiple data points simultaneously. SIMD is the foundation of array processing.
3. Processing Elements (PEs)
 Processing Elements: The individual computational units in an array processor. Each PE
performs the same operation on different pieces of data.
RISC And CISC,
Comparison: RISC vs. CISC
Feature RISC CISC
Instruction Set Small, simple, and fixed-size Large, complex, and variable-size
Instruction
Single-cycle for most instructions Multiple cycles for many instructions
Execution
Memory Access Load/store architecture Instructions can directly access memory
Registers Large number of general-purpose Fewer registers, more memory-based
 Feature RISC CISC
registers operations
Optimized for high-performance Complex instructions may take longer to
Performance
pipelining execute
Compiler Design Simplified due to uniform instructions More complex due to varied instruction set
Larger, more instructions for complex Smaller, fewer instructions for complex
Code Size
tasks tasks
Easier to implement and more More challenging due to instruction
Pipelining
efficient complexity