SOLUTIONS Level1 1 Extrinsic Semiconductor 1. Number density of atoms in silicon speci d t silicon specimen =5 x 10" aoms/n 5 10"aon sons neeee ee lum atoms doped per atoms, so total number of $0 total number of indium atoms doped per cm? of silicon will be n=5 > 107 5x10” = 10" atoms em”? 2. By using mass action taw n? af (oy 10" perm? 3. The number density of donor atoms, nu, = 5X20" /m? 10° =5x 10" atoms/m? (As 1 ppm =4 part per milir Each donor atom contributes one free electron, So x10" /m? By using mass action lawn? = n,n, 7.5 Wd > Way 74a 5. (a) n-type semiconductor as n, > n, (b)0 = etna, + mgi,) = 1.6% 10" [4.5 x10" x 096-+1.5 10" x 0.18] =26.35 S/m 6. prtype semiconductor he _(_6.63%10™x3 10° 7. E, shal =| 868107 2310") os ey so sani he 62x10 3%10" _so559 4 EB (114x16x10") fee 12400 _ 12400 _ 49604 x Elev) 25 This is the maximum wavelength i, the signals having wavelength greater than this value are not detected by photodiode. 2p-n Junction Diode v__ 0s d 5x10 1 0° vm 2. (a) Forward biased (b) Forward biased (c) Reverse biased (¢) Forward biased W _ 07-05 3. Forward resistance = 8. ard Al 10x16 ava 4, Reverse resistance = 4V = + __ al 05x10 =200 10° 2 4-41 300” 100 6. The diode isin reverse biasing so current through itis zero. 7, -85205_ 4 100” 100 8. In the given condition diode is in reverse biasing so it acts ‘a8 open circuit. Hence potential difference between A and Bisby. ‘9. The upper junction diode is forward biased and middle junction diode is reverse biased. So, effective resistance of circuit =10 +10 =20 2. 40 mA 10. Total resistance in the circuit =2kQ, E=20v The current = 22. = 1 2000 ~ 100 414. In circuit A, both (p-n) junction diode act as forward biased, Hence, current flows in circuit A, Total resistance is given by 1iayt aa 2 > R=20 4 According to Ohm's law VaIR => 8x2 = I, In circuit 8, lower p-n junction diode is reverse biased. Hence, no current will flow but upper diode is forward biased, so current can flow through it ValR xd = =2A 32, Diodes D, and, are forward biased and, is reverse biased so the circuit can be redrawn as follows E = ist R— 3 E 48, Reverse biased potential for the Zener breakdown V, =Ed=10°x25x 10" =2.5,0lt 14, Voltage across Zener diode is constant 200 1 iw NV Fina 2ov| wi ha froma 15mA 45 volt 1kQ i, _@0-159V__5V__ 20 93500” 7500” 30008 7°™ ingenie ={20~15)=5mA 3 Rectifier 41. For full wave rectifier, ripple frequency =2x input frequency =2 x50 =100 Hz 2. The average value of output ina full wave rectifier = "2, 3, The average value of output direct current in a half wave rectifier (average value of current over a cycle)/2 5. Effci cy of a rectifier is given by = DE Power output ‘AC power input For full wave rectifier, DC power output te) emp AC input power =12, (r, += +: Rectifier efficiency n= 4. ‘will be maximum, ifr, is negligible as compared toR, ‘Maximum rectified efficiency = 81.2%. 4 Logic Gates 41. (A) Output of NAND gate 0 and output of NOT s 1. The ‘output of OR gate is 1 (8) Output of NOT gate is 1 and of other NOT gate is 0. The ‘output of NAND gate is 3. (C) Output of NOR gate is 0 and output of AND gate iso 2. The input of OR gate is A and (AB). Hence ¥ = A+ (AB), 3. ¥=(A-B)-C 7 (a) IfA=1,8=1,C=1,thenY =(1-1)-1=0 (o)IFA=0, 0.c=0,then 4 trom craitY =8 Thsisan output of 0 AND at 5. The output of NOR gate gives y" A+B Toe cut of NANO pte y'7=(A+B)-(A+B) =(A+B)+(A+B)=A+ ere It is a Boolean expression for NOR gate 6. NAND gate 7. AND gate The truth table ofthe circuits given ABC XHAB y=Be Z-X0¥ lmmmao “10 Pacman 10 0 1 fiver oa 7a ‘Output Z of single three input gate is that of AND gate 8. From the given waveforms, the following truth table can be madeInputs Output Time interval Ag y ont, Oho ° Tot ° 1 ° Lol 1 ° ° non 1 1 1 This truth table is equivalent to AND gate 9. (1= high, 0= low) Input to i in the sequence, 1.0,1,0 Input to8 is in the sequence, 1, 0,0, 1 Sequence is inverted by NOT gate Thus inputs to OR gate become 0, 1,0, 1 and 0,1, 1,0. Output of OR gate becomes 0, 1, 1, 1 which is drawn as. S71 40. Boolean expression of the given circuit is SA+B+A+B=A4B Level 2 Single Choice(s) Correct Questions 4. N, >N,for ptype semiconductor Ny > n, Semiconductor i ptype and n, 4, Aswe know, current density = nqv - a aod en ty ” 3s rae ian, a8 > mn 5 5. n,=8x10"/m*, n, so semiconductor isn type Also conductivity 6 elma. +a) Resistivity @) 6x10" [8x 10" x2.3 +510" x 0.01) 134. 2m 10" x16 x10" (0:36 + 0:14) =16Qm" 10. 11. 2. 13. 4. 15. 16. 17, 18, pep lat 295X107 _25; PA GA 16x10" 8 Ve? 2p osia R 25/8 25 . The temperature co-efficient of resistance of a semiconductor is always negative. . Conductor has positive temperature coefficient of resistance but semiconductor has negative temperature coefficient of resistance. 2. Germanium is semiconductor, whereas copper is conductor. For conductors, R= At Rat at Hence, when both are cooled, then resistance of copper decreases whereas that of germanium increases. E, (C)>E,(SI>E,(Ge) ‘When donor impurity (+5 valence) is added to a pure silicon (+4 valence), the +5 valence donor atom sits in the place of +44 valence silicon atom. So it has a net additional +1 ‘electronic charge. The four valence electrons form covalent bond and get fixed in the lattice. The fith electron (with ‘net ~1 electronic charge) can be approximated to revolve ‘around + 1 additional charge. The situation is like the 136 hydrogen atom for which energy is given by E e For semiconductors, V. For the case of hydrogen. the permittivity was taken as, However, i the medium has a permittivity, relative to thene=- 2S ey, For Si ¢,=12and for Itisa semiconductor, For Ge, AE, =0.72eV Forsi,AE, =11eV @ Diagram (() represents semiconductor because in semiconductor the forbidden energy gap between valence and conduction band s equal to the energy corresponding toroom temperature The donor level i found only in n-type semiconductors. The donor level ies closely below the bottom of the conduction band, In sample X no impurity level seen so itis undoped. in sample Y impurity energy level lies below the conduction bond so itis doped with fith group impurity {nsample Z, impurity energy level lies above the valence band so itis doped with third group impurity @ pn photodiode is a semiconductor diode that produces a significant current when iluminated. It is reversed biased buts operated below the breakdown voltage Energy of radiation = band gap energy E=0.1eV2. bv Dev of ya 20%16% 10" 5x10" He 6.610“ he _ 6.6210" x 3x 10° 6000 x 10° =3.31x10") po coP os pal SORIO™AINI ar 509 4 Eo mahi Stee holes in pside, they diffuse from their own side to other side. Hence depletion region produces 22. Ina p-n junction diode, electrons in conduction band on, ‘type side travel across the junction and leave the positively ionized impurity atoms unneutralised. Consequently, there is positively charged region adjacent to the junction in n-type material. On p-type side the electrons ‘hich have traversed the boundary recombine with positive holes in the valence band and form a layer of tunneutralised negatively ionised trivalent impurity atoms making a negatively charged region as shown in figure, Unneutralsed Unneuralses acceptor atom donor atom *o 0 @ oo. eee oe toro” 0 © © © @ 0 “o Elxtm Noe : 9 2°66 © @° ¢ Extant of dent ot Acceptor i negative positive Donor ‘atom "space. ‘space | alom (neutra) | charge charge (neutral) region region onp-ype on/-type sie side ‘The region around the junction is called charge depletion region or space charge region. Hence, within the depletion region, pside is negative and n-side is positive. 23. Depletion layer consists of mainly stationary ions. 24. Due to the reverse biasing the width of depletion region increases and current flowing through the diode is almost zero. In this case electric field is almost zero at the middle of the depletion region, 25. In.a p-n junction, the direction of diffusion current is from region to m-region only. 26. In forward biasing the diffusion current increases and drift ‘current remains constant so not current is due to the diffusion. In reverse biasing diffusion becomes more difficult so net current (very small) is due to the drift 27. In forward biasing both V, and x decrease 28. Under normal reverse voltage, a very little reverse current flows through a p-n junction. However, if the reverse voltage attains a high value, the junction may breakdown with sudden rise in reverse 29. 31, 32. 34, 35. 39. R, current. If reverse voltage is increased continuously, the kinetic energy of electrons (minority carriers) may become high enouigh to knock out electrons from the semiconductor atoms. At this stage breakdown of the junction occurs characterised by a sudden rise of reverse current and a sudden fall of the resistance of barrier region, ‘This may destroy the junction permanently, In forward biasing of pn junction diode width of depletion layer decreases. In intrinsic semiconductor fermi energy level is exactly in the middle of the forbidden gap | te] 6 The reverse current is identical in two diodes if the identical reverse bias is applied across the diodes. ‘Arsenic has five valence electrons, so it is a donor impurity Hence X becomes n-type semiconductor. Indium has only three outer electrons, so itis an acceptor impurity. Hence Y becomes p-type semiconductor. Also nlie.,X)is connected to positive terminal of battery and p(i-e.Y)is connected to negative terminal of battery so p-n junction is reverse biased. Positive charge (ie., holes) should move in the direction of ‘current and negative charge (i.e. electrons) should move opposite to the direction of current. In circuit 2, each p-n junction is reverse biased, some current will flow giving equal potential difference across ‘each p-n junction diode. In circuit 3, each p-n junction is forward biased, hence same current flows, giving same potential difference across p-n junctions. Total resistance = 50 + 5000 = 5050 2 50 2 1 5050101” “Forward current: 9 mA . In a forward biased p-n junction, the applied potential is ‘opposite to the junction barrier potential V,.The consequence ofthis isthe effective barrier potential reduces. Hence, the graph (d) is correctly shown. . Resistance in forward biasing, = 1002 and resistance in reverse biasing R,, = 10°Q & 1 Ry 10 Forward biased resistance AV_ 07-06 ot Al (15-5)x107 10x10 av_ (13-8) “Ml (60 40)x 10" 102 5 x 10°ov ‘gs. The current at2V is 400 mA and at 2.1 Vit is 800 mA. The * ynamic resistance in this region pad =__@A-2) ‘ai (800~400)x 107 4 a cor forward bias,|=“= 5 __ 5. 42, Forforwar R 25410" 35 48, The potential of mside is more negative than that of pside, hence diode isin forward biasing from circuit, resultant potential is 2 44, When diode is forward biased, then there ia smal voltage drop acrossit, j= ¥—V" Given, V =8 volt, V’ 8-05 22x10” = i=34ma 45. Ifiis the current in the diode and Vis voltage drop across it, then for given figure voltage equation is ix100+V=8 = sve 300° * 400 = (o01v +008 Thus the slope of :V graph = + =0.01 Rx 46. In forward biasing, resistance of pn junction diode is zero, ‘sowhole voltage appears across the resistance. 47. Vy = Ving +1R OF 4=0.7+10°R oF R=3.3/10° =3.3x 10° v0: Voltage drop across Hence,R=1/0.2=5Q ‘S. Incrcuit the upper diode junction i forward biased and the lower diode junction is reverse biased. Thus there will ‘beno conduction across lower diode junction. Now the total resistance of circuit = 100 +150 +50 =3000 Current in 1009 = = % 0028 300 5-05=10V 50. The equivalent circult can be redrawn as 2K La | From figure its clear that 14 kand 12 k& have been short-circuited. So current drawn from the battery i = °. 51. In the given circu, diode O, is reverse biased, soit will not, conduct. iodesD, and D, are forward biased, so they will conduct. The corresponding equivalent circuits as shown in the figure sa by ov The equivalent resistance of the circuit is (5+5)x20 _10%20 _ 200 5+5)+20° 10+20 30 Current through the battery, =o 7 3 52. According to the given figure Ais at lower potential w.r.t. B. hence both diodes are in reverse biasing, so equivalent Circuit can be redrawn as follows = Equivalent resistance between A andB R=B4246=160 pe A fr 80, 120 53. (iV, =-10Vandy, Diodes 0, andD, are reverse biased and, is forward biased a a }———WW—+ a it eamel cae aed Ra atov sve(ii) When v, =~5V and V, = ~10V Diode D, is reverse biased while D, and D, are forward biased R = + 4 (ii) tn this case equivalent resistance between A and is, alsoR Hence (i) = (i) < (i) 54. Consider the case when Ge and Si diodes are connected as. show in the given figure. Equivalent voltage drop across the combination Ge and Si diode =3.0V = Current Now consider the case when Ge diode connection is reversed. In this case voltage drop across the diode’s combination = 0.7V 12-07 5kQ Vy=iR=2.26mA x5k2=113V Hence charge inthe value of V,=11.7~11.3=0.4V 55, Timet=CRis known as time constant. tis time in which charge on the capacitor decreases to © times ofits inital 26 mA = Currenti charge (steady state charge) In figure (i) p-n junction diode isin forward bias, so current will flow the circuit ie. charge on the capacitor decreases and in time tit becomes Q= + (Q,); where Q, =CV e wv = qe e In figure (i) p-n junction diode is in reverse bias, s0 no current will flow through the circuit. Hence charge on capacitor will not decay and it remains same, i.e. CV after timet. 56. If Vis the voltage across the junction and/ is the circuit EVV \E current, then V +R =E or Slope of load line R 1000 57. Zener breakdown can occur in heavily doped diodes. In lightly doped diodes the necessary voltage is higher, and avalanche multiplication is then the chief process involved. values of load resistance, the curent 58, For aide ange ge butte volageacosie the zener di Tad Thus the oUtDUt VOIABE 2055 the feerdogearegunedOta6e vu reverse voltage, the minority charge carriers Fae very Mk yore tes, These by collision break down aaa vent bonds, generating more carriers. This mechanism is called Avalanche breakdown. oss load resistance 60. Voltage available acre Resistance of load, 5x10°=15kQ 10V and R, = 15002 0 4 =6.67mA 1500 61, Given circuit, Vy, Oma 1, =10-6.67 =3.33 mA 120-50 _ 50 5 10 Ig = 8225030 ng 5 10 63. When Zener diode is forward biased, it behaves like ‘ordinary diode and when reverse biased, it will be a voltage stabilizer. Also, at room temperature, the voltage across the depletion layer for silicon is about 0.6-0.7 V and for germanium is about 0.3-0.35V. Hence, statement Ais correct but statement B is incorrect. 64. At high reverse voltage, due to high electric field, the ‘minority charge carriers, while crossing the junction acquire very high velocities. These by collision breaks down the covalent bonds generating more carriers. A chain reaction is established giving rise to high current. This mechanism is called avalanche breakdown. 65. For, <0, the diode is reverse biased and hence offer infinite resistance, so circuit would be like as shown in Fig. (2) and V, = 0, sy mA 62. Fig. (2) Fig. (3)So Lome moeestoreeer seer ae See WE prnagny or pastne anc megane: Tash ees st BUS some e Saami woot ene eee oe Smee ¥ amt, are iftore nen Te RES UE maar. Sgr wll = eee see ‘poste Tat are Tagamet oo The MMe SETS [SES ear ns, oe = . . SoS HERO 7 ere wt ase rectie te cue Di votes more (© rece ed commer ne wen hte ae = See See hwo Dent Seema oer SES “Serge wee SouneSTsROeST Soar | eee Ghee ae cosets mess es tease al SEES fee AND, OR MOT ca be atmaimen 24 sing ony am A Week tne repetithe ase of NEND ant NOR sate gives ago, B WecmstdagsnstaNOD gre wmen ise mouse ‘Serer. S Ben 2s MAND =END= NOT re mum sabe of te lng game gwen 2s s Y ¥ = 2 2 2 Fe re sativa cece immer AC sigma eam 2 ° wet wae a | rors Dame BT DE tence the pat ic hee apes anc une et age sepa. Fane are me TD, ene a Ce aoa cee ‘Sioa AC sea comatose SE ne ss mene ‘Se, De reautting gate © NOT ene. FE sane etic near age peaimane timer SD cts —earver seotage = 2 1sY (© OR pee wet uma = = Tepper -orean ah wae rectiier ME ke loge gar Se Sopeen eqrenion sé C=1 (npn tal oye oe dente © tonwcart-beasing a ‘Ae lage gute 0 the Boctean expression ic A=: heer con see as erie a eagataer tat ce ter een rari. an oR OY TE RO 4a oer‘89. We can realise the combination as shown below. x RY —_} Gate-t is OR gate while gate-2is AND gate, ‘Output of OR gate, W, =X +¥ ‘Thus, output of AND gate, W = 90. FaW+x)W+Y) W-W+W-Y4W-X4X¥ =W+W-Y4W-X4X-¥ b-wewew) WLFY)+WeXE XY, WA+X)+X-¥ based) =W+xy (e(@4+x)=1andw-1=w) ‘91. We can realise the gate circuit as A> Output of gate 1. ¥, Output of gate 2,¥, Ase meC=(A4B)-C The output is ¥ =(A+B)-C The truth table of the given circuit is as shown in the table ae 1 ° - mo 0 ° ° ° “oO ° ° o ° o a) o (4-8)-(6 (4-8) =A(A+5)+8-(A+8) 5 POT kg ont —4} wie noo tly ot to ‘Output X, Yand Zchanges to0, 1,0. ‘96. Lower NOT gate inverts input to zero. NOT gate from NAND gate inverts this output to 1. Upper NAND gate converts this input 1 and input 0 to 1. Thus A=1.and8=1 become inputs of NAND gate giving final ‘output as zero. Choice +Bi.e, out of a NOR gate, ‘98. Truth table for gi sn combination is, A a x o ° 1 1 ° 1 ° 1 ° 1 1 1 ‘This comes out to be truth table of OR gate.99. Output of G, =(A+B) Output of, =A output of G, =(A+B)-(A:B) which give XOR gate. Aandé =8) which is the output of an AND gate. 101. From truth table it is clear that output is high only when both inputs are high. The Boolean expression. Which satisfies the output of this logic gate isC = A-B, which is for AND gate. 102. From real time variation of input signals, we can from truth table for A and and conclude output from NAND gate. . a Ac Inputs g 7 : wv 2K 8 0 Given in question, V,=30V Let potential at = 0V Let potential at€,V, = 10 From output, we can show real time variation of output signal as below. tA 78) 103. (d) 1104. Given, A and B are inputs and Cis output. Assume that some voltage is applied across AB. Ifthe voltage is positive, then diode corresponding to A will be ON and the other diode will be OFF = CA 4, The given circuits, If the voltage is negative then diode corresponding to 8 will ir mn be ON and the other diode will be OFF = c=8 ay [F Ly. Therefore, we can say that C= A or B. Therefore, it acts like ‘OR gate. So the correct option is (d). Be Das Previous Year's Questions Y=AB+AB=B-(A+A)=B JEE Maa Main ‘Truth table wll be 1. A diode is said to be in reverse biased when p-side is connected to less voltage than n-side. i5. Asemiconduttor starts conducting more ts the temperature Increases. It means fesistance decreases with increase in tehyeratore. So if temp Increases Its : resistty decreases 7 Aso, eae eit _as temperature increases, ‘tdecreases but n increases and n is dominant over ¢, thus reducing overall resistivity of the semiconductor 6 Ay We Power rating of zener = 1.6 W ‘Max voltage across zener = 8 V Using P = VI: for zener diode, P16 ta F a HnO2A Hence, for safe operation 2V (excess voltage of 10 V) potential drop must occur in series resistor R,. ForR,,V=2V,1=02A Using, VeIR, re? 2100 02 7, Given, forward bias resistance ()=252 Diode b, is in reverse biased, thus, = 0. Since, resistance in each branch is same Thus, fh, From KCL, 5 htletheh © ash > hee 8. A photodiode is operated in reverse bias because photocurrent is more significant in reverse blas as compared to the forward bias, 9. When Sis doped with trivalent Impurities like Boron, then a p-type semiconductor is formed. In p-type semiconductor, ‘excess number of holes are found because holes are majority carrier in p-type semiconductor. When Sis doped with pentavalent impurities (like Arsenlc), then an mtype semiconductor is formed. In retype semiconductor, excess no. of electrons are found because these are majority carrier. Thus, statement Is correct. ‘When p-type semiconductor and n-type semiconductor are fused to make a junction, a potential barrier Is produced across the junction which stops the flow of current, Thus, no current is detected by externally connected ammeter. Hence, statement Ils incorrect. reavily doped p-n junction. When an electron scllon band to valence band in forward 10, AnteD Isa his nearly equal to the energy gap transits from cond bias, itomits energy which in form of visible radiation. So, an LED cannot be used In reverse bias, ‘everse blased heavily doped pn junction fed In breakdown reglon. Zener diod tlosgned to operate in the reverse breakclown voltage continuously without keing damaged. 42, The highest energy level that an electron can occupy atthe known as the ferm! level, The absolute zero temperature Is form’ level les between the valence banc! and conduction pand because at absolute zero temperature, the electrons ‘are all in the lowest energy state. In intrinsic semiconductor, ferml level is between the two bands. in pstype, fermi level Is closer to valence band. Inmtype, fermi level Is closer to concluction band. Inmetal, fermi level is inside conduction band, Thus, correct sequence Is A=, Belll, C= 1, De IV. 11, Zener dlode Is ar diode, It Is operate 13, 2 A¥8 = A4B = output of OR gate HATE 414, We know that output of NAND gate is high only when one ‘or both input are low (zero) and low when both inputs are high (1), Thus, option (a) Is correct, 15, Circult will not work when both A and B are clos ~s +18 lt |_| So above circuit Is logic equivalent of NOT + AND = NAND. 16, pens {ip 5 ay = ls Be pad Truth table of above gate Is A 8 MW MW MW OM OX oo 4 1 0 0 0 1 0 O 4 oO 4 4 o 1 1 0 4 Oo 14 1,4 0 0 0 0 017. The ape Create amg ae ures 9 1 BB a tf -2)-6 BB) SMBS BB =D 1, Pansies sits ae Bee case ny Al egy wir by charie carers bes Tig aL SF omen Gasca. 9. Datte'e smternina tec which conduc caren Sormced accor. mill co conte tomers tie BV charenedctics Sf sahex AN ze Stowe eM. Fe creat degra tor the geen stuaitons stew seamtA) 4000 Bly 1 1 1 ae ‘Which resembles to NAND gate, so correct option is (b). 29. From the given input and output waveforms, we observe that outputY is high only when both the inputs A andB are Individually high. This is possible only in AND gate. 30, Given, logic inputs are given as (A.B)= (0,0), (0,4), (1,0) and (2,1) drawn as, ‘Output ofthe given logic circuits given as (B-(A+8)=AB+(A+B) [using de-Morgan's theorem] =(A+8)+A-B=A+B + AB ‘Now. by using truth table for above logic circuit a |B | AB| Y A 1 2 4 1 34. In igure A, V, and V, are two input voltages (either 5 V or 0 v When, Vs Both D, andD, are OFF, soV,=0, When, V,=1ie.5V,%y=0ie.0V D, Is ON but, is OFF $0, Vp=[Link] When, V,=Oi.e.0V, Yj =1ie.5V D, Is OFF and, is ON 50, Vy=1ie.5V. Similarly, when V, =V, = 1 BothD, andD, are ON So, Vg=tle.5¥. ‘We get the final truth table on the basls of inputs and the corresponding output. a eaanime:/ay, o[ofo Eee oe a[a The given circuit (A) is an OR gate. in figure, its a transistor in common emitter Configuration which gives high output at low input and low output at high input. Hence, this circuit behaves as NOT Gate. 22. Given, logic circuit can be drawn as shown below. ‘The expression for output is : a8) RTS a Soo) =A+(A+6)-B+(A+8) (Using de-Morgan's theorem, AVERY, = V=(A+A¥8)(B+A+8) Draw the truth table forthe logic circuit is shown below ‘The output, Z=A-8 = A+B (Using de-Morgan theorem) ‘This is the expression of a NOR gate. So, the logic operation carried out by the given circuit is NOR. 34, By using de-Morgan's theorem, De —D-! So, the given circuit perform AND operation.The output & Ae ‘ute the expeenssion for NAND gate, 94 ot yx consi the ver fog elect an SoBe a oolean alge wrt eA wm [> { Were, ede Ar Be aeR a veQeaee which san expression for NOR Gate, 4% According (0 te alven fue sla ave A rift ls Ey Velalal on ‘The output oF ven ctrl agra at} yA yes | Fy using concep of de Morgan avy, VoAitead ‘Truth table wiven sal bs Wine tnterval | A | |B] AB (own ypojafr (ih Pry ol} oe Wy fo} oj alo (aay Vp rtoto (ole ryofaga Herve, city eal Maslin SB. Here A ant be the ment ant ee sR AR. AR As HAR ee) SAR) AA AR AR aR SOAR DARD SAR EAR Accent he HAAR ER AA BAR AR Yoake Ae Ceori i e y err eee e oo toe 6 Lye ev ve - 9, The hate eet Os Ne a ay Uy rng Ke nanan Keane, CALE ARR ‘Wie eatin ee aban Re ERE AANA wep we ‘ "Herve, eant@et ath AQ, Cueto Ne a eH ANE ENE NE NN —_ ‘ie ye Hae one wre l x Woe (Nes At Ne ale A ant EN RR, A Vewa Wane) . Vetted) AAS Avent Ae eR tei ait, ’ * A WY eta) “ewLet! currents flowing through the circuit. -Kirchhoff’s voltage loop equation will be 10sineot -1R-3=0 > IR=V =10sinat-3 At time, t=0,V=0-3=-3V t=F.vat0s{ 22) t a T)4 =10-3=7V t=T/2toT, diode isin reverse bias. OV and T/28tsT. ‘No graph matches these cor 42. Given, =621x10" m ‘As we know that c=") x he = ese a 663x103 10" 621x107 x16x10 = 0.02014x 10? =2014 eV =2eV ti) ) 43. Consider the given figure and draw the direction of current as follows 4 20002 =100V R = 1=100=50 50 ma fl 1000 [b+ Resistance and Zener diode are in parallel, therefore voltages across them are same 25mA ll By using Kirchhoff 's current law, " leh +l, = hall Ci From Eq. (i) and (i) and, we get