BARINGO NATIONAL POLYTECHNIC MAY -
AUGUST DIGITAL ELECTRONICS LEARNING
PLAN
Scheme of Work – Digital Electronics (Module
2)
Duration: 10 Weeks
Level: Diploma
Contact Hours/Week: 2 Hours
Target Learners: Diploma in
Electrical/Electronics Engineering Students
Pre-requisite: Basic Electronics, Mathematics
Week 1–2: Number Systems
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
1 Introduction to Number Systems
Understand the different number systems
and perform conversions - Decimal, Binary,
Octal, Hexadecimal
- Conversions between systems
- Number system arithmetic - Lecture
- Class demonstrations
- Guided practice on conversions Whiteboard,
Slides, Worksheets Quiz on conversions
2 Binary Arithmetic & Complements
Perform binary arithmetic operations and
apply complements - Binary addition,
subtraction, multiplication, division
- 1’s and 2’s complement
- Signed numbers Group exercises, problem-
solving Calculator, Worksheets Assignment
(computation problems)
Week 3: Binary Codes
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
3 Binary Coding Systems Understand and
apply different binary codes - BCD, Gray Code
- ASCII, EBCDIC
- Code conversion
- Applications of codes Class discussion,
group work, examplesCoding charts, Slides
Class test
Week 4–5: Logic Gates & Boolean Algebra
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
4 Logic Gates Identify and explain the
function of logic gates- AND, OR, NOT, NAND,
NOR, XOR, XNOR
- Truth tables Lab demonstration
Digital circuit simulation Logic trainer kits,
simulation software Lab report
5 Boolean Algebra Apply Boolean laws to
simplify expressions - Laws of Boolean
Algebra
- DeMorgan’s Theorems
- Simplification using lawsPractice problems,
chalk-talk method Slides, Practice sheets
Written test
Week 6–7: Combinational Logic Design
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
6 Design of Combinational Circuits Design and
analyze basic combinational circuits - Half
Adder, Full Adder
- Multiplexers, Demultiplexers
- Encoders, Decoders Group project, circuit
simulations Logic software (e.g., Multisim),
Whiteboard Quiz + Simulation assignment
7 Karnaugh Maps (K-Maps) Use K-Maps to
simplify Boolean expressions - 2-variable to 4-
variable K-Maps
- SOP and POS forms
- Minimization techniques Guided examples,
practice sheets K-Map templates, Slides
Test on simplification
Week 8–9: Logic Families
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
8 Introduction to Logic FamiliesDifferentiate
between types of logic families - TTL, CMOS
- Characteristics: speed, power, voltage, fan-out
- Comparison Class lecture, datasheet analysis
Datasheets, Slides, ChartsAssignment on
logic family comparison
9 TTL vs CMOS ApplicationsIdentify
applications and selection criteria -
Interfacing TTL and CMOS
- Noise margin, propagation delay Discussion
+ demonstration Lab kits, Diagrams Short quiz
Week 10: Revision and Assessment
Week Topic Learning Outcomes Content
Teaching Activities Resources
Assessment
10 Course Review & Final Assessment
Demonstrate understanding of all module
content - Recap major topics
- Address difficult areas Review games, Q&A,
Mock test Past papers, Summary notes Final
Written Test + Practical/Simulation Assessment
Notes:
Practical sessions should be integrated
wherever possible (especially Weeks 4–7).