ANALOG & DIGITAL ELECTRONICS

LABORATORY MANUAL

Compiled Set of Experiments with Aim, Theory, Observation Tables,

Graphs, Sample Calculations, Results and Critical Comments
Contents
● 1. Verification of Ohm's Law
● 2. PN Junction Diode Characteristics
● 3. Zener Diode Characteristics and Voltage Regulator
● 4. Rectifiers (Half-Wave and Full-Wave)
● 5. RC Filter
● 6. Clipper and Clamper Circuits
● 7. Transistor Characteristics (CE Configuration)
● 8. Common Emitter Amplifier
● 9. Operational Amplifier - Inverting Amplifier
● 10. Non-Inverting Amplifier
● 11. Summing Amplifier
● 12. Integrator and Differentiator using Op-Amp
● 13. Logic Gates Verification
● 14. Half Adder and Full Adder using Logic Gates
● 15. Flip-Flop Circuits
Experiment 1: Verification of Ohm's Law
1. Aim
To verify Ohm's Law and to determine the resistance of a given resistor by plotting the voltage-current (V-I) characteristic.

2. Theory
Ohm's Law states that the current (I) flowing through a conductor between two points is directly proportional to the voltage
(V) across the two points, provided the physical conditions (temperature, etc.) remain constant. Mathematically, V = IR,
where R is the resistance of the conductor measured in ohms. A graph of V versus I is therefore a straight line passing
through the origin, and the slope of this line gives the value of resistance R. Any deviation from a straight line indicates a
non-ohmic behaviour, which may arise due to heating effects or non-linear circuit elements.

3. Observation Table
Sl. No. Voltage V (Volts) Current I (mA) R = V/I (kΩ)
1 1 1 1
2 2 2 1
3 3 3 1
4 4 4 1
5 5 5 1
6 6 6 1
7 7 7 1
8 8 8 1
9 9 9 1
10 10 10 1

4. Graph
The graph of Voltage (V) versus Current (I) is plotted below. The plot is a straight line passing through the origin, confirming
Ohm's Law; the slope of the line gives the resistance of the circuit.

5. Calculation
Slope of the V-I graph = ΔV/ΔI = (10 - 0) V / (10 - 0) mA = 1 kΩ
Mean value of R from table = (ΣV/I)/n = 1.0 kΩ (for the 10 readings taken)
Percentage error = |(R_measured - R_marked)/R_marked| × 100 = |(1.0 - 1.0)/1.0| × 100 = 0% (using a standard 1 kΩ
resistor)

6. Conclusion and Critical Comment

The V-I graph obtained is a straight line passing through the origin, verifying Ohm's Law. The resistance calculated from the
slope (1 kΩ) closely matches the standard/marked value of the resistor, within experimental error.
Critical Comment: Slight deviations from linearity, if observed at higher currents, may be attributed to self-heating of the
resistor (which changes its resistance) or contact/lead resistance in the circuit. Accuracy can be improved by using a digital
multimeter instead of analog meters and by keeping the applied voltage low enough to avoid heating. Loose connections and
parallax error in analog meter reading are common sources of error that should be minimized.
Experiment 2: PN Junction Diode Characteristics
1. Aim
To study the forward and reverse bias V-I characteristics of a PN junction diode and to determine its static and dynamic
resistance, and cut-in (knee) voltage.

2. Theory
A PN junction diode is formed by joining a p-type and an n-type semiconductor. In forward bias, the p-type is connected to
the positive terminal and n-type to the negative terminal of the supply; the depletion region narrows and current increases
exponentially once the applied voltage exceeds the barrier (cut-in) voltage — approximately 0.6-0.7 V for silicon and 0.2-0.3
V for germanium diodes. In reverse bias, the depletion region widens and only a very small reverse saturation current (in the
µA or nA range) flows, which remains almost constant until the breakdown voltage is reached. The static resistance is Rdc =
V/I at a given point, while the dynamic (AC) resistance is rac = ΔV/ΔI, obtained from the slope of the characteristic curve.

3. Observation Table
(a) Forward Bias
Sl. No. Forward Voltage Vf (V) Forward Current If (mA)
1 0.1 0
2 0.3 0
3 0.5 0.2
4 0.55 0.5
5 0.6 2
6 0.65 8
7 0.7 18
8 0.75 25

(b) Reverse Bias

Sl. No. Reverse Voltage Vr (V) Reverse Current Ir (µA)
1 1 2
2 2 3
3 4 4
4 6 5
5 8 6
6 10 7

4. Graph
The forward and reverse characteristics are plotted separately (different current scales are used since forward current is in mA
while reverse current is in µA).
5. Calculation
Cut-in / knee voltage (from graph, point where current rises sharply) ≈ 0.6 V (Silicon diode).
Static resistance, Rdc = Vf/If = 0.7 V / 18 mA ≈ 38.9 Ω (in forward conduction region)
Dynamic resistance, rac = ΔVf/ΔIf = (0.75-0.65) V / (25-8) mA = 0.1/17 ≈ 5.9 Ω
Reverse resistance = Vr/Ir = 10 V / 7 µA ≈ 1.43 MΩ (very high, confirming reverse blocking action)

6. Conclusion and Critical Comment

The diode conducts negligible current until the cut-in voltage (~0.6 V for Si) is reached, after which current rises
exponentially, confirming the exponential diode equation. In reverse bias, only a small, almost constant leakage current
flows, verifying the rectifying property of the PN junction.
Critical Comment: A series current-limiting resistor is essential in the forward-bias circuit to protect the diode from excessive
current beyond its rated value. Care must be taken while measuring the exponential region as small changes in voltage cause
large changes in current; a finer voltage step size near the knee gives a more accurate curve. The reverse current measured
using a general-purpose micro-ammeter may include a small error due to meter loading.
Experiment 3: Zener Diode Characteristics and Voltage Regulator
1. Aim
To study the reverse V-I characteristics of a Zener diode, to determine its breakdown (Zener) voltage, and to study its
performance as a voltage regulator (line and load regulation).

2. Theory
A Zener diode is a heavily doped PN junction diode designed to operate in the reverse breakdown region without damage.
When reverse voltage reaches the Zener voltage (Vz), the diode conducts heavily while maintaining an almost constant
voltage across it over a wide range of current. This property is exploited in voltage regulator circuits, where the Zener diode
is connected in reverse bias, in parallel with the load, through a series resistor Rs. As long as the input voltage stays above Vz
and the series resistor limits the current appropriately, the output (load) voltage remains nearly constant, providing both line
regulation (output constant despite input variation) and load regulation (output constant despite load current variation).

3. Observation Table
(a) Zener V-I Characteristics
Sl. No. Reverse Voltage V (V) Reverse Current I (mA)
1 1 0.02
2 3 0.02
3 5 0.02
4 5.4 0.5
5 5.6 5
6 5.7 15
7 5.8 30

(b) Line Regulation (Load Resistance Fixed)

Sl. No. Input Voltage Vin (V) Output Voltage Vout (V)
1 6 5.4
2 8 5.55
3 10 5.6
4 12 5.6
5 14 5.6

4. Graph
The Zener characteristic shows a sharp breakdown near Vz = 5.6 V, and the regulation graph shows Vout saturating even as
Vin increases beyond the breakdown point.
5. Calculation
Zener breakdown voltage (from graph) Vz ≈ 5.6 V
Zener dynamic resistance rz = ΔV/ΔI = (5.8-5.6) V / (30-5) mA = 0.2/25 = 8 Ω
Line regulation (%) = [(Vout(max) - Vout(min)) / Vout(nominal)] × 100 = [(5.6-5.4)/5.6] × 100 ≈ 3.57% for Vin varied from
6 V to 14 V

6. Conclusion and Critical Comment

The Zener diode exhibits a sharp, well-defined breakdown at Vz ≈ 5.6 V, and the output voltage of the regulator circuit
remains nearly constant despite changes in input voltage, confirming its use as a voltage regulator.
Critical Comment: The series resistor Rs must be chosen so that even at minimum input voltage, sufficient current flows
through the Zener to keep it in breakdown, and at maximum input voltage the Zener's maximum power rating is not
exceeded. Load regulation degrades if the load current demanded exceeds the current available after the minimum Zener
current is subtracted, so the regulator has a maximum load current limit. Temperature drift of Vz should also be accounted for
in precision applications.
Experiment 4: Rectifiers (Half-Wave and Full-Wave)
1. Aim
To study the working of half-wave and full-wave rectifier circuits and to calculate their ripple factor, rectification efficiency,
and regulation.

2. Theory
A rectifier converts alternating current (AC) into direct current (DC) using the unidirectional conduction property of diodes.
In a half-wave rectifier, a single diode conducts only during one half-cycle of the input AC, so the output is a series of pulses
with high ripple. A full-wave rectifier (using a centre-tapped transformer with two diodes, or four diodes in a bridge
configuration) conducts during both halves of the input cycle, giving a higher average DC output and lower ripple. Key
parameters are: DC output voltage Vdc, ripple factor r = (rms value of AC component)/(DC component), and rectification
efficiency η = Pdc/Pac.

3. Observation Table
Sl. No. Rectifier Type Vin (rms) (V) Vdc (Output) (V) Ripple Facto
1 Half-Wave 12 5.1 1.21
2 Full-Wave (Centre-tap) 12 10.2 0.48
3 Full-Wave (Bridge) 12 10 0.48

4. Graph
The waveforms below show the sinusoidal AC input, and the corresponding pulsating DC outputs for half-wave and full-
wave rectification.

5. Calculation
For Half-Wave Rectifier: Vdc = Vm/π, ripple factor r = 1.21 (theoretical), efficiency η(max) = 40.6% (theoretical).
For Full-Wave Rectifier: Vdc = 2Vm/π, ripple factor r = 0.48 (theoretical), efficiency η(max) = 81.2% (theoretical).
Example: With Vm = 16 V (peak) — Half-wave Vdc = 16/π = 5.09 V; Full-wave Vdc = 2×16/π = 10.19 V, matching
observed table values.

6. Conclusion and Critical Comment

The full-wave rectifier gives higher DC output voltage, lower ripple factor, and higher efficiency compared to the half-wave
rectifier, as verified experimentally and matching theoretical predictions.
Critical Comment: Diode forward voltage drop reduces the practical Vdc below the ideal value, especially significant in
bridge rectifiers where two diodes conduct in series at any instant. A filter capacitor across the load further reduces ripple but
was intentionally excluded here to observe the raw rectified waveform; its effect is studied separately in the RC filter
experiment. Transformer centre-tap full-wave rectifiers use only half the secondary winding at a time (higher PIV
requirement per diode), whereas bridge rectifiers use the full winding but need four diodes.
Experiment 5: RC Filter
1. Aim
To study the frequency response of an RC low-pass filter and to determine its cut-off frequency.

2. Theory
An RC filter uses a resistor and capacitor to attenuate certain frequencies while passing others. In a low-pass RC filter, the
output is taken across the capacitor; at low frequencies the capacitor's reactance (Xc = 1/2πfC) is high so most of the input
voltage appears across it, while at high frequencies Xc becomes small and the output voltage drops. The cut-off (or corner)
frequency, where output power falls to half (voltage falls to 1/√2 = 0.707 of maximum, i.e., -3 dB), is given by fc =
1/(2πRC). Frequencies below fc are passed with little attenuation, while frequencies above fc are progressively attenuated at
a rate of 20 dB/decade.

3. Observation Table
Sl. No. Frequency f (Hz) Output Voltage Vout (V) Gain = Vout/Vin Gain
1 50 1 1 0
2 200 0.99 0.99 -0
3 1000 0.707 0.707 -
4 5000 0.196 0.196 -14
5 10000 0.1 0.1 -2
6 50000 0.02 0.02 -3

4. Graph
The Bode plot (Gain in dB vs frequency on log scale) shows a flat response up to fc, followed by a roll-off of about -20
dB/decade.

5. Calculation
Taking R = 1.6 kΩ and C = 0.1 µF: fc = 1/(2πRC) = 1/(2π × 1600 × 0.1×10⁻⁶) ≈ 995 Hz ≈ 1 kHz, matching the observed -3
dB point in the table/graph.
At f = 5fc = 5 kHz, expected attenuation ≈ 20log10(√(1+25)) ≈ 14.15 dB, consistent with the observed table value.

6. Conclusion and Critical Comment

The RC low-pass filter passes low-frequency signals with negligible attenuation and progressively attenuates signals above
the cut-off frequency fc = 1/(2πRC), which was verified to be approximately 1 kHz for the chosen R and C values.
Critical Comment: Stray capacitance in wiring and the output impedance of the signal source can shift the effective cut-off
frequency from the theoretical value, so a buffered/low-impedance source should be used for accurate results. For a high-pass
configuration, the output would instead be taken across the resistor, giving the complementary response.
Experiment 6: Clipper and Clamper Circuits
1. Aim
To study the working of diode clipper and clamper circuits and observe their effect on an input waveform.

2. Theory
Clipper circuits use diodes to remove (clip) a portion of the input waveform above or below a reference level, without
altering the remaining part of the waveform; they are used for waveform shaping and protection against over-voltage. A
clamper circuit, on the other hand, does not change the shape of the waveform but shifts its DC level up or down, using a
diode and capacitor combination — a positive clamper shifts the waveform upward so that its negative peak coincides with
(or is close to) zero, while a negative clamper shifts it downward. Clampers are essentially DC restorers.

3. Observation Table
(a) Clipper (Bi-level clipping at ±2 V)
Sl. No. Input Voltage Vin (V) Output Voltage Vout (V)
1 -5 -2
2 -2 -2
3 0 0
4 2 2
5 5 2

(b) Positive Clamper (Vm = 5V input)

Sl. No. Input Peak (V) Output Positive Peak (V) Output Negative P
1 5 9.8 -0.2
2 5 9.8 -0.2

4. Graph
The input sine wave, clipped output (flattened beyond ±2 V), and the positive-clamped output (shifted upward with the same
shape) are shown below.

5. Calculation
Clipping levels are set by the reference (bias) voltages of the diodes; here clipping occurs symmetrically at approximately ±
(Vref + Vdiode) = ±(1.4 + 0.6) ≈ ±2 V, matching observation.
For the clamper, ideal DC shift = Vm = 5 V (neglecting diode drop); with a practical Si diode drop of ~0.2 V, output ranges
from about -0.2 V to +9.8 V for a 5 V-amplitude input, matching the observed table.

6. Conclusion and Critical Comment

The clipper circuit successfully removed portions of the input waveform beyond the set reference levels, while the clamper
circuit shifted the entire waveform vertically without distorting its shape, confirming the expected theoretical behaviour.
Critical Comment: The capacitor in a clamper circuit must be large enough that its reactance is negligible at the signal
frequency, otherwise the capacitor cannot hold its charge between cycles and the clamping action degrades (waveform
droop). Diode forward drop introduces a small deviation from the ideal clipping/clamping levels, which should be accounted
for when precise levels are required.
Experiment 7: Transistor Characteristics (CE Configuration)
1. Aim
To study the input and output characteristics of an NPN transistor in Common Emitter (CE) configuration and to determine
its h-parameters (hie, hfe, hoe).

2. Theory
In the Common Emitter configuration, the emitter terminal is common to both the input (base-emitter) and output (collector-
emitter) circuits. The input characteristic is a plot of base current (Ib) versus base-emitter voltage (Vbe) at a constant
collector-emitter voltage (Vce), and resembles a forward diode characteristic. The output characteristic is a plot of collector
current (Ic) versus Vce for different fixed values of Ib; it shows a steep rise (saturation region) followed by a nearly flat
region (active region) where Ic is controlled almost entirely by Ib, and finally the breakdown region at high Vce. From these
curves, important small-signal parameters are extracted: input resistance hie = ΔVbe/ΔIb, output resistance hoe = ΔIc/ΔVce,
and current gain hfe = ΔIc/ΔIb (in the active region).

3. Observation Table
(a) Input Characteristics (Vce = 5V constant)
Sl. No. Vbe (V) Ib (µA)
1 0.5 0
2 0.55 2
3 0.6 10
4 0.65 30
5 0.7 60
6 0.75 95

(b) Output Characteristics (Ib = 20 µA and 40 µA)

Sl. No. Vce (V) Ic at Ib=20µA (mA) Ic at Ib=40µA (mA)
1 0.5 1.6 3.3
2 1 1.9 3.9
3 2 2 3.98
4 4 2 4
5 6 2 4
6 8 2 4
7 10 2 4

4. Graph
5. Calculation
hie = ΔVbe/ΔIb (at Vce=5V) = (0.70-0.65)/(60-30)µA = 0.05V/30µA ≈ 1.67 kΩ
hfe = ΔIc/ΔIb (in active region, Vce=4V) = (4.0-2.0) mA / (40-20) µA = 2mA/20µA = 100
hoe = ΔIc/ΔVce (at Ib=40µA, between Vce=6V and 10V) = (4.0-4.0)/(10-6) ≈ 0 (very high output resistance, ideal flat
region)

6. Conclusion and Critical Comment

The input characteristic resembles a forward-biased diode curve, and the output characteristic shows distinct cut-off, active,
and saturation regions, with Ic remaining nearly constant with Vce in the active region for a fixed Ib — confirming transistor
action as a current-controlled current source. A current gain (hfe/β) of approximately 100 was obtained.
Critical Comment: Self-heating at higher Ic can cause a slight upward slope in the output characteristic (finite hoe) rather
than a perfectly flat curve, which is why real curves are not perfectly horizontal. Care must be taken not to exceed the
maximum power dissipation (Pd = Vce × Ic) rating of the transistor while taking readings at high Vce and Ic simultaneously.
Experiment 8: Common Emitter Amplifier
1. Aim
To study the frequency response of a single-stage RC-coupled Common Emitter amplifier and to determine its voltage gain,
and lower and upper cut-off frequencies (bandwidth).

2. Theory
A Common Emitter amplifier uses a transistor biased in the active region (typically using voltage-divider bias for stability) to
amplify an AC input signal applied at the base, with the amplified, phase-inverted (180° out of phase) output taken at the
collector. Coupling capacitors block DC while passing the AC signal between stages, and an emitter bypass capacitor
prevents gain loss due to negative feedback at the operating frequency. The voltage gain in the mid-frequency range is
approximately Av = -gm×(Rc||RL), and remains essentially constant over the mid-band. At low frequencies, gain falls due to
the increasing reactance of coupling/bypass capacitors; at high frequencies, gain falls due to the transistor's internal junction
capacitances and Miller effect. The bandwidth is defined as the frequency range between the lower cut-off frequency (fL) and
upper cut-off frequency (fH), both measured at the -3 dB (0.707 × maximum gain) points.

3. Observation Table
Sl. No. Frequency f (Hz) Output Voltage Vout (V) Gain Av = Vout/Vin Gain (d
1 20 0.15 15 23.5
2 100 0.65 65 36.3
3 1000 1 100 40
4 10000 1 100 40
5 50000 0.9 90 39.1
6 100000 0.6 60 35.6
7 500000 0.15 15 23.5

4. Graph
The Bode plot shows a flat mid-band gain of about 40 dB, with roll-off at both low and high frequency ends, giving the
characteristic bandpass response of an RC-coupled amplifier.

5. Calculation
Mid-band voltage gain, Av(mid) = 100 (= 40 dB), taken with Vin = 10 mV giving Vout = 1.0 V.
Lower cut-off frequency fL (from graph, at gain = 70.7) ≈ 100 Hz; Upper cut-off frequency fH ≈ 60 kHz (approx., read at -
3dB points).
Bandwidth = fH - fL ≈ 60,000 - 100 = 59,900 Hz ≈ 59.9 kHz

6. Conclusion and Critical Comment

The amplifier exhibits a well-defined mid-band gain with roll-off at both frequency extremes, giving the characteristic RC-
coupled amplifier response, and the measured bandwidth agrees reasonably with the theoretical estimate based on component
values.
Critical Comment: Improper biasing (Q-point not centred in the active region) leads to clipping/distortion of the output for
larger input signals, so the DC operating point should always be verified with a multimeter before applying the AC signal.
Stray capacitance from the oscilloscope probe can affect the measured high-frequency roll-off, so low-capacitance probes are
preferred for accurate fH measurement.
Experiment 9: Operational Amplifier - Inverting Amplifier
1. Aim
To design and study an inverting amplifier using an Op-Amp (IC 741) and to verify its theoretical gain.

2. Theory
In the inverting amplifier configuration, the input signal is applied through an input resistor (Rin) to the inverting (-) terminal
of the Op-Amp, while the non-inverting (+) terminal is grounded. A feedback resistor (Rf) connects the output back to the
inverting terminal. Using the virtual short concept (V- ≈ V+ = 0) and the fact that no current flows into the Op-Amp's input
terminals (ideal Op-Amp assumptions), the closed-loop voltage gain is given by Av = -Rf/Rin. The negative sign indicates
that the output is 180° out of phase with the input. This configuration provides a stable, predictable gain determined purely by
external resistors, largely independent of the Op-Amp's open-loop gain.

3. Observation Table
(Rin = 1 kΩ, Rf = 10 kΉ, theoretical gain = -10)
Sl. No. Input Vin (V) Output Vout (V) (Practical) Gain (Practical) Gain (Theor
1 0.2 -1.98 -9.9 -10
2 0.4 -3.96 -9.9 -10
3 0.6 -5.95 -9.92 -10
4 0.8 -7.9 -9.88 -10
5 1 -9.85 -9.85 -10

4. Graph
The Vin-Vout plot is a straight line with a negative slope, whose magnitude gives the practical gain of the amplifier.

5. Calculation
Theoretical gain, Av = -Rf/Rin = -10kΩ/1kΩ = -10
Practical gain (from table, average) = -(9.9+9.9+9.92+9.88+9.85)/5 ≈ -9.89
Percentage error = |(-10) - (-9.89)| / |-10| × 100 ≈ 1.1%

6. Conclusion and Critical Comment

The practical gain obtained (≈ -9.89) closely matches the theoretical gain (-10) calculated from the resistor ratio, verifying the
inverting amplifier equation Av = -Rf/Rin, within a small experimental error of about 1%.
Critical Comment: The small deviation from the ideal gain is attributable to the finite open-loop gain of the practical Op-
Amp (IC 741), input bias current, and resistor tolerances (typically ±5%). Care should be taken to keep the output within the
supply rail limits (typically ±12 V to ±15 V) to avoid saturation/clipping of the output waveform, which would otherwise
distort the measured gain at larger input amplitudes.
Experiment 10: Non-Inverting Amplifier
1. Aim
To design and study a non-inverting amplifier using an Op-Amp (IC 741) and to verify its theoretical gain.

2. Theory
In the non-inverting amplifier configuration, the input signal is applied directly to the non-inverting (+) terminal of the Op-
Amp, while the inverting (-) terminal is connected to a voltage divider formed by resistors Rf (feedback) and R1 (to ground).
By the virtual short concept, the voltage at the inverting terminal equals the input voltage at the non-inverting terminal.
Applying the voltage divider relation and the ideal Op-Amp condition of zero input current, the closed-loop gain is derived as
Av = 1 + (Rf/R1). Unlike the inverting amplifier, the output here is in phase with the input, and the gain is always greater
than or equal to 1. This configuration also offers very high input impedance, since the input is applied directly to the Op-
Amp's non-inverting terminal.

3. Observation Table
(R1 = 1 kΩ, Rf = 10 kΩ, theoretical gain = 11)
Sl. No. Input Vin (V) Output Vout (V) (Practical) Gain (Practical) Gain (Theor
1 0.2 2.18 10.9 11
2 0.4 4.36 10.9 11
3 0.6 6.54 10.9 11
4 0.8 8.72 10.9 11
5 1 10.85 10.85 11

4. Graph
The Vin-Vout plot is a straight line with a positive slope, whose value gives the practical gain of the amplifier.

5. Calculation
Theoretical gain, Av = 1 + (Rf/R1) = 1 + (10kΩ/1kΩ) = 11
Practical gain (average from table) ≈ (10.9+10.9+10.9+10.9+10.85)/5 ≈ 10.89
Percentage error = |11 - 10.89|/11 × 100 ≈ 1.0%

6. Conclusion and Critical Comment

The practical gain obtained (≈10.89) closely agrees with the theoretical gain (11) calculated from Av = 1 + Rf/R1, confirming
the non-inverting amplifier's operation, and the output was verified to be in phase with the input.
Critical Comment: Because the minimum possible gain of this configuration is unity (when Rf = 0), it is not suitable for
attenuation, unlike the inverting amplifier. The very high input impedance of this configuration makes it useful as a
buffer/impedance transformer when Rf is shorted and R1 removed (unity-gain buffer/voltage follower), which is a special
case worth noting.
Experiment 11: Summing Amplifier
1. Aim
To design and verify the operation of an inverting summing (adder) amplifier using an Op-Amp.

2. Theory
A summing amplifier is a variation of the inverting amplifier where multiple input signals are applied through separate input
resistors to a common inverting terminal (virtual ground). Since no current flows into the Op-Amp input and the inverting
terminal is held at virtual ground, the total current flowing into the feedback resistor equals the sum of the currents from each
input branch. This yields the output relation Vout = -Rf(V1/R1 + V2/R2 + V3/R3 + ...). When all input resistors are equal
(R1=R2=R3=R), the output simplifies to Vout = -(Rf/R)(V1+V2+V3), giving a scaled, inverted sum of the input voltages.
This circuit is widely used in audio mixers and analog computing applications.

3. Observation Table
(R1 = R2 = 10 kΩ, Rf = 10 kΩ, theoretical Vout = -(V1+V2))
Sl. No. V1 (V) V2 (V) Theoretical Vout (V) Practical Vout (V)
1 0.5 0.5 -1 -0.98
2 1 0.5 -1.5 -1.47
3 1 1 -2 -1.96
4 1.5 1 -2.5 -2.44
5 2 1 -3 -2.93

4. Graph
(Not plotted separately — the linear summation relation is verified directly through the observation table above, since the
output depends on two independent input variables.)

5. Calculation
For V1 = 1.5V, V2 = 1.0V: Theoretical Vout = -(Rf/R1)V1 - (Rf/R2)V2 = -(1×1.5) - (1×1.0) = -2.5 V
Percentage error for this reading = |(-2.5)-(-2.44)|/2.5 × 100 = 2.4%

6. Conclusion and Critical Comment

The practical output voltages closely match the theoretical sum (with inversion and unity scaling since R1=R2=Rf),
confirming that the circuit correctly performs analog addition of the two input voltages.
Critical Comment: The accuracy of summation depends heavily on the matching of resistor values; any mismatch between
R1, R2, and Rf introduces unequal weighting of the inputs. To build a scaling adder (weighted sum), different resistor ratios
can be deliberately chosen for R1, R2, etc. A non-inverting summer can also be built but requires additional resistor-network
derivation and is less commonly used.
Experiment 12: Integrator and Differentiator using Op-Amp
1. Aim
To design Op-Amp based integrator and differentiator circuits and to study their output response for a square wave input.

2. Theory
An Op-Amp integrator replaces the feedback resistor of an inverting amplifier with a capacitor. The virtual ground at the
inverting input forces the input resistor current to be entirely diverted into the capacitor, and the output becomes proportional
to the negative integral of the input voltage over time: Vout = -(1/RC)∫Vin dt. For a square wave input, this produces a
triangular wave output. Conversely, an Op-Amp differentiator uses a capacitor at the input and a resistor in the feedback
path; the output is proportional to the negative rate of change (derivative) of the input: Vout = -RC(dVin/dt). For a square
wave input (which changes abruptly), the ideal differentiator output consists of sharp spikes (impulses) at each transition.

3. Observation Table
(a) Integrator (Square wave input, Vp-p = 2V, f = 1 kHz, R=10kΩ, C=0.01µF)
Sl. No. Time (ms) Input Vin (V) Output Vout (V) (Triangular)
1 0 1 0
2 0.25 1 -2.5
3 0.5 -1 -5
4 0.75 -1 -2.5
5 1 1 0

(b) Differentiator (Square wave input, same parameters, R=10kΩ, C=0.01µF)

Sl. No. Time (ms) Input Vin (V) Output Vout (V) (Spikes)
1 0 1 0
2 0.5 -1 -8
3 0.5001 -1 0
4 1 1 8
5 1.0001 1 0

4. Graph
5. Calculation
Integrator: RC = 10kΩ × 0.01µF = 100 µs. For a square wave of amplitude ±1V and half-period T/2 = 0.5 ms, change in
output ΔVout = (1/RC)×Vin×(T/2) = (1/100µs)×1V×500µs = 5 V (peak-to-peak triangular swing), consistent with the
observation table.
Differentiator: RC = 100 µs. Ideally output spike amplitude is very large (theoretically infinite for an instantaneous edge);
practically limited by the Op-Amp's slew rate and supply rails, observed here as ≈ ±8 V spikes limited by supply.

6. Conclusion and Critical Comment

The integrator successfully converted the square wave input into a triangular wave output, and the differentiator produced
sharp positive/negative spikes at each transition of the square wave, both matching the expected mathematical operations of
integration and differentiation.
Critical Comment: A practical differentiator is prone to high-frequency noise amplification and instability because its gain
increases with frequency (20 dB/decade); a small resistor is usually added in series with the input capacitor to limit high-
frequency gain and stabilize the circuit. Similarly, a practical integrator requires a large resistor in parallel with the feedback
capacitor to prevent output drift/saturation caused by the Op-Amp's input bias current charging the capacitor over time.
Experiment 13: Logic Gates Verification
1. Aim
To study and verify the truth tables of basic logic gates: AND, OR, NOT, NAND, NOR, XOR, and XNOR, using standard
TTL/CMOS ICs.

2. Theory
Logic gates are the fundamental building blocks of digital electronics, each implementing a basic Boolean operation on one
or more binary inputs to produce a single binary output. The AND gate outputs 1 only when all inputs are 1 (Y = A.B). The
OR gate outputs 1 when at least one input is 1 (Y = A+B). The NOT gate (inverter) outputs the complement of its single
input (Y = A'). NAND and NOR are the complements of AND and OR respectively, and are known as universal gates
because any Boolean function can be implemented using only NAND gates (or only NOR gates). The XOR (Exclusive-OR)
gate outputs 1 when the inputs differ (Y = A⊕B), and XNOR outputs 1 when the inputs are the same.

3. Observation Table (Truth Tables)

A B AND (A.B) OR (A+B) NAND NOR XOR XNOR
0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1

(NOT Gate)
A NOT (A')
0 1
1 0

4. Graph
Logic gate verification is tabular in nature (Boolean truth tables); no continuous graph is applicable here. Timing diagrams
may optionally be drawn showing input/output pulse levels over time to visually confirm gate behaviour.

5. Calculation
No numerical calculation is required; verification is done by comparing the practically obtained output (LED indicator ON =
logic 1, OFF = logic 0) for each input combination against the theoretical truth table given above.

6. Conclusion and Critical Comment

The practical outputs obtained for all input combinations, for each of the seven gates tested, matched exactly with their
respective theoretical truth tables, verifying correct operation of the ICs used.
Critical Comment: Unused input pins of CMOS gates must never be left floating, as this can cause unpredictable output or
increased power consumption; they should be tied to a fixed logic level (Vcc or ground) as appropriate. IC pin numbering
and orientation (notch/dot indicating pin 1) must be verified carefully before wiring to avoid damaging the IC due to reversed
power supply connections.
Experiment 14: Half Adder and Full Adder using Logic Gates
1. Aim
To design, construct, and verify the truth tables of a Half Adder and a Full Adder circuit using basic logic gates.

2. Theory
A Half Adder adds two single binary digits (A and B) and produces two outputs: Sum (S) and Carry (C). It can be
implemented using an XOR gate for the Sum (S = A⊕B) and an AND gate for the Carry (C = A.B). However, the half adder
cannot accept a carry input from a previous addition stage, which limits it to adding only the least significant bit of a multi-bit
number. A Full Adder overcomes this limitation by accepting three inputs: A, B, and a Carry-in (Cin) from the previous
stage, producing Sum and Carry-out (Cout). It can be built using two half adders and an OR gate, with Sum = A ⊕B ⊕Cin and
Cout = A.B + Cin.(A⊕B). Cascading full adders allows the addition of multi-bit binary numbers (ripple-carry adder).

3. Observation Table
(a) Half Adder
A B Sum (S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

(b) Full Adder

A B Cin Sum (S) Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

4. Graph
Not applicable — verification is tabular (truth table based); a logic circuit diagram (XOR/AND gates for half adder; two half
adders + OR gate for full adder) is drawn separately in the practical record.

5. Calculation
Boolean verification: For the Full Adder, taking A=1, B=1, Cin=1: Sum = A⊕B⊕Cin = 1⊕1⊕1 = 1; Cout = AB +
Cin(A⊕B) = (1.1) + 1.(1⊕1) = 1 + 0 = 1, matching row 8 of the observed truth table.

6. Conclusion and Critical Comment

The Half Adder and Full Adder circuits were constructed using basic gates and their outputs, verified for all possible input
combinations, matched the expected truth tables exactly, confirming correct binary addition logic including carry
propagation.
Critical Comment: The full adder is a more versatile and practically useful building block since real arithmetic circuits (like
an n-bit ripple-carry adder) require carry propagation between stages, which the half adder alone cannot provide. A drawback
of the ripple-carry approach (cascaded full adders) is propagation delay, since each stage must wait for the carry from the
previous stage — this is addressed in high-speed designs using carry-look-ahead adders.
Experiment 15: Flip-Flop Circuits
1. Aim
To study the construction and truth tables of SR, D, JK, and T flip-flops, and to observe the toggling action of a JK flip-flop
connected in toggle mode.

2. Theory
A flip-flop is a basic memory element in sequential digital circuits, capable of storing one bit of binary information, with its
output changing only at specific triggering edges/levels of a clock signal. The SR (Set-Reset) flip-flop has two inputs, S and
R; setting S=1,R=0 sets the output Q=1, while S=0,R=1 resets Q=0, and S=R=1 is an invalid (forbidden) state for the basic
NAND/NOR latch implementation. The D (Data/Delay) flip-flop has a single data input D, and simply transfers D to Q at the
clock edge, avoiding the ambiguous SR state. The JK flip-flop resolves the SR ambiguity: when J=K=1, the output toggles
(changes state) on every clock pulse, making it the most versatile flip-flop. The T (Toggle) flip-flop, derived from a JK flip-
flop by tying J and K together, toggles its output whenever T=1 at the clock edge, and holds its state when T=0. Flip-flops are
the fundamental building blocks of registers, counters, and other sequential circuits.

3. Observation Table
(a) SR Flip-Flop
S R Q (next state)
0 0 Q (no change)
0 1 0
1 0 1
1 1 Invalid

(b) D Flip-Flop
D Q (next state)
0 0
1 1

(c) JK Flip-Flop
J K Q (next state)
0 0 Q (no change)
0 1 0
1 0 1
1 1 Toggle (Q')

(d) T Flip-Flop
T Q (next state)
0 Q (no change)
1 Toggle (Q')

4. Graph
The timing diagram below shows the JK flip-flop (with J=K=1) toggling its output Q at every rising edge of the clock,
verifying its toggle-mode operation.
5. Calculation
No numerical calculation applies; verification is based on comparing observed output transitions (via LED indicators, one
clock pulse at a time) against the theoretical characteristic table/timing diagram for each flip-flop type.
For the JK flip-flop in toggle mode (J=K=1), toggle frequency of Q = (clock frequency)/2, since Q changes state once every
full clock cycle — this relation is exploited in binary (÷2) counter design.

6. Conclusion and Critical Comment

All four flip-flop types (SR, D, JK, T) were verified against their respective truth/characteristic tables, and the JK flip-flop
connected in toggle mode was observed to divide the input clock frequency by two, confirming its use as the basic building
block of binary counters.
Critical Comment: The SR latch's invalid state (S=R=1) must be avoided in practical circuits, which is why the JK flip-flop
(with a feedback-based toggle resolution) is generally preferred over the basic SR flip-flop in synchronous design. Care must
be taken to identify whether a given flip-flop IC is edge-triggered or level-triggered (transparent latch), as feeding a level-
triggered device with a slow-changing clock can cause multiple unintended transitions (race-around condition), which is
specifically why the master-slave JK flip-flop configuration was developed.