VINUNIVERSITY
COLLEGE OF ENGINEERING Semester: Spring AY 2024 - 2025
AND COMPUTER SCIENCE
MIDTERM EXAMINATION
Student’s Full Name:
Student’s ID:
Course name: Digital Logic and Computer Organization
Course code: ELEC3010
Time allowed: 110 minutes (including 10 minutes reading time)
Number of questions: 7
Total number of
4 pages, including exam cover sheet
pages:
Instructor’s name: Pham Ngoc Nam
Exam code: ELEC3010_S24_25_Mid
INSTRUCTIONSk
PLEASE READ CAREFULLY BEFORE PROCEEDING
Please turn off and stow away all electronic devices including smart watches. You may
not use them for any reason during the exam. Do not bring them with you if you leave the
room temporarily. You may use a calculator.
This is a closed book and notes examination. You may use one A4-page cheat sheet.
There are 7 questions. Make sure you have the whole exam. You have 100 minutes to
complete 100 points. Use your time accordingly.
Examination materials must not be removed from the examination room.
It is a violation of the Academic Integrity Code to look at any exam other than your own,
to look at any other reference material, or to otherwise give or receive unauthorized help.
Do not commence writing until you are instructed to do so.
If any points are not clear, you have 15 minutes at the beginning of the exam to ask the
instructors.
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1. Question 1 (10 points):
Given the following variable declarations in C.
long int x = -115;
double y = -17.125;
a. [6 points] How are x and y stored in the computer memory when the code is
running?
b. [4 points] Why is Two’s complement representation used in almost all digital and
computer systems instead of Sign-Magnitude representation?
Hint: IEEE-754 format for double-precision
64 Bits: 1 sign bit, 11 exponent bits, 52 fraction bits
1 sign bit: 0 positive, 1 negative
11-bit biased exponent= exponent + 1023
2. Question 2 (20 points):
Given the following circuit:
a. [10 points] Derive the truth table of the circuit and design the corresponding logic
circuit with a minimum number of AND, OR, NOT gates.
b. [10 points] Describe the structure of the circuit using Verilog assuming that the
components in this circuit have been described in separate modules.
3. Question 3 (10 points):
A checker has a 4-bit input A and a 1-bit output F. F=1 when A is an even number
and the total number of bits 1 in A is smaller than the number of bits 0 in A, and
F=0 when A is an odd number and the total number of bits 1 in A is bigger than
the number of bits 0 in A. For example, if A=0100 then F=1, if A=1101 then F=0.
Design the checker using basic logic gates.
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4. Question 4 (10 points):
a. [5 points] Implement the following function using a 3:8 decoder and a multiple
input OR gate:
F= ABC’ + BC + B’
b. [5 points] Implement the following function using a 4:1 Multiplexer and a NOT
gate (if needed):
F= A’BC + AB’C + C’
5. Question 5 (20 points):
A digital lock has two pushbutton inputs X1, X2, and one output Unlock. Unlock =
1 whenever there is a combination of X2 being pushed, followed by X1 being
pushed, followed by X2 being pushed (X2, X1, X2). When Unlock =1, the lock
should be unlocked and return to the initial state. The lock can be reset from any
state by pushing both X1 and X2.
Draw a Moore FSM of the controller of the lock and implement the FSM using
basic logic gates and a minimum number of DFFs.
6. Question 6 (20 points):
Given the following circuit:
a. [15 points] Analyze the circuit to find the FSM.
b. [5 points] Calculate the maximum clock frequency of the circuit given the
parameters of the FFs in the table below. The propagation delays of the OR gate
and XOR gate are 3ns and 5ns, respectively.
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7. Question 7 (10 points):
Describe the following FSM using Verilog with a synchronous active Low Reset
signal.
GOOD LUCK!