DIGITAL LOGIC
AND MICROPROCESSOR
[Link]
Assistant Professor(Senior Grade)
School of Electromics
VIT, Chennai
REGISTER
It is a group of flip-flops suitable for holding binary information.
Each flip-flop is a binary cell capable of storing one bit of information.
n-bit register has group of n flip-flops and storing binary information
containing n bits.
In addition, it have combinational gates that perform data-processing
tasks.
Gates in register control when and how the information transferred into
register
REGISTER
Various types of registers are available in MSI circuits.
simplest possible register is one that contains no external gates, and is
constructed of only flip-flops.
4 bit Register
SHIFT REGISTER
Shifting its binary information either to right or left is called a shift register
Chain of flip-flop connected in cascade
Output of one flip-flop connected to input of next flip-flop
All flip-flops receive a common clock pulse causes the shift from one stage to
the next
Two methods of shifting the data
- Serial shifting – shift one bit at a time for each clock pulse
- Parallel shifting- all data shifted simultaneously during single
clock pulse
TYPES OF SHIFT REGISTER
Serial Serial
Serial
data input data output data input n bit Serial-in Parallel-out (SIPO)
n bit
Parallel
Serial-in serial-out(SISO) data output
Parallel Parallel
data input data input
Serial
data output
n bit n bit Parallel-in parallel-out(PIPO)
Parallel-in serial-out(PISO) Parallel
data output
SERIAL-IN SERIAL-OUT (SISO)
Serial
Serial data output
data input
D QA D QB D QC D QD
D Q D
CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0 Operation of SISO
3 1 1 1 0
4 1 1 1 1
OPERATION OF SISO
This type of shift register, accepts data serially, (one bit at a time on single
input line and also produce single output serially)
Data shifted may be left using shift left register and right using shift right
Register
Clock pulse applied to all flip-flop simultaneously
Bit stored in first FF is transferred to second FF and from second FF to
third FF and so on.
Example consider 4-bit binary number 1111 is to stored in register
Initially when no clock pulse is applied, QA=0, QB=0, QC=0, QD=0
When first clock pulse is applied, 1 is applied to D, and this 1 shifted to FF1
and all other FFs store their respective bits at D inputs
After first clock pulse, QA=1, QB=0, QC=0, QD=0
Similarly shift the bits for other clock pulses by applying other binary inputs
Finally it completes serial entry of 1111.
SERIAL-IN PARALLEL-OUT (SIPO)
Q3 Q2 Q1 Q0
Serial Parallel
data input data output
D D D D
D Q D
CLK Q3 Q2 Q1 Q0
0 0 0 0 0
Once the data bit are stored, each
bit appears on its respective output
1 1 0 0 0
simultaneously, rather than bit by bit
2 1 1 0 0 basis as with serial output.
3 1 1 1 0
4 1 1 1 1
Operation of SIPO
PARALLEL-IN PARALLEL-OUT (SIPO)
D3 D2 D1 D0
D D D D
D Q D
Q3 Q1 Q0
Q2
OPERATION OF PIPO
Data entered into register and taken out from register are in parallel form
When clock pulse is applied, D inputs are shifted into Q outputs of flip-flop.
Register stores the data and is available instantly for shifting out in parallel
form
PARALLEL-IN SERIAL-OUT (PISO)
SHIFT/ D2 D1 D0
4 1 5 2 6 3
D3
Q0
D D D D
Q3 Q2 Q1
D Q D
OPERATION OF PISO
Data bits are entered simultaneously on parallel lines into all flip-flop but d
ata are shifted out serially.
D3, D2, D1, D0 are parallel data input lines and is control input
Control input allow the data to be entered in parallel form and shifted
out serially
When is low, it allow AND gates 1 , 2 and 3 are enabled, allow
data at parallel inputs.
When is high, AND gates 4,5,6 are enabled, allowing the data bits
to shift from one stage to next after clock pulse applied.
OR gates allow either normal shifting operating or parallel data entry opera
tion depends on which AND gates are enabled by
UNIVERSAL SHIFT REGISTER
THANK YOU