DIGITAL LOGIC
AND MICROPROCESSOR
[Link]
Assistant Professor(Senior Grade)
School of Electronics
VIT, Chennai
MODULE-3
SEQUENTIAL LOGIC CIRCUITS
INTRODUCTION
Block diagram of a sequential circuit
Output at any instant of time depend not only on the present inputs but
also on the past outputs are called sequential circuit.
Output are fed back to the input side
It consist of combinational circuit to which memory element connected to
form feedback path
TYPES OF SEQUENTIAL CIRCUITS
Synchronous- knowledge of its signals
at discrete instants of time
Asynchronous-depends upon the input
signals at any instant of time
Synchronous sequential circuit
Most frequently encountered in practice
Synchronization is achieved by a timing
device called a clock generator (Clk), provides Clocked sequential circuit
clock signal
use clock pulses to control storage elements ar
e called clocked sequential circuits
feasible because it manifest stability problems
FLIP FLOPS
Memory elements used in clocked sequential circuits are called flip-flops.
Store one bit of information
A flip-flop circuit maintain a binary state until directed by an input signal
to switch states
SR FLIP FLOP WITH NOR GATES
S R Q Q’
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
Q′
1 1 0 0
Truth Table
Flip-flop has two outputs, Q and Q′, and two inputs, set and reset.
Flipflop is sometimes called a direct-coupled SR flip-flop or SR latch.
OPERATION
In general NOR gate, output = 0 if any input is 1;output = 1 only when
all inputs are 0.
S = 0, R = 0; normal resting state of the circuit and it has no effect of the
output states.
S = 1, R = 0; this will set Q to 1, it works in SET mode operation.
Q and Q’ will remain in prior state. It works in HOLD (no change) mode
operation.
S = 0, R = 1; this will reset Q to 0, it works in RESET mode operation.
S = 1, R = 1; Q & Q’ = 0. This condition is undefined and avoided
SR FLIP FLOP WITH NAND GATES
S R Q Q’
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
Q′
0 0 1 1
Truth Table
OPERATION
In general NOR gate, output = 0 if any input is 1;output = 1 only when
all inputs are 0.
S = 1, R = 1; normal resting state of the circuit and it has no effect on
output states.
S = 1, R = 0; this will set Q to 1, it works in SET mode operation.
Q and Q’ will remain in prior state. It works in HOLD (no change) mode
operation.
S = 0, R = 1; this will reset Q to 0, it works in RESET mode operation.
S = 0, R = 0; Q & Q’ = 1. This condition is undefined and avoided
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