EVALUATION KIT AVAILABLE

MAX2769B

Universal GPS Receiver

General Description Features

The MAX2769B is a next-generation Global Navigation S AEC-Q100 Automotive Qualified
Satellite System (GNSS) receiver covering GPS, GLONASS, S GPS/GLONASS/Galileo/Compass Systems
Galileo, and Compass navigation satellite systems on
a single chip. This single-conversion GNSS receiver is S 40pF Output Clock Drive Capability
designed to provide high performance for industrial and S No External IF SAW or Discrete Filters Required
automotive applications. S Programmable IF Frequency
Designed on Maxim’s advanced, low-power SiGe BiCMOS S Fractional-N Synthesizer with Integrated VCO
process technology, the MAX2769B offers the highest Supports Wide Range of Reference Frequencies
performance and integration at a low cost. Incorporated
S Dual-Input Uncommitted LNA for Separate Passive
on the chip is the complete receiver chain, including a
and Active Antenna Inputs
dual-input LNA and mixer, followed by the image-rejected
filter, PGA, VCO, fractional-N frequency synthesizer, S 1.4dB Cascade Noise Figure
crystal oscillator, and a multibit ADC. The total cascaded S Integrated Crystal Oscillator
noise figure of this receiver is as low as 1.4dB.
S Integrated Active Antenna Sensor
The MAX2769B completely eliminates the need for exter-
S 2.7V to 3.3V Supply Voltage
nal IF filters by implementing on-chip monolithic filters
and requires only a few external components to form a S Small, 28-Pin, RoHS-Compliant, Thin QFN Lead-
com­plete low-cost GPS RF receiver solution. Free Package (5mm x 5mm)
The MAX2769B is the most flexible receiver on the mar-
ket. The integrated delta-sigma fractional-N frequency Ordering Information appears at end of data sheet.
synthesizer allows programming of the IF frequency
within a ±30Hz (fXTAL = 32MHz) accuracy while operat-
ing with any reference or crystal frequencies that are
Block Diagram
available in the host system. The ADC outputs CMOS
logic levels with 1 or 2 quantized bits for both I and Q
VCC_ADC

channels, or up to 3 quantized bits for the I channel. I and CLKOUT

XTAL
Q0

Q1

Q analog outputs are also available.

I1

I0

21 20 19 18 17 16 15
The MAX2769B is packaged in a 5mm x 5mm, 28-pin thin
N.C. 22 14 VCCD
QFN package with an exposed paddle.
ADC

ADC

Applications VCC_IF 23
MAX2769B
13 VCC_CP

Automotive Navigation Systems

PLL

IDLE 24 12 CPOUT

Location-Enabled Mobile Handsets FILTER

LNA2 25 11 VCC_VCO
PNDs (Personal Navigation Devices) LNA2 VCO
90

Telematics (Asset Tracking, Inventory

PGM 26 10 CS
Management)
0

INTERFACE

Marine/Avionics Navigation
3-WIRE

LNA1 27 LNA1 9 SCLK

Software GPS
Laptops and Netbooks N.C. 28
+
8 SDATA

1 2 3 4 5 6 7
ANTFLAG

LNAOUT

ANTBIAS

VCC_RF

MIXIN

LD

SHDN

For related parts and recommended products to use with this part,
refer to [Link]/[Link].

For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at [Link]. 19-5875; Rev 2; 10/12
 MAX2769B

Universal GPS Receiver

ABSOLUTE MAXIMUM RATINGS

VCC_ to Ground.....................................................-0.3V to +4.2V Operating Temperature Range........................... -40NC to +85NC
Other Pins Except LNA_, MIXIN, XTAL, and LNAOUT to Junction Temperature......................................................+150NC
Ground............................. -0.3V to +(Operating VCC_ + 0.3V) Storage Temperature Range............................. -65NC to +150NC
Maximum RF Input Power.............................................. +15dBm Lead Temperature (soldering, 10s).................................+300NC
Continuous Power Dissipation (TA = +70NC) Soldering Temperature (reflow).......................................+260NC
TQFN (derates 27mW/NC above +70NC)....................2500mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

CAUTION! ESD SENSITIVE DEVICE

DC ELECTRICAL CHARACTERISTICS
(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Supply Voltage 2.7 2.85 3.3 V
Default mode, LNA1 is active (Note 2) 18 27 31
Default mode, LNA2 is active (Note 2) 15 25 30.5 mA
Supply Current
Idle ModeK, IDLE = low, SHDN = high 5
Shutdown mode, SHDN = low 200 FA
Voltage Drop at ANTBIAS from
Sourcing 20mA at ANTBIAS 0.2 V
VCC_RF
Short-Circuit Protection Current at
ANTBIAS is shorted to ground 57 mA
ANTBIAS
Active Antenna Detection Current To assert logic-high at ANTFLAG 1.1 mA
DIGITAL INPUT AND OUTPUT
Digital Input Logic-High Measure at the SHDN pin 1.5 V
Digital Input Logic-Low Measure at the SHDN pin 0.4 V

Idle Mode is a trademark of Maxim Integrated Products, Inc.

Maxim Integrated   2

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.
 MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS*
(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

CASCADED RF PERFORMANCE
RF Frequency L1 band 1575.42 MHz
LNA1 input active, default mode (Note 3) 1.4
Noise Figure LNA2 input active, default mode (Note 3) 2.7 dB
Measured at the mixer input 10.3
Out-of-Band 3rd-Order Input
Measured at the mixer input (Note 4) -7 dBm
Intercept Point
In-Band Mixer Input Referred 1dB
Measured at the mixer input -85 dBm
Compression Point
Mixer Input Return Loss 10 dB
Image Rejection 25 dB
LO leakage -101
Spurs at LNA1 Input dBm
Reference harmonics leakage -103
Maximum Voltage Gain Measured from the mixer to the baseband analog output 91 96 103 dB
Variable Gain Range 55 59 dB
FILTER RESPONSE
FBW = 00 4
Passband Center Frequency FBW = 10 4 MHz
FBW = 01 9.27
FBW = 00 2.5
Passband 3dB Bandwidth FBW = 10 4.2 MHz
FBW = 01 9.66
Lowpass 3dB Bandwidth FBW = 11 9 MHz
3rd-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 30
Stopband Attenuation dB
5th-order filter, bandwidth = 2.5MHz, measured at 4MHz offset 40 49.5
LNA
LNA1 INPUT
Power Gain 19 dB
Noise Figure 0.83 dB
Input IP3 (Note 5) -1.1 dBm
Output Return Loss 10 dB
Intput Return Loss 8 dB

Maxim Integrated   3

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.
 MAX2769B

Universal GPS Receiver

AC ELECTRICAL CHARACTERISTICS* (continued)

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40NC to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.) (Note 1)

PARAMETER CONDITIONS MIN TYP MAX UNITS

LNA2 INPUT
Power Gain 13 dB
Noise Figure 1.14 dB
Input IP3 (Note 5) 1 dBm
Output Return Loss 19 dB
Input Return Loss 11 dB
FREQUENCY SYNTHESIZER
LO Frequency Range 0.2V < VTUNE < (VCC_ - 0.3V) 1550 1610 MHz
LO Tuning Gain 57 MHz/V
Reference Input Frequency 8 44 MHz
Main Divider Ratio 36 32,767 —
Reference Divider Ratio 1 1023 —
ICP = 0 0.5
Charge-Pump Current mA
ICP = 1 1
TCXO INPUT BUFFER/OUTPUT CLOCK BUFFER
Frequency Range 8 32 MHz
Output Logic-Level High (VOH) With respect to ground, IOH = 10FA (DC-coupled) 2 V
Output Logic-Level Low (VOL) With respect to ground, IOL = 10FA (DC-coupled) 0.8 V
Capacitive Slew Current Load = 10kW + 40pF, fCLKOUT = 32MHz 11 mA
Output Load 10||40 kI||pF
Reference Input Level Sine wave 0.5 VP-P
Clock Output Multiply/Divide /4, /2, /1
÷4 x2 —
Range (x2, max input frequency of 16MHz)
ADC
ADC Differential Nonlinearity AGC enabled, 3-bit output Q0.1 LSB
ADC Integral Nonlinearity AGC enabled, 3-bit output Q0.1 LSB
Note 1: MAX2769B is production tested at TA = +25NC and +85NC. All min/max specifications are guaranteed by design and char-
acterization from -40NC to +85NC, unless otherwise noted. Default register settings are not production tested or guaran-
teed. User must program the registers upon power-up.
Note 2: Default, low-NF mode of the IC. LNA choice is gated by the ANT_FLAG signal. In the normal mode of operation without an
active antenna, LNA1 is active. If an active antenna is connected and ANT_FLAG switches to 1, LNA1 is automatically dis-
abled and LNA2 becomes active. PLL is in an integer-N mode with fCOMP = fTCXO/16 = 1.023MHz and ICP = 0.5mA. The
complex IF filter is configured as a 5th-order Butterworth filter with a center frequency of 4MHz and bandwidth of 2.5MHz.
Output data is in a 2-bit sign/magnitude format at CMOS logic levels in the I channel only.
Note 3: The LNA output connects to the mixer input without a SAW filter between them.
Note 4: Two tones are located at 12MHz and 24MHz offset frequencies from the GPS center frequency of 1575.42MHz at -60dBm/
tone. Passive pole at the mixer output is programmed to be 13MHz.
Note 5: Measured from the LNA input to the LNA output. Two tones are located at 12MHz and 24MHz offset frequencies from the
GPS center frequency of 1575.42MHz at -60dBm per tone.

Maxim Integrated   4

*The parametric values (min, typ, max limits) shown in the Electrical Characteristics table supersede values quoted elsewhere in this data sheet.
 MAX2769B

Universal GPS Receiver

Typical Operating Characteristics

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.)

CASCADED RECEIVER GAIN CASCADED GAIN AND NOISE FIGURE LNA1 |S21| AND |S12|
vs. PGA GAIN CODE vs. TEMPERATURE vs. FREQUENCY
MAX2769B toc02
120 2.0 120 40
MAX2769B toc01

MAX2769B toc03
|S21|
30
TA = -40°C 115
CASCADED RECEIVER GAIN (dB)

100 1.5 20

LNA1 |S21| AND |S12| (dB)

AGC GAIN
NOISE FIGURE (dB)

110 10

CASCADED GAIN
TA = +25°C
0
80 1.0 NOISE FIGURE 105
-10 |S12|

TA = +85°C 100 -20

60 0.5
-30
95
-40
40 0 90 -50
0 5 10 15 20 25 30 35 40 45 50 55 60 65 -40 -15 10 35 60 85 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
PGA GAIN CODE (DECIMAL FORMAT) TEMPERATURE (°C) FREQUENCY (GHz)

LNA1 GAIN AND NOISE FIGURE LNA1 GAIN AND NOISE FIGURE LNA1 INPUT 1dB COMPRESSION POINT
vs. LNA1 BIAS DIGITAL CODE vs. TEMPERATURE vs. LNA1 BIAS DIGITAL CODE
MAX2769B toc04 MAX2769B toc05
1.6 25 1.4 19.6 5.0

MAX2769B toc06
LNA BIAS = 1000
LNA1 INPUT 1dB COMPRESSION POINT (dBm)

1.4 GAIN 19.4 2.5

1.2
20 19.2
1.2 0
1.0
NOISE FIGURE (dB)

NOISE FIGURE (dB)

19.0
LNA1 GAIN (dB)

LNA1 GAIN (dB)

1.0 15 -2.5
0.8 18.8
0.8 -5.0
0.6 18.6
0.6 10 -7.5
NOISE FIGURE 18.4
0.4 NOISE FIGURE
0.4 GAIN -10.0
5 18.2
0.2 0.2 -12.5
18.0
0 0 0 17.8 -15.0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -40 -15 10 35 60 85 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LNA BIAS DIGITAL CODE (DECIMAL) TEMPERATURE (°C) LNA BIAS DIGITAL CODE (DECIMAL)

Maxim Integrated   5

 MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.)

LNA2 |S21| AND |S12| LNA2 GAIN AND NOISE FIGURE LNA INPUT RETURN LOSS
vs. FREQUENCY vs. TEMPERATURE vs. FREQUENCY
MAX2769B toc08
30 2.0 13.6 0
MAX2769B toc07

MAX2769B toc09
|S21| LNA BIAS = 10
1.8 LNA1
20 13.4
1.6 -10

LNA INPUT RETURN LOSS (dB)

LNA2 |S21| AND |S12| (dB)

10
1.4 13.2
NOISE FIGURE (dB)

LNA2 GAIN (dB)

0 1.2 -20
13.0
-10 |S12| 1.0
0.8 12.8 -30
-20 NOISE FIGURE
0.6 LNA2
GAIN 12.6
-30
0.4 -40
-40 12.4
0.2
-50 0 12.2 -50
0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 -40 -15 10 35 60 85 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2
FREQUENCY (GHz) TEMPERATURE (°C) FREQUENCY (GHz)

LNA OUTPUT RETURN LOSS MIXER INPUT REFERRED IP1dB

vs. FREQUENCY vs. OFFSET FREQUENCY
0 0
MAX2769B toc10

MAX2769B toc11
PGA GAIN = 32dB
-10
MIXER INPUT REFERRED IP1dB (dB)
LNA OUTPUT RETURN LOSS (dB)

-20
-5
-30
LNA1 PGA GAIN = 51dB
-40
-10
-50
-60
-15
-70
LNA2
-80
PRF = -100dBm
-20 -90
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 0 50 100 150 200 250 300
FREQUENCY (GHz) OFFSET FREQUENCY (MHz)

Maxim Integrated   6

 MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.)

MIXER INPUT REFERRED NOISE FIGURE

1dB CASCADED NOISE FIGURE DESENSITIZATION vs. JAMMER FREQUENCY
MAX2769B toc12a MAX2769B toc12b vs. PGA GAIN
0
16

MAX2769B toc13
MIXER INPUT REFERRED NOISE FIGURE (dB)
-5 14
JAMMER POWER (dBm)

12
-10

10
-15
8

-20
800 825 850 875 900 925 950 1800 1850 1900 1950 2000 2050 2100 6
5 15 25 35 45 55 65
JAMMER FREQUENCY (MHz)
PGA GAIN (dB)

3RD-ORDER POLYPHASE FILTER MAGNITUDE 5TH-ORDER POLYPHASE FILTER MAGNITUDE MIXER INPUT REFERRED GAIN
RESPONSE vs. BASEBAND FREQUENCY RESPONSE vs. BASEBAND FREQUENCY vs. PGA GAIN CODE
10 10 100
MAX2769B toc14

MAX2769B toc15

MAX2769B toc16
FBW = 00b FBW = 00b
0 0
MIXER INPUT REFERRED GAIN (dB)

TA = -40°C
-10 80
-10
MAGNITUDE (dB)

MAGNITUDE (dB)

-20 TA = +25°C
-20
-30 60
-30
-40 TA = +85°C
-40
-50 40
-50 -60

-60 -70 20
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65
BASEBAND FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) PGA GAIN CODE (DECIMAL FORMAT)

Maxim Integrated   7

 MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.)

3RD-ORDER POLYPHASE FILTER 5TH-ORDER POLYPHASE FILTER 3RD-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 01) vs. BASEBAND FREQUENCY (FBW = 01) vs. BASEBAND FREQUENCY (FBW = 10)
10 10 10
MAX2769B toc17

MAX2769B toc18

MAX2769B toc19
0 0 0
FREQUENCY RESPONSE (dB)

FREQUENCY RESPONSE (dB)

FREQUENCY RESPONSE (dB)

-10 -10 -10

-20 -20 -20

-30 -30 -30

-40 -40 -40

-50 -50 -50

-60 -60 -60

0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)

5TH-ORDER POLYPHASE FILTER

vs. BASEBAND FREQUENCY (FBW = 10) 2-BIT ADC TRANSFER CURVE 3-BIT ADC TRANSFER CURVE
10 3.5
MAX2769B toc20

MAX2769B toc21

MAX2769B toc22
7
0 3.0
6
FREQUENCY RESPONSE (dB)

2.5
CODE (DECIMAL VALUE)

CODE (DECIMAL VALUE)

-10
5
2.0
-20
4
1.5
-30 3
1.0
-40 2
0.5
-50 1
0
0
-60 -0.5
0 2 4 6 8 10 12 14 16 18 20 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0
FREQUENCY (MHz) DIFFERENTIAL VOLTAGE (V) DIFFERENTIAL VOLTAGE (V)

Maxim Integrated   8

 MAX2769B

Universal GPS Receiver

Typical Operating Characteristics (continued)

(MAX2769B EV kit, VCC_ = 2.7V to 3.3V, TA = -40°C to +85NC, PGM = Ground. Registers are set to the default power-up states. LNA
input is driven from a 50I source. All RF measurements are done in the analog output mode with ADC bypassed. PGA gain is set
to 51dB gain by serial-interface word GAININ = 111010. Maximum IF output load is not to exceed 10kI||7.5pF on each pin. Typical
values are at VCC_ = 2.85V and TA = +25NC, unless otherwise noted.)

CRYSTAL OSCILLATOR FREQUENCY

DIGITAL OUTPUT CMOS LOGIC DIGITAL OUTPUT DIFFERENTIAL LOGIC vs. DIGITAL TUNING CODE
MAX2769B toc23 MAX2769B toc24
16,368.10

MAX2769B toc25
CLK

CRYSTAL OSCILLATOR FREQUENCY (kHz)

2V/div
CLK 16,368.05 TA = +25°C
1V/div

16,368.00
SIGN DATA
2V/div SIGN+ TA = -40°C
1V/div 16,367.95

MAGNITUDE SIGN- 16,367.90 TA = +85°C

DATA 1V/div
2V/div
16,367.85
20ns/div 40ns/div 0 4 8 12 16 20 24 28 32
DIGITAL TUNING CODE (DECIMAL)

CRYSTAL OSCILLATOR FREQUENCY CLOCK OUTPUT DRIVER WITH

VARIATION vs. TEMPERATURE 40pF LOAD
CRYSTAL OSCILLATOR FREQUENCY VARIATION (ppm)

MAX2769B toc27
10
MAX2769B toc26

8
6
4
2
0
-2
-4
-6
-8
-10
-40 -15 10 35 60 85 20ns/div
TEMPERATURE (°C)

Maxim Integrated   9

 MAX2769B

Universal GPS Receiver

Typical Application Circuit

BASEBAND

REFERENCE
BASEBAND
OUTPUT

CLOCK

INPUT
C10 C11
VCC_ADC

CLKOUT
TOP VIEW C7

XTAL
Q0

Q1
I1

I0

C6
21 20 19 18 17 16 15
VCCD
N.C. 22 14
C8
ADC

ADC

VCC_IF VCC_CP
23 13 C5
MAX2769B
IDLE CPOUT
PLL

24 12
C1 C2
C9 FILTER
LNA2 VCC_VCO
25 11
LNA2 VCO
90

C4
PGM
26 10 CS
0

C0
INTERFACE

LNA1
3-WIRE

27 9 SCLK SERIAL
LNA1
INPUT

N.C.
28 8 SDATA
+

1 2 3 4 5 6 7
ANTFLAG

LNAOUT

ANTBIAS

VCC_RF

MIXIN

LD

SHDN

C3 C13

ACTIVE
ANTENNA BIAS
C12

Table 1. Component List

DESIGNATION QUANTITY DESCRIPTION
C0, C9 2 0.47nF AC-coupling capacitors
C1 1 27pF PLL loop filter capacitor
C2 1 0.47nF PLL loop filter capacitor
C3–C8 6 0.1FF supply voltage bypass capacitor
C10, C11 2 10nF AC-coupling capacitor
C12 1 0.47nF AC-coupling capacitor
C13 1 0.1nF supply voltage bypass capacitor
R1 1 20kI PLL loop filter resistor

Maxim Integrated   10

 MAX2769B

Universal GPS Receiver

Pin Configuration

VCC_ADC

CLKOUT
TOP VIEW

XTAL
Q0

Q1
I1

I0
21 20 19 18 17 16 15

N.C. 22 14 VCCD

VCC_IF 23 13 VCC_CP

IDLE 24 12 CPOUT

LNA2 25 11 VCC_VCO
MAX2769B
PGM 26 10 CS

LNA1 27 9 SCLK
EP
+
N.C. 28 8 SDATA

1 2 3 4 5 6 7
ANTFLAG

LNAOUT
ANTBIAS
VCC_RF

MIXIN
LD

SHDN

TQFN

Pin Description
PIN NAME FUNCTION
Active Antenna Flag Logic Output. A logic-high indicates that an active antenna is connected to the
1 ANTFLAG
ANTBIAS pin.
2 LNAOUT LNA Output. The LNA output is internally matched to 50I.
3 ANTBIAS Buffered Supply Voltage Output. Provides a supply voltage bias for an external active antenna.
RF Section Supply Voltage. Bypass to ground with 100nF and 100pF capacitors in parallel as close
4 VCC_RF
as possible to the pin.
5 MIXIN Mixer Input. The mixer input is internally matched to 50I.
6 LD Lock-Detector CMOS Logic Output. A logic-high indicates the PLL is locked.
7 SHDN Operation Control Logic Input. A logic-low shuts off the entire device.
8 SDATA Data Digital Input of 3-Wire Serial Interface
Clock Digital Input of 3-Wire Serial Interface. Active when CS is low. Data is clocked in on the rising
9 SCLK
edge of the SCLK.

Maxim Integrated   11

 MAX2769B

Universal GPS Receiver

Pin Description (continued)

PIN NAME FUNCTION
Chip-Select Logic Input of 3-Wire Serial Interface. Set CS low to allow serial data to shift in. Set CS
10 CS
high when the loading action is completed.
11 VCC_VCO VCO Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.
Charge-Pump Output. Connect a PLL loop filter as a shunt C and a shunt combination of series R and
12 CPOUT
C (see the Typical Application Circuit).
PLL Charge-Pump Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to
13 VCC_CP
the pin.
Digital Circuitry Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the
14 VCCD
pin.
15 XTAL XTAL or Reference Oscillator Input. Connect to XTAL or a DC-blocking capacitor if TCXO is used.
16 CLKOUT Reference Clock Output
17 Q1 Q-Channel Voltage Outputs. Bits 0 and 1 of the Q-channel ADC output or analog differential voltage
18 Q0 output.
19 VCC_ADC ADC Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.
20 I0 I-Channel Voltage Outputs. Bits 0 and 1 of the I-channel ADC output or analog differential voltage
21 I1 output.
22 N.C. No Connection. Leave this pin unconnected.
23 VCC_IF IF Section Supply Voltage. Bypass to ground with a 100nF capacitor as close as possible to the pin.
Operation Control Logic Input. A logic-low enables the idle mode, in which the XTAL oscillator is
24 IDLE
active, and all other blocks are off.
25 LNA2 LNA Input Port 2. This port is typically used with an active antenna. Internally matched to 50I.
Logic Input. Connect to ground to use the serial interface. A logic-high allows programming to 8
26 PGM hard-coded by device states connecting SDATA, CS, and SCLK to supply or ground according to
Table 3.
LNA Input Port 1. This port is typically used with a passive antenna. Internally matched to 50I (see
27 LNA1
the Typical Application Circuit).
28 N.C. No connection. Leave this pin open.
Exposed Pad. Ultra-low-inductance connection to ground. Place several vias to the PCB ground
— EP
plane.

Maxim Integrated   12

 MAX2769B

Universal GPS Receiver

Detailed Description
Integrated Active Antenna Sensor
BASEBAND
The MAX2769B includes a low-dropout switch to bias an CLOCK
external active antenna. To activate the antenna switch 16
CLKOUT

output, set ANTEN in the Configuration 1 register to logic 10nF

1. This closes the switch that connects the antenna bias
pin to VCC_RF to achieve a low 200mV dropout for a MAX2769B
20mA load current. A logic-low in ANTEN disables the
XTAL
antenna bias. The active antenna circuit also features 15
short-circuit protection to prevent the output from being 23pF
shorted to ground.
Low-Noise Amplifier (LNA)
The MAX2769B integrates two low-noise amplifiers.
LNA1 is typically used with a passive antenna. This LNA
requires an AC-coupling capacitor. In the default mode,
the bias current is set to 4mA, the typical noise figure and Figure 1. Schematic of the Crystal Oscillator in the MAX2679B
EV Kit
IIP3 are approximately 0.8dB and -1.1dBm, respectively.
LNA2 is typically used with an active antenna. The LNA2
is internally matched to 50. and requires a DC-blocking operates by counting the number of magnitude bits over
capacitor. Bits LNAMODE in the Configuration 1 register 512 ADC clock cycles and comparing the magnitude bit
control the modes of the two LNAs. See Table 6 and count to the reference value provided through a control
Table 7 for the LNA mode settings. word (GAINREF). The desired magnitude bit density is
Mixer expressed as a value of GAINREF in a decimal format
The MAX2769B includes a quadrature mixer to output divided by the counter length of 512. For example, to
low-IF or zero IF I and Q signals. The quadrature mixer achieve the magnitude bit density of 33%, which is opti-
is internally matched to 50I and requires a low-side LO mal for a 2-bit converter, program the GAINREF to 170,
injection. The output of the LNA and the input of the mixer so that 170/512 = 33%.
are brought off-chip to facilitate the use of a SAW filter. Baseband Filter
Programmable Gain Amplifier (PGA) The baseband filter of the receiver can be programmed
The MAX2769B integrates a baseband programmable to be a lowpass filter or a complex bandpass filter.
gain amplifier that provides 59dB of gain control range. The lowpass filter can be configured as a 3rd-order
The PGA gain can be programmed through the serial Butterworth filter for a reduced group delay by setting
interface by setting bits GAININ in the Configuration bit F3OR5 in the Configuration 1 register to be 1 or a
3 register. Set bits 12 and 11 (AGCMODE) in the 5th-order Butterworth filter for a steeper out-of-band
Configuration 2 register to 10 to control the gain of the rejection by setting the same bit to be 0. The two-sided
PGA directly from the 3-wire interface. 3dB corner bandwidth can be selected to be 2.5MHz,
4.2MHz, 9.66MHz, or by programming bits FBW in the
Automatic Gain Control (AGC) Configuration 1 register. When the complex filter is
The MAX2769B provides a control loop that automatically enabled by changing bit FCENX in the Configuration 1
programs PGA gain to provide the ADC with an input register to 1, the lowpass filter becomes a bandpass
power that optimally fills the converter and establishes a filter and the center frequency can be programmed by
desired magnitude bit density at its output. An algorithm bits FCEN and FCENMSB in the Configuration 1 register.

Maxim Integrated   13

 MAX2769B

Universal GPS Receiver

Table 2. Output Data Format

INTEGER SIGN/MAGNITUDE UNSIGNED BINARY TWO’S COMPLEMENT BINARY
VALUE 1b 2b 3b 1b 2b 3b 1b 2b 3b
7 0 01 011 1 11 111 0 01 011
5 0 01 010 1 11 110 0 01 010
3 0 00 001 1 10 101 0 00 001
1 0 00 000 1 10 110 0 00 000
-1 1 10 100 0 01 011 1 11 111
-3 1 10 101 0 01 010 1 11 110
-5 1 11 110 0 00 001 1 10 101
-7 1 11 111 0 00 000 1 10 100

Synthesizer Integer Divider = 78(d) = 000 000 0100 1110 (binary)

The MAX2769B integrates a 20-bit sigma-delta fractional- Fractional Divider = 0.771 x 220 = 808452 (decimal) =
N synthesizer allowing the device to tune to a required 1100 0101 0110 0000 0100
VCO frequency with an accuracy of approximately
In the fractional mode, the synthesizer should not be
Q30Hz. The synthesizer includes a 10-bit reference
operated with integer division ratios greater than 251.
divider with a divisor range programmable from 1 to
1023, a 15-bit integer portion main divider with a divisor Crystal Oscillator
range programmable from 36 to 32767, and also a 20-bit The MAX2769B includes an on-chip crystal oscillator. A
fractional portion main divider. The reference divider is parallel mode crystal is required when the crystal oscilla-
programmable by bits RDIV in the PLL integer division tor is being used. It is recommended that an AC-coupling
ratio register (see Table 11), and can accommodate ref- capacitor be used in series with the crystal and the XTAL
erence frequencies from 8MHz to 32MHz. The reference pin to optimize the desired load capacitance and to
divider needs to be set so the comparison frequency falls center the crystal-oscillator frequency. Take the para-
between 0.05MHz to 32MHz. sitic loss of interconnect traces on the PCB into account
The PLL loop filter is the only external block of the syn- when optimizing the load capacitance. For example, the
thesizer. A typical PLL filter is a classic C-R-C network MAX2769B EV kit utilizes a 16.368MHz crystal that is
at the charge-pump output. The charge-pump output designed for a 12pF load capacitance. A series capaci-
sink and source current is 0.5mA by default, and the tor of 23pF is used to center the crystal oscillator frequen-
LO tuning gain is 57MHz/V. As an example, see the cy, see Figure 1. In addition, the 5-bit serial-interface
Typical Application Circuit for the recommended loop- word, XTALCAP in the PLL Configuration register, can
filter component values for fCOMP = 1.023MHz and loop be used to vary the crystal-oscillator frequency electroni-
bandwidth = 50kHz. cally. The range of the electronic adjustment depends on
how much the chosen crystal frequency can be pulled
The desired integer and fractional divider ratios can be
by the varying capacitor. The frequency of the crystal
calculated by dividing the LO frequency (fLO) by fCOMP.
oscillator used on the MAX2769B EV kit has a range of
fCOMP can be calculated by dividing the TCXO frequency
approximately 200Hz.
(fTCXO) by the reference division ratio (RDIV). For exam-
ple, let the TCXO frequency be 20MHz, RDIV be 1, and The MAX2769B provides a reference clock output. The
the nominal LO frequency be 1575.42MHz. The following frequency of the clock can be adjusted to crystal-oscilla-
method can be used when calculating divider ratios sup- tor frequency, a quarter of the oscillator frequency, a half
porting various reference and comparison frequencies: of the oscillator frequency (fXTAL P 16MHz), or twice the
fTCXO 20MHz oscillator frequency, by programming bits REFDIV in the
= =
Comparison Frequency = 20MHz PLL Configuration register.
RDIV 1
fLO 1575.42MHz
= =
LO Frequency Divider = 78.771
fCOMP 20MHz

Maxim Integrated   14

 MAX2769B

Universal GPS Receiver

ADC data mapping. The variable T = 1 designates the location
The MAX2769B features an on-chip ADC to digitize the of the magnitude threshold for the 2-bit case.
downconverted GPS signal. The maximum sampling
ADC Fractional Clock Divider
rate of the ADC is approximately 50Msps. The sampled
A 12-bit fractional clock divider is located in the clock
output is provided in a 2-bit format (1-bit magnitude and
path prior to the ADC and can be used to generate the
1-bit sign) by default and also can be configured as a
ADC clock that is a fraction of the reference input clock.
1-bit or 2-bit in both I and Q channels, or 1-bit, 2-bit, or
In a fractional divider mode, the instantaneous division
3-bit in the I channel only. The ADC supports the digital
ratio alternates between integer division ratios to achieve
outputs in three different formats: the unsigned binary,
the required fraction. For example, if the fractional output
the sign and magnitude, or the two’s complement format
clock is 4.5 times slower than the input clock, an average
by setting bits FORMAT in Configuration register 2. MSB
division ratio of 4.5 is achieved through an equal series
bits are output at I1 or Q1 pins and LSB bits are output at
of alternating divide-by-4 and divide-by-5 periods. The
I0 or Q0 pins, for I or Q channel, respectively. In the case
fractional division ratio is given by:
of 3-bit, output data format is selected in the I channel
only, the MSB is output at I1, the second bit is at I0, and fOUT/fIN = LCOUNT/(4096 - MCOUNT + LCOUNT)
the LSB is at Q1. where LCOUNT and MCOUNT are the 12-bit counter val-
Figure 2 illustrates the ADC quantization levels for 2-bit ues programmed through the serial interface.
and 3-bit cases and also describes the sign/magnitude

011

01

010

001

00

000

-7 -6 -5 -4 -3 -2 -1

1 2 3 4 5 6 7
100

10 T=1
101

110

11
111

Figure 2. ADC Quantization Levels for 2- and 3-Bit Cases

Maxim Integrated   15

 MAX2769B

Universal GPS Receiver

DSP Interface data, and so on. In this case, the serial clock must be at
GPS data is output from the ADC as the four logic sig­nals least twice as fast as the ADC clock. If a 4-bit serialization
(bit0, bit1, bit2, and bit3) that represent sign/magnitude, of bit0, bit1, bit2, and bit3 is chosen, the serial clock must
unsigned binary, or two’s complement binary data in be at least four times faster than the ADC clock.
the I (bit0 and bit1) and Q (bit2 and bit3) channels. The The ADC data is loaded in parallel into four holding
resolution of the ADC can be set up to 3 bits per channel. registers that correspond to four ADC outputs. Holding
For example, the 2-bit I and Q data in sign/magnitude registers are 16 bits long and are clocked by the ADC
format is mapped as follows: bit0 = ISIGN, bit1 = IMAG, clock. At the end of the 16-bit ADC cycle, the data is
bit2 = QSIGN, and bit3 = QMAG. The data can be serial- transferred into four shift registers and shifted serially to
ized in 16-bit segments of bit0, followed by bit1, bit2, and the output during the next 16-bit ADC cycle. Shift regis-
bit3. The number of bits to be serialized is controlled by ters are clocked by a serial clock that must be chosen
the bits STRMBITS in the Configuration 3 register. This fast enough so that all data is shifted out before the next
selects between bit0; bit0 and bit1; bit0 and bit2; and set of data is loaded from the ADC. An all-zero pattern
bit0, bit1, bit2, and bit3 cases. If only bit0 is serialized, the follows the data after all valid ADC data are streamed
data stream consists of bit0 data only. If a serialization of to the output. A DATASYNC signal is used to signal the
bit0 and bit1 (or bit2) is selected, the stream data pattern beginning of each valid 16-bit data slice. In addition,
consists of 16 bits of bit0 data followed by 16 bits of bit1 there is a TIME_SYNC signal that is output every 128 to
(or bit2) data, which, in turn, is followed by 16 bits of bit0 16,384 cycles of the ADC clock.

STRM_EN

PIN 21
I
OUTPUT PIN 20
ADC
DRIVER PIN 17
Q
PIN 18

BIT 0 DATA_OUT
BIT 1 CLK_SER
BIT 2 DATA_SYNC
BIT 3 TIME_SYNC
STRM_EN
STRM_START STRM_EN
STRM_STOP
CONTROL STRM_COUNT<2:0>
SIGNALS DIEID<1:0>
FROM 3-WIRE STRM_BITS<1:0>
INTERFACE FRM_COUNT<27:0>
STAMP_EN
DAT_SYNCEN
TIME_SYNCEN
STRM_RST
CLK_ADC CLK_SER

ADCCLK_SEL L_CNT<11:0>
M_CNT<11:0>

CLK_IN CLK_OUT
REF/XTAL THROUGH
PIN 15 /2
/4
x2 FRCLK_SEL

REFDIV<1:0> SERCLK_SEL

Figure 3. DSP Interface Top-Level Connectivity and Control Signals

Maxim Integrated   16

 MAX2769B

Universal GPS Receiver

Preconfigured Device States Serial Interface, Address, and
When a serial interface is not available, the device can Bit Assignments
be used in preconfigured states that don’t require pro- A serial interface is used to program the MAX2769B for
gramming through the serial interface. Connecting the configuring the different operating modes.
PGM pin to logic-high and SCLK, SDATA, and CS pins The serial interface is controlled by three signals: SCLK
to either logic-high or low sets the device in one of the (serial clock), CS (chip select), and SDATA (serial data).
preconfigured states according to Table 3. The control of the PLL, AGC, test, and block selection
Power-On Reset (POR) is performed through the serial-interface bus from the
The MAX2769B incorporates power-on reset circuitry to baseband controller. A 32-bit word, with the MSB (D27)
ensure that register settings are loaded upon power-up. being sent first, is clocked into a serial shift register when
To ensure proper operation, the rising edge of PGM must the chip-select signal is asserted low. The timing of the
occur no sooner than when VCC_ reaches 90% of its final interface signals is shown in Figure 5 and Table 4 along
nominal value; see Figure 4 for details. with typical values for setup and hold time requirements.

Table 3. Preconfigured Device States

DEVICE ELECTRICAL CHARACTERISTICS 3-WIRE CONTROL PINS
DEVICE STATE

LOGIC LEVEL
FREQUENCY

FREQUENCY
REFERENCE

REFERENCE

I AND Q OR I

NUMBER OF

IF CENTER

IF FILTER
BW (MHz)

IF FILTER
DIVISION

DIVISION

I AND Q
IQ BITS

ORDER
RATIO

RATIO

ONLY

DATA
(MHz)

(MHz)

SCLK
MAIN

CS
0 16.368 16 1536 I 1 Differential 4.092 2.5 5th 0 0 0
1 16.368 16 1536 I 1 Differential 4.092 2.5 3rd 0 0 1
2 16.368 16 1536 I 2 CMOS 4.092 2.5 5th 0 1 0
3 32.736 32 1536 I 2 CMOS 4.092 2.5 5th 0 1 1
4 19.2 96 7857 I 2 CMOS 4.092 2.5 5th 1 0 0
5 27.456 26 1488 I 3 CMOS 4.092 4.2 5th 1 0 1
6 16.368 16 1536 I 3 CMOS 4.092 4.2 5th 1 1 0
7 27.456 26 1508 I 3 CMOS 9.27075 9.66 5th 1 1 1

VCC_

100%

90%

0%
PGM TIME (s)

PGM RISING EDGE ANYTIME

PGM = 0 AFTER VCC_ HAS REACHED
90% OF ITS NOMINAL VALUE.

TIME (s)

Figure 4. VCC_ Power-On Reset

Maxim Integrated   17

 MAX2769B

Universal GPS Receiver

CS

tCSH
tCSS tCSW

SCLK

tDS tDH tCH

tCL

DATA DATA ADDR ADDR

SDATA
MSB LSB MSB LSB

Figure 5. 3-Wire Timing Diagram

Table 4. Serial-Interface Timing Requirements

SYMBOL PARAMETER TYP VALUE UNITS
tCSS Falling edge of CS to rising edge of the first SCLK time. 10 ns
tDS Data to serial-clock setup time. 10 ns
tDH Data to clock hold time. 10 ns
tCH Serial clock pulse-width high. 25 ns
tCL Clock pulse-width low. 25 ns
tCSH Last SCLK rising edge to rising edge of CS. 10 ns
tCSW CS high pulse width. 1 clock

Table 5. Default Register Settings Overview

REGISTER ADDRESS
DATA
NAME (A3:A0)
CONF1 0000 Configures RX and IF sections, bias settings for individual blocks.
CONF2 0001 Configures AGC and output sections.
CONF3 0010 Configures support and test functions for IF filter and AGC.
PLLCONF 0011 PLL, VCO, and CLK settings.
DIV 0100 PLL main and reference division ratios, other controls.
FDIV 0101 PLL fractional division ratio, other controls.
STRM 0110 DSP interface number of frames to stream.
CLK 0111 Fractional clock-divider values.
TEST1 1000 Reserved for test mode.
TEST2 1001 Reserved for test mode.

Maxim Integrated   18

 MAX2769B

Universal GPS Receiver

Table 6. Default Register Settings

POWER-ON
REGISTER ADDRESS RESET, PRECONFIGURED DEVICE STATE, PGM = 1 (hex)
NAME (A3:A0) PGM = 0
(hex) 0 1 2 3 4 5 6 7
CONF1 0000 A2919A3 A2919A3 A2919A3 A2919A7 A2919A3 A2919A3 A293573 A293573 A29B26B
CONF2 0001 055028C 055121C 055028C 055121C 055028C 055028C 855030C 855030C 855030C
CONF3 0010 EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC EAFE1DC
PLLCONF 0011 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008 9EC0008
DIV 0100 0C00080 0C00080 0C00080 0C00080 0C00100 3D62300 0BA00D0 0C00080 0BC80D0
FDIV 0101 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070 8000070
STRM 0110 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000 8000000
CLK 0111 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2 10061B2
TEST1 1000 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401 1E0F401
TEST2 1001 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 28C0402 7CC0403

Detailed Register Definitions

Table 7. Configuration 1 (Address: 0000)
DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
Chip enable. Set 1 to enable the device and 0 to disable the entire device except the
CHIPEN 27 1
serial bus.
IDLE 26 0 Idle enable. Set 1 to put the chip in the idle mode and 0 for operating mode.
RESERVED 25:22 1000 —
RESERVED 21:20 10 —
RESERVED 19:18 10 —
RESERVED 17:16 01 —
Mixer pole selection. Set 1 to program the passive filter pole at mixer output at 36MHz, or
MIXPOLE 15 0
set 0 to program the pole at 13MHz.
LNA mode selection, D14:D13 = 00: LNA selection gated by the antenna bias circuit, 01:
LNAMODE 14:13 00
LNA2 is active; 10: LNA1 is active; 11: both LNA1 and LNA2 are off.
MIXEN 12 1 Mixer enable. Set 1 to enable the mixer and 0 to shut down the mixer.
ANTEN 11 1 Antenna bias enable. Set 1 to enable the antenna bias and 0 to shut down the antenna bias.
IF center frequency programming. Default for fCENTER = 3.092MHz, BW = 2.5MHz. The
FCEN 10:5 001101 MSB of FCEN is located in Register Test Mode 2 (Table 16).
001101 = 3.092MHz, 001011 = 4.092MHz, 010011 = 10.0MHz
IF filter center bandwidth selection. D4:D3 = 00: 2.5MHz; 10: 4.2MHz; 01: 9.66MHz;
FBW 4:3 00
11: Reserved.
Filter order selection. Set 0 to select the 5th-order Butterworth filter. Set 1 to select the 3rd-
F3OR5 2 0
order Butterworth filter.
Polyphase filter selection. Set 1 to select complex bandpass filter mode. Set 0 to select
FCENX 1 1
lowpass filter mode.
FGAIN 0 1 IF filter gain setting. Set 0 to reduce the filter gain by 6dB.

Maxim Integrated   19

 MAX2769B

Universal GPS Receiver

Table 8. Configuration 2 (Address: 0001)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
I and Q channels enable. Set 1 to enable both I and Q channels and 0 to enable I
IQEN 27 0
channel only.
AGC gain reference value expressed by the number of MSB counts (magnitude bit
GAINREF 26:15 170d density). 10101010 = 234 magnitude bit density reference, 1010100 = 84 magnitude bit
density reference, 100111010 = 314 magnitude bit density reference.
RESERVED 14:13 00 Reserved.
AGC mode control. Set D12:D11 = 00: independent I and Q; 01: reserved; 10: gain is set
AGCMODE 12:11 00
directly from the serial interface by GAININ; 11: reserved.
Output data format. Set D10:D9 = 00: unsigned binary; 01: sign and magnitude; 1X:
FORMAT 10:9 01
two’s complement binary.
Number of bits in the ADC. Set D8:D6 = 000: 1 bit, 001: reserved; 010: 2 bits;
BITS 8:6 010
011: reserved, 100: 3 bits.
Output driver configuration. Set D5:D4 = 00: CMOS logic, 01: reserved; 1X: analog
DRVCFG 5:4 00
outputs.
RESERVED 3 1 —
RESERVED 2 0 —
DIEID 1:0 00 Identifies a version of the IC.

Table 9. Configuration 3 (Address: 0010)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
PGA gain value programming from the serial interface in steps of dB per LSB. 000000 =
GAININ 27:22 111010 PGA gain set to 0dB, 101011 = 42dB, 101100 = 43dB, 101110 = 45dB, 111010 = 57dB,
111111 = 62dB.
RESERVED 21 1 —
HILOADEN 20 0 Set 1 to enable the output driver to drive high loads.
RESERVED 19 1 —
RESERVED 18 1 —
RESERVED 17 1 —
RESERVED 16 1 —
Highpass coupling enable. Set 1 to enable the highpass coupling between the filter
FHIPEN 15 1
and PGA, or 0 to disable the coupling.
RESERVED 14 1 —
RESERVED 13 1 —
RESERVED 12 0 —
DSP interface for serial streaming of data enable. This bit configures the IC such that the
STRMEN 11 0 DSP interface is inserted in the signal path. Set 1 to enable the interface or 0 to disable
the interface.

Maxim Integrated   20

 MAX2769B

Universal GPS Receiver

Table 9. Configuration 3 (Address: 0010) (continued)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
The positive edge of this command enables data streaming to the output. It also enables
STRMSTART 10 0
clock, data sync, and frame sync outputs.
The positive edge of this command disables data streaming to the output. It also
STRMSTOP 9 0
disables clock, data sync, and frame sync outputs.
RESERVED 8:6 111 —
Number of bits streamed. D5:D4 = 00: reserved; 01: 1 MSB, 1 LSB; 10: reserved, Q
STRMBITS 5:4 01
MSB; 11: 1 MSB, 1 LSB, Q MSB, Q LSB.
The signal enables the insertion of the frame number at the beginning of each frame. If
STAMPEN 3 1
disabled, only the ADC data is streamed to the output.
This signal enables the output of the time sync pulses at all times when streaming is
enabled by the STRMEN command. Otherwise, the time sync pulses are available only
TIMESYNCEN 2 1
when data streaming is active at the output, for example, in the time intervals bound by
the STRMSTART and STRMSTOP commands.

This control signal enables the sync pulses at the DATASYNC output. Each pulse is
DATSYNCEN 1 0 coincident with the beginning of the 16-bit data word that corresponds to a given output
bit.
This command resets all the counters irrespective of the timing within the
STRMRST 0 0
stream cycle.

Table 10. PLL Configuration (Address: 0011)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
RESERVED 27 1 —
RESERVED 26 0 —
RESERVED 25 0 —
REFOUTEN 24 1 Clock buffer enable. Set 1 to enable the clock buffer or 0 to disable the clock buffer.
RESERVED 23 1 —
Clock output divider ratio. Set D22:D21 = 00: clock frequency = XTAL frequency x 2;
REFDIV 22:21 11 01: clock frequency = XTAL frequency/4; 10: clock frequency = XTAL frequency/2;
11: clock frequency = XTAL.
Current programming for XTAL oscillator/buffer. Set D20:D19 = 00: reserved; 01: buffer
IXTAL 20:19 01
normal current; 10: reserved; 11: oscillator high current.
RESERVED 18:14 10000 —
LDMUX 13:10 0000 PLL lock-detect enable.

Maxim Integrated   21

 MAX2769B

Universal GPS Receiver

Table 10. PLL Configuration (Address: 0011) (continued)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
ICP 9 0 Charge-pump current selection. Set 1 for 1mA and 0 for 0.5mA.
PFDEN 8 0 Set 0 for normal operation or 1 to disable the PLL phase frequency detector.
RESERVED 7 0 —
RESERVED 6:4 000 —
INT_PLL 3 1 PLL mode control. Set 1 to enable the integer-N PLL or 0 to enable the fractional-N PLL.
PWRSAV 2 0 PLL power-save mode. Set 1 to enable the power-save mode or 0 to disable.
RESERVED 1 0 —
RESERVED 0 0 —

Table 11. PLL Integer Division Ratio (Address 0100)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
NDIV 27:13 1536d PLL integer division ratio.
RDIV 12:3 16d PLL reference division ratio.
RESERVED 2:0 000 —

Table 12. PLL Division Ratio (Address 0101)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
FDIV 27:8 80000h PLL fractional divider ratio.
RESERVED 7:0 01110000 —

Table 13. Reserved (Address 0110)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
RESERVED 27:0 8000000h —

Maxim Integrated   22

 MAX2769B

Universal GPS Receiver

Table 14. Clock Fractional Division Ratio (Address 0111)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
Sets the value for the L counter. 000100000000 = 256 fractional clock divider,
L_CNT 27:16 256d
100000000000 = 2048 fractional clock divider.
Sets the value for the M counter. 011000011011 = 1563 fractional clock divider,
M_CNT 15:4 1563d
100000000 = 2048 fractional clock divider.
Fractional clock divider. Set 1 to select the ADC clock to come from the fractional clock
FCLKIN 3 0
divider, or 0 to bypass the ADC clock from the fractional clock divider.
ADC clock selection. Set 0 to select the ADC and fractional divider clocks to come from
ADCCLK 2 0
the reference divider/multiplier.
RESERVED 1 1 —
MODE 0 0 DSP interface mode selection.

Table 15. Test Mode 1 (Address 1000)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
RESERVED 27:0 1E0F401 —

Table 16. Test Mode 2 (Address 1001)

DEFAULT
DATA BIT LOCATION VALUE DESCRIPTION
(PGM = 0)
RESERVED 27:1 28C0402 —
FCENMSB 0 0 When combined with FCEN, this bit represents the MSB of a 7-bit FCEN word.

Applications Information Power-Supply Layout

The LNA and mixer inputs require careful consideration To minimize coupling between different sections of the
in matching to 50I lines. Proper supply bypassing, IC, a star power-supply routing configuration with a large
grounding, and layout are required for reliable perfor- decoupling capacitor at a central VCC_ node is recom-
mance from any RF circuit. mended. The VCC_ traces branch out from this node,
each going to a separate VCC_ node in the circuit. Place
Layout Issues
a bypass capacitor as close as possible to each supply
The MAX2769B EV kit can be used as a starting point
pin This arrangement provides local decoupling at each
for layout. For best performance, take into consideration
VCC_ pin. Use at least one via per bypass capacitor for
grounding and routing of RF, baseband, and power-
a low-inductance ground connection. Do not share the
supply PCB proper line. Make connections from vias
capacitor ground vias with any other branch.
to the ground plane as short as possible. On the high-
impedance ports, keep traces short to minimize shunt Refer to Maxim’s Wireless and RF Application Notes
capacitance. EV kit Gerber files can be requested at for more information.
[Link].

Maxim Integrated   23

 MAX2769B

Universal GPS Receiver

Chip Information Package Information

PROCESS: SiGe BiCMOS For the latest package outline information and land patterns (foot-
prints), go to [Link]/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
Ordering Information drawing pertains to the package regardless of RoHS status.

PACKAGE PACKAGE OUTLINE LAND

PART TEMP RANGE PIN-PACKAGE
TYPE CODE NO. PATTERN NO.
MAX2769BETI/V+ -40NC to +85NC 28 TQFN-EP*
28 TQFN-EP T2855+3 21-0140 90-0023
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V denotes an automotive qualified part.

Maxim Integrated   24

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Universal GPS Receiver

Revision History

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 5/11 Initial release —
1 8/11 Corrected part number in Ordering Information section. 24
Removed Temperature Sensor Voltage vs. Temperature graph in the Typical
2 10/12 9
Operating Characteristics.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical
Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 25
© 2012 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.
 MAX2769B

Universal GPS Receiver

Maxim Integrated   26

 MAX2769B

Universal GPS Receiver

Maxim Integrated   27