1. A CPU with a 20-MHz clock is connected to a memory unit whose access time is 40 ns.
Formulate a READ and WRITE timing diagrams using a READ strobe and WRITE strobe.
Include the address in the timing diagram.
Ans:
20 MHz = 20 × 106Hz
T = 10-6 / 20 = 50 n sec
2. Indicate whether the following constitute a control, status or data transfer commands:
a) skip next instruction if flag is set
b) seek a given record on a magnetic disk
c) check if I/O device is ready
d) move printer paper to begining of next page
e) read interface status register
Ans:
(a) Status command – Checks status of flag bit.
(b) Control command – Moves magnetic head in disk.
(c) Status command – checks if device power is on.
(d) Control command – Moves paper position.
(e) Data input command – Reads value of a register.
3) Give atleast five status conditions for the setting of individual bits in the status register of
an asynchronus communication interface.
Ans:
1. Output flag to indicate when transmitter register is empty.
2. Input flag to indicate when receiver register is full.
3. Enable interrupt if any flag is set.
4. Parity error; 5.
5. Framing error.
4) How many characters per second can be transmitted over a 1200-baud line in each of the
following modes?
a. synchronous serial transmission
b. asynchronous serial transmission with two stop bits
c. . asynchronous serial transmission with two one bit
Ans:
Synchronous serial transmission
Buad rate = 1200 bytes per second
a) Number of 8-bit characters that can be transmitted per second = (1200)/8 = 150 characters per
second (cps)
b) Asynchronous serial transmission with two stop bits.
Total Data To send in 1 frame = 1 bit(start) + 8 bits(char size) + 2 bits (Stop) = 11 bits.
Number of 8-bit characters that can be transmitted per second = (1200)/11 = 109 cps
c) synchronous serial transmission with one stop bit
Total Data To send in 1 frame = 1 bit(start) + 8 bits(char size) + 1 bit (Stop) = 10 bits.
Number of 8-bit characters that can be transmitted per second = (1200)/10 = 120 cps
5) A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4
decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
Ans:
RAM chip size = 1k ×8 [1024 words of 8 bits each]
RAM to construct =16k ×16
Number of chips required = (16k x 16)/ ( 1k x 8)
= (16 x 2) [16 chips vertically with each having 2 chips horizontally]
So to select one chip out of 16 vertical chips,
we need 4 x 16 decoder.
Available decoder is 2 x 4 decoder
T
o be constructed is 4 x 16 decoder
Hence 4 + 1 = 5 decoders are required.
6. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt
service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to machine instruction which takes one
clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock
cycles to execute. The designer of the system also has an alternate approach of using DMA
controller to implement the same transfer. The DMA controller requires 20 clock cycles for
initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one
byte of data from the device to the memory. What is the approximate speedup when the DMA
controller based design is used in place of the interrupt driven program based input-output?
Ans:
STATEMENT CLOCK CYCLE(S) NEEDED
Initialize the address register 1
Initialize the count to 500 1
LOOP: Load a byte from device 2
Store in memory at address given by address register0 2
Increment the address register 1
Decrement the count 1
If count != 0 go to LOOP 1
Interrupt driven transfer time = 1+1+500×(2+2+1+1+1) = 3502
DMA based transfer time = 20+500*2 = 1020
Speedup = 3502/1020 ≈ 3.4
7. An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-
bytes. The processor generates 32-bit addresses. The cache controller maintains the tag
information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As
many bits as the minimum needed to identify the memory block mapped in the cache. What is
the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
Ans:
Cache size = 8 KB
Block size = 32 bytes
Number of cache lines = Cache size / Block size = (8 × 1024 bytes) / 32 = 256
19 bits 8-bits 5-bits
Tag index block
total bits required to store meta-data of 1 line = 1 + 1 + 19 = 21 bits
total memory required = 21 × 256 = 5376 bits
8. Why does DMA have priority over the CPU when both request a memory transfer?
Ans:
The CPU can wait to fetch instructions and data from memory without any damage occurring
except loss of time. DMA usually transfers data from a device that cannot be stopped since
information continues to flow so loss of data may occur.
9. A DMA controller transfers 16-bits word to memory using cycle stealing. The word are
assembled from a device that transmits character at a rate of 2400 characters per second. The
CPU is fetching and executing intructions at an average rate of 1 million instructions per
second. By how much will the CPU be slowed down because of DMA transfer?
Ans:
1 character is 8 bits which makes speed of device 2400 Bytes/sec.
Word size is 2B tranferring it will take 1/1200=833.33 microseconds.
CPU refers to memory on the average once (or more) every 1 µ sec (1/106 ).
Memory executes 106 instructions which means it fetches 106 instructions or words in 1 second.
Therfore 1 word is accessed in 1 microsecond or it cycle time.
Therfore slow down =(1/(833.33+1))×100%= 0.119 or 0.12%
10. A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of
the following is a legal program counter (all values in decimal)?
a) 600 b) 700 c) 400 c) 500
Ans:
Here, size of instruction = 24 / 8 = 3 bytes.
Program Counter can shift 3 bytes at a time to jump to next instruction.
Starting address of the program is 300. The size of instruction is 3 bytes long So the address is
always the multiple of 3 bytes next address is 600 it is also the next instruction of the program.
Option A is the correct answer.
11. Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss
and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that
80% of the processor’s read requests result in a cache hit. The average read access time in
nanoseconds is__
Ans:
avg access time = hit rate * hit time + miss rate * miss time
= 0.8 * 5 + 0.2 * 50 = 14 ns
12. 4. The size of the data count register of a DMA controller is 16 bits. The processor needs to
transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable.
The minimum number of times the DMA controller needs to get the control of the system bus
from the processor to transfer the file from the disk to main memory is?
Ans:
Size of data count register of the DMA controller = 16 bits
Data that can be transferred in one go = 2^16 bytes = 64 kilobytes
File size to be transferred = 29154 kilobytes
So, number of times the DMA controller needs to get the control of the system bus from the
processor to transfer the file from the disk to main memory = (29154 / 64) = 456 (appx).
13. A processor is fetching instructions at the rate of 1 MIPS. A DMA module is used to
transfer characters to RAM from a device transmitting at 9600 bps. How much time will the
processor be slowed down due to DMA activity?
Ans:
DMA module transferring characters at 9600 bps = 9600/8 Bps = 1200 Bps
Processor is fetching instructions at the rate = 1 MIPS (million instruction per second) Slowdown
= 1200 / (10^6) sec
= (1200 * 10^3 ) / (10^6) ms
= 12 / 10 ms = 1.2 ms
14. After the completion of the DMA transfer, the processor is notified by---------
Ans: Interrupt signal ( The controller raises an interrupt signal to notify the processor that the
transfer was complete).
15. The controller is connected to the ------
Ans: System BUS ( The controller is directly connected to the system BUS to provide faster
transfer of data).
16. The technique whereby the DMA controller steals the access cycles of the processor to
operate is called-----------
Ans: Cycle stealing ( The controller takes over the processor’s access cycles and performs memory
operations)
17. The registers of the controller are --------
Ans: 32 bits
18. When the process requests for a DMA transfer?
Ans: Process is temporarily suspended & Another process gets executed
19. The DMA transfer is initiated by-------------
Ans: I/O devices
20. The device which is used to connect a peripheral to bus is known as
Ans: Interface is the device which is used to connect a peripheral to bus
21. The Memory Address Register is
Ans: Contains the address of the memory location that is to be read from or stored into
22. Various storage devices used by an operating system can be arranged as follows in
increasing order of accessing speed:
Ans: Magnetic tapes → optical disks → magnetic disks → electronic disks → main memory →
cache → registers
23. On receiving an interrupt from an I/O device,the CPU does
Ans: Branches off to the interrupt service routine after completion of the current instruction
24. An interrupt in which the external device supplies its address as well as the interrupt
requests is known as
Ans: Vectored interrupt
25. The search concept used in associative memory is
Ans: Associative memory is suitable for parallel searches and is used where search time needs to be
minimized. It requires hardware support like comparators and multiplexers to implement associative
memory as it is usually present in the form of banks and a fixed length block from each of these
banks can be read simultaneously.
26. In _____ method, the word is written to the block in both the cache and main memory, in
parallel.
Ans: In write through method, the word is written to the block in both the cache and main memory,
in parallel and in write back method the word is written to the block in cache but actual update into
the corresponding location in main memory only at specified intervals or under certain conditions.
In Write Protected cache policy word cannot be modified or deleted. In direct mapping block M of
main memory maps into block M modulo n of the cache, where n is the total number of blocks in
cache.
27. The minimum time delay between the initiation of two independent memory operations is
called
Ans: Cycle time
28. Size of the main memory mainly depends on the size of -------- bus.
Ans: The size of the main memory depends on the size of the address bus of the CPU. The main
memory mainly consists of RAM and ROM, where RAM contains the current data and programs
and ROM contains permanent programs like BIOS.
29. Which memory is independent of the address bus?
Ans: The secondary memory is independent of the address bus. It increases the storage space. It is
implemented in the form of magnetic storage devices.
30. If M denotes the number of memory locations and N denotes the word size, then an
expression that denotes the storage capacity is:
Ans: M * N