The VHDL Process Block
VHDL Statements
Concurrent VHDL Statements : 1
• Can only be used inside the Architecture
Block.
Sequential VHDL Statements :
• Can only be used inside the Process Block.
1
Concurrent VHDL Statements
• Process Block
• Component Instantiation
• Concurrent Signal Assignments (using <=)
• Conditional Signal Assignment (When – Else)
• Selected Signal Assignment (With – Select)
• Generate
Concurrent VHDL Statements
• Process Block
• Component Instantiation
• Concurrent Signal Assignments (using <=)
• Conditional Signal Assignment (When – Else)
• Selected Signal Assignment (With – Select)
• Generate statement
A <= B;
Process Block
• A process statement is the main
construct in behavioral modeling that
allows you to use sequential statements
to describe the behavior of a system
over time.
• Written inside the Architecture Body
• Can have multiple process blocks
Process Block Syntax
process_name : process (sensitivity_list)
-- Declarative Section
begin
-- Body Section, where we specify our circuit behaviour
- -it can consist list of sequential statements such as:
--signal assignments
--variable assignments
--case statement
---exit statement
--if statement
--loop statement
--next statement
--null statement
--procedure call
--wait statement
end process;
Process Block Example
library ieee;
use ieee.std_logic_1164.all;
entity andGate is
port (in1, in2 : in std_logic;
out1 : out std_logic);
end andGate;
architecture BEHAV_and of andGate is
begin
and_PROCESS: process (in1, in2)
begin
if (in1 = ‘1’ and in2 = ‘1’) then
out1 <= ‘1’;
else
out1 <= ‘0’;
end if;
end process;
end BEHAV_and;
Process Block – Sensitivity List
• Sensitivity List Is a list of signals
• The process waits for one of the signals in
Sensitivity List to CHANGE state before running.
• Process Block runs only when a signal in the
sensitivity list changes state.
• In simulation all The process blocks are run once
at time 0 regardless of what is in the sensitivity list
• If the process has nothing in the sensitivity list, the
it will run over and over without stoping because it
does not have to wait for any signal, and this will
cause the simulation to hang up
Process - Example
TestProcess1: process(Sig1)
begin
Sig2 <= Sig1;
end process;
In the above example the testProcess1 will wait until sig1 changes state, then it
simply assigns sig1 to sig2
Process - Example
AND_GATE : process(A, B)
begin
C <= A and B;
end process;
In the above example the process name is AND_GATE
- the output of the AND_GATE process is the signal C which is ( A and B)
-the process waits until either input A or B changes which will change the value
of the output C
-conclusion: all inputs to a process must also be included in the sensitivity list
because we want the process to execute whenever one of its inputs change
state
Incomplete Sensitivity List
AND_GATE : process(A)
begin
Missing signal B
C <= A and B;
end process;
When A Changes When B Changes
IF statement
- The statements inside a process are executed sequentially.
- The if statement executes a sequence of statements whose sequence
depends on one or more conditions. The syntax is as follows:
if Condition1 then
-- Statement Group 1
elsif Condition2 then
-- Statement Group 2
else
-- Statement Group 3
end if;
More on the IF Statement
• If statements must be written inside process block
• The if statement cant be written directly in the architecture
if Condition1 then
-- Statement Group 1
else
-- Statement Group 2
end if;
if Condition2 then
-- Statement Group 3
end if;
Example
• The following example illustrates a Full Adder, composed of two Half Adders.
• This example also illustrates how one process can generate signals that will trigger other
processes when events on the signals in its sensitivity list occur.
• We can write the Boolean expression of a Half Adder and Full Adder as follows:
S_ha = (AB) and C_ha = AB
For the Full Adder:
Sum = (AB)Cin = S_ha Cin
Cout = (AB)Cin + AB = S_ha.Cin + C_ha
• Figure 4 illustrates how the Full Adder has been modeled
library ieee;
use ieee.std_logic_1164.all;
entity FULL_ADDER is
port (A, B, Cin : in std_logic;
Sum, Cout : out std_logic);
end FULL_ADDER;
architecture BEHAV_FA of FULL_ADDER is
signal int1, int2, int3: std_logic;
begin
-- Process P1 that defines the first half adder
P1: process (A, B)
begin
int1<= A xor B;
int2<= A and B;
end process;
-- Process P2 that defines the second half adder and the OR --
gate
P2: process (int1, int2, Cin)
begin
Sum <= int1 xor Cin;
int3 <= int1 and Cin;
Cout <= int2 or int3;
end process;
end BEHAV_FA;
- of course one could simplify the behavioral model by using a single process
Full adder Solution2 : A set of concurrent assignment
statements
• -- Behaviour Modeling
-- File : [Link]
-- Entity : FA
-- Architecture : FA_arch
-------------------------------------------------------------------------------
-- Description : FULL ADDER.
-------------------------------------------------------------------------------
--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
---------------------------------- Entity Declarations -------------------------
entity FA is
port(
A,B,Cin : in STD_LOGIC;
SUM,CARRY : out STD_LOGIC);
end FA;
architecture FA_arch of FA is
begin
SUM<= A XOR B XOR Cin;
CARRY<= (A AND B) OR (Cin AND A)OR (Cin AND B);
end FA_arch;
Registered Process
• Used to implement registers (or flip-
flops).
• Sensitivity list can only contain :
• A Clock signal (Compulsory)
• A Reset signal (Optional)
• Checks for the clock rising or falling
edge.
Flip Flop Circuit
D QOUT Q
DIN
Clk
Reset
Rst
Registered Process
TestProcess : process(Rst, Clk)
begin
if Rst = ‘1’ then
Q <= ‘0’;
elsif rising_edge(Clk) then
Q <= D;
end if
end process;
More on Registered Processes
• Signals driven by a registered process are always
outputs of flip flops.
TestProcess2 : process(Reset, Clock)
begin In this examole since The
process called
if Reset = ‘1’ then
TestProcess2 derives 3
Out1 <= ‘0’; outputs: Out1,Out2,Out3
Out2 <= ‘0’; these 3 outputs can be
Out3 <= ‘0’; implemented as the
elsif rising_edge(Clock) then outputs of 3 flip flops
Out1 <= A; Clocked Section
Out2 <= A and B;
A signal assigned here
Out3 <= A or B;
end if; will create a flip flop.
end process;
More on Registered Processes
A Out1
Clock FF1
Out2
B
Clock FF2
Out3
Clock FF3
More on Registered Processes
TestProcessGeneral : process(Reset, Clock)
begin
if Reset = ‘1’ then
Y <= ‘0’;
elsif rising_edge(Clock) then
Y <= Function(X1, X2, X3,... XN);
end if;
end process;
Combinational Y
X1 ...XN Logic
FF
Clock
Reset
Comments
• rising_edge() -> Is a function found in the
std_logic_1164 Package.
• This function returns true if there is a rising
edge of the clock signal
• falling_edge()
• This function returns true if there is a falling
edge of the clock signal
Sensitivity List
• What goes in a sensitivity list?
Combinational Process Registered Process
All signals read within Only Clock and reset.
the process.
Sensitivity List
• What goes in a sensitivity list?
Combinational Process Registered Process
All signals read within Only Clock and reset.
the process.
• Sensitivity list can be empty:
• Only in simulation!
• Then must have wait statements.
• Not synthesisable.
More on Processes
Example 1
Process A Process B
Sig1<= ‘0’; Sig1 <= ‘0’;
-we can have more than one process in the VHDL file
-but it is not allowed for more than one process to change the same signal
More on Processes
Example 1
Process A Process B
Sig1<= ‘0’; Sig1 <= ‘0’;
More on Processes
Example 2
Process A Process B
Sig1<= ‘0’; Sig2 <= ‘0’;
More on Processes
Example 3
Process A Process B
Sig1<= X; Sig2 <= X;
-it is allowed for the same signal(here it is X) to be read by more than one process
Summary
• What is a process?
• Combinational & Registered Processes.
• Writing a basic process in VHDL.
• Sensitivity list.
• If statement
• rising_edge() & falling_edge() functions.
• Hardware visualisation of a process.